DESCRIPTION:
+ GENLIB provides a C interface of a set
+- of functions usefull to create a netlist of cells or a physical layout.
++ of functions useful to create a netlist of cells or a physical layout.
+ For example given a cell library, a simple C function call is enough to
+ create an instance of a cell. The result is a netlist (or a physical
+ layout) built during the sequential execution of the C source code.
+@@ -374,7 +374,7 @@
+
+ - DESCRIPTION:
+ GENPAT is used to write digital
+- stimuli. It provides a C interface of a set of functions usefull to
++ stimuli. It provides a C interface of a set of functions useful to
+ create stimuli. It loads a C file describing patterns and run the C
+ compiler. Finally it generates a stimuli file.
+ (PAT file format).
+@@ -709,7 +709,7 @@
+ - STRENGTH
+ SYF is a good FSM synthesizer.
+ It offers most common encoding algorithms and it verifies
+- formally some very basic but usefull correctness properties.
++ formally some very basic but useful correctness properties.
+
+
+ - WEAKNESS
+diff --git a/alliance/src/documentation/overview/nmx2_y.ps b/alliance/src/documentation/overview/nmx2_y.ps
+index a45fee2..8d31b91 100644
+--- a/alliance/src/documentation/overview/nmx2_y.ps
++++ b/alliance/src/documentation/overview/nmx2_y.ps
+@@ -4,9 +4,9 @@
+ %%Creator: Rps v1.03 with l2p -color -noheader -scale=2.936567 nmx2_y
+ %SCALE=2.936567
+ % = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+-% This is the beginning of the l2p COLOR PostScript dictionnary.
++% This is the beginning of the l2p COLOR PostScript dictionary.
+ % (If you want to change colors or patterns, this is THE place to do it.)
+-% (Remember that you can substitute another PostScript dictionnary.)
++% (Remember that you can substitute another PostScript dictionary.)
+ %%Pages: 1 1
+ %%EndComments
+ %%BeginPreview: 256 64 1 64
+@@ -300,7 +300,7 @@ h neg 2 w {
+ %- - - END OF LAYER TRADUCTION - - -
+ %%EndSetup
+
+-% This is the end of the l2p COLOR PostScript dictionnary.
++% This is the end of the l2p COLOR PostScript dictionary.
+ % = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+ %%Page: 1 1
+ 1.468284 setlinewidth
+diff --git a/alliance/src/documentation/overview/overview.tex b/alliance/src/documentation/overview/overview.tex
+index e2430d0..04e7918 100644
+--- a/alliance/src/documentation/overview/overview.tex
++++ b/alliance/src/documentation/overview/overview.tex
+@@ -152,7 +152,7 @@ complete \textbf{Alliance} design framework.
+ Each \textbf{Alliance} tool therefore supports several standard \textbf{VLSI}
+ description formats : \textbf{SPICE}, \textbf{EDIF}, \textbf{VHDL}, \textbf{CIF},
+ \textbf{GDS2}.
+-In that respect, the tools ouputs are fully usable under the
++In that respect, the tools outputs are fully usable under the
+ \textbf{Compass} and \textbf{Cadence Opus} environnement, provided these
+ tools have the necessary configuration files.
+ The \textbf{Alliance} tools support a zero-default top-down design
+diff --git a/alliance/src/documentation/tutorials/place_and_route/src/amd2901/Makefile b/alliance/src/documentation/tutorials/place_and_route/src/amd2901/Makefile
+index a3b92aa..d697322 100644
+--- a/alliance/src/documentation/tutorials/place_and_route/src/amd2901/Makefile
++++ b/alliance/src/documentation/tutorials/place_and_route/src/amd2901/Makefile
+@@ -8,11 +8,11 @@
+ # \------------------------------------------------------------------/
+ #
+
+-# Standart System binary access paths.
++# Standard System binary access paths.
+ STANDART_BIN = /usr/local/bin:/usr/bin:/bin
+ STANDART_PATH = PATH=$(STANDART_BIN); export PATH
+
+-# Standart Alliance binary access paths.
++# Standard Alliance binary access paths.
+ ALLIANCE_BIN = $(ALLIANCE_TOP)/bin
+
+ # FitPath Alliance binary access paths.
+diff --git a/alliance/src/documentation/tutorials/place_and_route/src/amd2901/amd2901_core.c b/alliance/src/documentation/tutorials/place_and_route/src/amd2901/amd2901_core.c
+index 23aae48..ff37b6f 100644
+--- a/alliance/src/documentation/tutorials/place_and_route/src/amd2901/amd2901_core.c
++++ b/alliance/src/documentation/tutorials/place_and_route/src/amd2901/amd2901_core.c
+@@ -53,7 +53,7 @@ main()
+ GENLIB_LOCON("vss", IN ,"vss");
+
+
+- /* **************** Data-Path Instanciation ***************** */
++ /* **************** Data-Path Instantiation ***************** */
+
+
+ GENLIB_LOINSE("amd2901_dpt", "amd2901_dpt",
+@@ -112,7 +112,7 @@ main()
+ "vss => vss", 0);
+
+
+- /* ***************** Control Instanciation ****************** */
++ /* ***************** Control Instantiation ****************** */
+
+
+ GENLIB_LOINSE("amd2901_ctl", "ctl",
+diff --git a/alliance/src/documentation/tutorials/simulation/tex/simulation.tex b/alliance/src/documentation/tutorials/simulation/tex/simulation.tex
+index 7a7bc19..2b99a40 100644
+--- a/alliance/src/documentation/tutorials/simulation/tex/simulation.tex
++++ b/alliance/src/documentation/tutorials/simulation/tex/simulation.tex
+@@ -217,12 +217,12 @@ This directory contains two subdirectories and one Makefile :
+
+ The {\bf ALLIANCE} tools used are :
+ \begin{itemize}\itemsep=-.8ex
+-\item {\bf vasy} : {\bf VHDL} analyzer and convertor.
++\item {\bf vasy} : {\bf VHDL} analyzer and converter.
+ \item {\bf asimut} : {\bf VHDL} Compiler and Simulator.
+ \item{\bf genpat} : Procedural generator of stimuli.
+ \end{itemize}
+
+-You can obtain the detailed informations on an any
++You can obtain the detailed information on an any
+ {\bf ALLIANCE} tool by typing the command :
+
+ \begin{commandline}
+@@ -365,7 +365,7 @@ Alliance subset.
+
+ The file addaccu4.vhdl is a description of the addaccu circuit,
+ using classical {\bf VHDL} subset (with process statements,
+-IEEE 1164 VHDL types, aritmetic operators etc ...)
++IEEE 1164 VHDL types, arithmetic operators etc ...)
+
+ You can convert this description to the {\bf .vbe} file format using
+ {\bf VASY}~:
+@@ -492,7 +492,7 @@ first part of this Tutorial. The circuit will be describe in two
+ levels of hierarchy :
+
+ \begin{itemize}\itemsep=-.8ex
+-\item The first level will write the circuit like the instanciation of three blocks.
++\item The first level will write the circuit like the instantiation of three blocks.
+ \item The second level will write each of the three blocks in term
+ of elementary gates of the standard library.
+ \end{itemize}
+@@ -522,7 +522,7 @@ vectors more consequent (a hundred clock-edges).
+ However, the writing of the stimuli file directly is a tiresome work.
+ The tool {\bf genpat} enables you to undertake this work in a
+ procedural way. The language {\bf genpat} is a subset of " C " functions.
+-For more informations on genpat and the functions of the
++For more information on genpat and the functions of the
+ associated library do not hesitate to use the command:
+
+ \begin{commandline}
+@@ -581,7 +581,7 @@ Initially you must write the structural
+ description file of addaccu. This file will have the extension "
+ vst " which is the usual extension to indicate a { \bf VHDL }
+ structural file (Vhdl Structural view). This view will contain the
+-instanciation of three independent blocks:
++instantiation of three independent blocks:
+
+ \begin{description}\itemsep=-.8ex
+ \item[Block 1] : The 4 bits adder.
+@@ -633,7 +633,7 @@ adder by their structural views by modifying the {\bf CATAL} file
+ (by removing the component name ).
+
+ Each block (alu, accu, mux) must now be described like an
+-interconnection of elementary gates. The gates which are to instanciate will
++interconnection of elementary gates. The gates which are to instantiate will
+ be chosen among those available in the library of standard cells {
+ \bf SXLIB }. For the functionality of the various cells and their
+ interface, the sxlib man is available. The behavioral
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amd2901/amd2901_core.c b/alliance/src/documentation/tutorials/synthesis/src/amd2901/amd2901_core.c
+index b437b14..2487397 100644
+--- a/alliance/src/documentation/tutorials/synthesis/src/amd2901/amd2901_core.c
++++ b/alliance/src/documentation/tutorials/synthesis/src/amd2901/amd2901_core.c
+@@ -52,7 +52,7 @@ main()
+ GENLIB_LOCON("vss", IN ,"vss");
+
+
+- /* **************** Data-Path Instanciation ***************** */
++ /* **************** Data-Path Instantiation ***************** */
+
+
+ GENLIB_LOINSE("amd2901_dpt", "dpt",
+@@ -111,7 +111,7 @@ main()
+ "vss => vss", 0);
+
+
+- /* ***************** Control Instanciation ****************** */
++ /* ***************** Control Instantiation ****************** */
+
+
+ GENLIB_LOINSE("amd2901_ctl", "ctl",
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amd2901/circuit.c b/alliance/src/documentation/tutorials/synthesis/src/amd2901/circuit.c
+index 1901622..bd4943e 100644
+--- a/alliance/src/documentation/tutorials/synthesis/src/amd2901/circuit.c
++++ b/alliance/src/documentation/tutorials/synthesis/src/amd2901/circuit.c
+@@ -13,7 +13,7 @@ GENLIB_LOCON("s",OUT,"s1");
+ GENLIB_LOCON("vdd",IN,"vdd");
+ GENLIB_LOCON("vss",IN,"vss");
+
+-/* Instanciation of the logical doors */
++/* Instantiation of the logical doors */
+ GENLIB_LOINS("na2_x1","nand2","a1","c1","f1","vdd","vss",0);
+ GENLIB_LOINS("no2_x1","nor2","b1","e1","g1","vdd","vss",0);
+ GENLIB_LOINS("o2_x2","or2","d1","f1","h1","vdd","vss",0);
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amd2901/data_path.c b/alliance/src/documentation/tutorials/synthesis/src/amd2901/data_path.c
+index 7e0522a..0153a87 100644
+--- a/alliance/src/documentation/tutorials/synthesis/src/amd2901/data_path.c
++++ b/alliance/src/documentation/tutorials/synthesis/src/amd2901/data_path.c
+@@ -22,7 +22,7 @@ GENLIB_MACRO(DPGEN_NAND2, "model_nand2_4bits", F_PLACE, 4, 1);
+ GENLIB_MACRO(DPGEN_OR2, "model_or2_4bits", F_PLACE, 4);
+ GENLIB_MACRO(DPGEN_ADSB2F, "model_add2_4bits", F_PLACE, 4);
+
+-/* operators Instanciation */
++/* operators Instantiation */
+
+ GENLIB_LOINS("model_nand2_4bits", "model_nand2_4bits",
+ "v", "v", "v", "v",
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe
+index 4c4e50e..3c26c07 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe
+index a3d6482..db861c4 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe
+index 1b837e9..f1b943a 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe
+index 449ab3d..bb4ff99 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe
+index a8c5397..0be89fa 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe
+index fc3372c..d39b84a 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe
+index e25d69a..ab47b34 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe
+index 78f6d3e..275ba98 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe
+index fc95e72..6af736f 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe
+index 8a37405..bb8cac0 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe
+index 52038f5..0e1acc2 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe
+index 5ba1aab..a85ba8f 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe
+index 1ee35c3..204762e 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe
+index 671c883..0a3aceb 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe
+index 1b9901b..845ee16 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe
+index 81d04d3..a431fbb 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe
+@@ -345,7 +345,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe
+index ffd7688..6db8993 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe
+index 46b09b0..823c98b 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe
+index 4a34962..0f9ab07 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe
+index 70c302f..7bcb9c4 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe
+index 64b6028..449501d 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe
+index 0c19eae..af7520c 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe
+index c594330..323347f 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe
+index c313e4b..4e15501 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe
+index f760a47..6531ba8 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe
+index 5ba1aab..a85ba8f 100755
+--- a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe
++++ b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe
+@@ -344,7 +344,7 @@ BEGIN
+ END BLOCK;
+ --
+ --
+--- Writing RAM adress b
++-- Writing RAM address b
+ --
+
+ -- b="0000"
+diff --git a/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex b/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex
+index bf2fdde..099caee 100755
+--- a/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex
++++ b/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex
+@@ -623,7 +623,7 @@ cell.
+ %-----------------------------------------------------
+ The netlist must be validated. For that, you have { \bf ASIMUT },
+ but also the tool { \bf PROOF } which proceeds to a formal comparison of two behavioral
+- descriptions ({ \bf vbe }). The tool { \bf FLATBEH } is usefull to obtain a
++ descriptions ({ \bf vbe }). The tool { \bf FLATBEH } is useful to obtain a
+ new behavioral file starting from a { \it netlist }
+ (given a {\bf vbe} file for each leave cells of the hierarchy).
+
+diff --git a/alliance/src/dreal/src/GRD_error.c b/alliance/src/dreal/src/GRD_error.c
+index 1a3a7d0..19d2107 100644
+--- a/alliance/src/dreal/src/GRD_error.c
++++ b/alliance/src/dreal/src/GRD_error.c
+@@ -214,11 +214,13 @@ void DrealInitializeErrorMessage( Debug )
+ sprintf( DrealAllFileName, "/tmp/%s_all_%d", PACKAGE, getpid() );
+
+ DrealStreamErr = freopen( DrealErrFileName, "w+", stderr);
++//DrealStreamErr = stderr;
+ DrealStreamAll = fopen ( DrealAllFileName, "w+" );
+
+ if ( DrealNormalMode )
+ {
+ DrealStreamOut = freopen( DrealOutFileName, "w+", stdout);
++ //DrealStreamOut = stdout;
+ }
+ else
+ {
+diff --git a/alliance/src/druc/man1/druc.1 b/alliance/src/druc/man1/druc.1
+index aa3628b..6e6179a 100644
+--- a/alliance/src/druc/man1/druc.1
++++ b/alliance/src/druc/man1/druc.1
+@@ -21,9 +21,9 @@ druc \- Design Rule Checker
+ This tool replace the \fBVERSATIL\fP tool that is not anymore supported.
+ .br
+ This manual presents the layout rules for tle \fBALLIANCE\fP symbolic layout approach.
+-The rules are described in a technology file defined by the environment variable \fB RDS_TECHNO_NAME\fP (see bellow).
++The rules are described in a technology file defined by the environment variable \fB RDS_TECHNO_NAME\fP (see below).
+ .br
+-The root cell and all the instanciated cells (except the intanciated libraries cells) must be in the current directory.
++The root cell and all the instantiated cells (except the intanciated libraries cells) must be in the current directory.
+ .br
+ The default mode of \fBDRuC\fP is (currently) full flat:
+ it first flatten all the hierarchy in order to obtain a flat, rectangle level description.
+@@ -464,7 +464,7 @@ This \fBgds\fP ro \fBcif\fp file contains only rectangles detected in violation.
+ .ti 8
+ - MBK_CATA_LIB - defines the catalog directory.
+ .HP
+-See the corresponding manual pages for further informations.
++See the corresponding manual pages for further information.
+ .SH EXAMPLE
+ druc register
+ .br
+diff --git a/alliance/src/exp/doc/exp.1 b/alliance/src/exp/doc/exp.1
+index 5293208..125c30e 100644
+--- a/alliance/src/exp/doc/exp.1
++++ b/alliance/src/exp/doc/exp.1
+@@ -6,8 +6,8 @@
+ .\" Main useful commands
+ .\" --------------------
+ .\" .TH Head and Foot of page
+-.\" .SH at the line begining is a Section Header
+-.\" .SS at the line begining is a Sub-Section Header
++.\" .SH at the line beginning is a Section Header
++.\" .SS at the line beginning is a Sub-Section Header
+ .\" .TP allows to present a list of items, the nextline is the title,
+ .\" the following lines is the corpus shifted of chars.
+ .\" if is omited, the default value is 7
+@@ -15,9 +15,9 @@
+ .\" \fB is for Bold font \fP is to return to Previous font
+ .\" \fI is to underlined or to change to Italic font
+ .\" .B .I can be used for Bold or Italic, if place a the line beginning
+-.\" .br at the line begining break the line, a blank line put a blank line
++.\" .br at the line beginning break the line, a blank line put a blank line
+ .\" .nf Begins a Non-Formatted zone where each line-break is put as-is
+-.\" .fi Returns to Formatted mode .nf/.fi is usefull for example to draw tables
++.\" .fi Returns to Formatted mode .nf/.fi is useful for example to draw tables
+ .\" ---------------------------------------------------------------------------
+
+ .SH EXP
+@@ -227,7 +227,7 @@ The minimum (resp. maximum) value of its arguments.
+ .IP \(bu 3
+ [min(3.0,12.1)] \fIprint\fP 3.000
+ .IP \(bu 3
+-[min('RW_ALU.*')] \fIprint\fP min value of all variables begining by RW_ALU
++[min('RW_ALU.*')] \fIprint\fP min value of all variables beginning by RW_ALU
+ .RE
+
+ .TP
+@@ -301,7 +301,7 @@ one is empty.
+ WITDH = 2;
+ LENGTH = 25 ;
+ ]
+-this message is unchanged but all expresions are computed
++this message is unchanged but all expressions are computed
+ length_div_2 = [LENGTH/2]
+ length_mul_2 = {LENGTH*2}
+ result = [max ('leng.*')]
+@@ -311,7 +311,7 @@ this message is unchanged but all expresions are computed
+ .nf
+ # this is a test file
+
+-this message is unchanged but all expresions are computed
++this message is unchanged but all expressions are computed
+ length_div_2 = 12.500
+ length_mul_2 = 50
+ result = 12.500
+diff --git a/alliance/src/exp/src/ht.c b/alliance/src/exp/src/ht.c
+index 8e647bd..3c610d6 100644
+--- a/alliance/src/exp/src/ht.c
++++ b/alliance/src/exp/src/ht.c
+@@ -22,13 +22,13 @@ htelt_t *eltadd (htelt_t * list, char *key)
+ }
+ else if ((new_elt = malloc (sizeof (htelt_t))) == NULL)
+ {
+- perror ("add elt in dictionnary");
++ perror ("add elt in dictionary");
+ exit (1);
+ }
+ if (key)
+ if ((new_elt->KEY = strdup (key)) == NULL)
+ {
+- perror ("add elt in dictionnary");
++ perror ("add elt in dictionary");
+ exit (1);
+ }
+ new_elt->NEXT = list;
+@@ -147,7 +147,7 @@ static long hash (ht_t * ht, char *key)
+
+ if (ht == NULL)
+ {
+- fprintf (stderr, "dictionnary not allocated\n");
++ fprintf (stderr, "dictionary not allocated\n");
+ exit (1);
+ }
+ if ((key == NULL) || (length == 0))
+diff --git a/alliance/src/fmi/man1/fmi.1 b/alliance/src/fmi/man1/fmi.1
+index df7670f..c66d870 100644
+--- a/alliance/src/fmi/man1/fmi.1
++++ b/alliance/src/fmi/man1/fmi.1
+@@ -11,7 +11,7 @@ fmi
+ .SH DESCRIPTION
+ .br
+ Made to run on FSM descriptions, \fBfmi\fP supports the same subset of VHDL as syf
+-(for further informations about this subset see SYF(1) and FSM(5)).
++(for further information about this subset see SYF(1) and FSM(5)).
+ \fBfmi\fP uses a Reduced Ordered Binary Decision Diagrams representation and
+ identifies equivalent states.
+ After this step, it drives a new FSM where all equivalent states are replaced
+@@ -29,7 +29,7 @@ The default value is the current directory.
+ .br
+ .HP
+ .ti 7
+-\fIMBK_CATA_LIB\fP gives some auxiliary pathes for the FSM descriptions.
++\fIMBK_CATA_LIB\fP gives some auxiliary paths for the FSM descriptions.
+ The default value is the current directory.
+ .SH OPTIONS
+ .ti 7
+diff --git a/alliance/src/fsm/man5/fsm.5 b/alliance/src/fsm/man5/fsm.5
+index e5f40ad..6ac0a21 100644
+--- a/alliance/src/fsm/man5/fsm.5
++++ b/alliance/src/fsm/man5/fsm.5
+@@ -36,7 +36,7 @@ For the scan-path, three more signals are required :
+ - scan_out: out bit
+ .RE
+ .br
+-For a ROM implementation, the vdd and vss signals must be explicitely declared as :
++For a ROM implementation, the vdd and vss signals must be explicitly declared as :
+ .RS
+ .br
+ - rom_vdd : in bit
+@@ -50,7 +50,7 @@ The '-P' option of \fBsyf\fP(1) allows scan-path implementation.
+ Pragmas :
+ .br
+ .RS
+-A pragma is a comment that gives necessary informations to the synthesis and formal
++A pragma is a comment that gives necessary information to the synthesis and formal
+ proof tools.
+ .br
+
+@@ -99,7 +99,7 @@ The last ones for ROM implementation
+ Two different processes are used : The first process, called state process,
+ allows to describe state transition and outputs generation.
+ It is not controlled by the clock.
+-The second process is controlled by the clock and descibes the state
++The second process is controlled by the clock and describes the state
+ register and stack registers modifications.
+ .br
+ State process sensitivity list contains inputs and CURRENT_STATE, it means
+@@ -236,7 +236,7 @@ end auto;
+ .SH MULTI FSM EXAMPLE
+ .br
+ It is possible to describe in the same description two or more FSM
+-communicating each others throw internal signals as shown bellow.
++communicating each others throw internal signals as shown below.
+ It is also possible to incorporate concurrent statements using VBE(5)
+ VHDL coding style.
+ .nf
+diff --git a/alliance/src/fsp/man1/fsp.1 b/alliance/src/fsp/man1/fsp.1
+index f7dcf93..704370f 100644
+--- a/alliance/src/fsp/man1/fsp.1
++++ b/alliance/src/fsp/man1/fsp.1
+@@ -11,7 +11,7 @@ fsp
+ .SH DESCRIPTION
+ .br
+ Made to run on FSM descriptions, \fBfsp\fP supports the same subset of VHDL as syf
+-(for further informations about this subset see SYF(1) and FSM(5)).
++(for further information about this subset see SYF(1) and FSM(5)).
+ \fBfsp\fP uses a Reduced Ordered Binary Decision Diagrams representation and
+ computes the product of the two FSM descriptions.
+ After this step, it explores the resulting FSM product and proves formally the equivalence
+@@ -27,7 +27,7 @@ The default value is the current directory.
+ .br
+ .HP
+ .ti 7
+-\fIMBK_CATA_LIB\fP gives some auxiliary pathes for the FSM descriptions.
++\fIMBK_CATA_LIB\fP gives some auxiliary paths for the FSM descriptions.
+ The default value is the current directory.
+ .SH OPTIONS
+ .ti 7
+diff --git a/alliance/src/genlib/doc/genlib/man_dpgen_nand2mask.html b/alliance/src/genlib/doc/genlib/man_dpgen_nand2mask.html
+index 9ce9235..172823e 100644
+--- a/alliance/src/genlib/doc/genlib/man_dpgen_nand2mask.html
++++ b/alliance/src/genlib/doc/genlib/man_dpgen_nand2mask.html
+@@ -191,7 +191,7 @@ CLASS="EMPHASIS"
+ CLASS="EMPHASIS"
+ >ANDed with the mask
+- (suplied by constVal).
+diff --git a/alliance/src/genlib/doc/genlib/man_dpgen_nor2mask.html b/alliance/src/genlib/doc/genlib/man_dpgen_nor2mask.html
+index ed42ff8..925b9a9 100644
+--- a/alliance/src/genlib/doc/genlib/man_dpgen_nor2mask.html
++++ b/alliance/src/genlib/doc/genlib/man_dpgen_nor2mask.html
+@@ -191,7 +191,7 @@ CLASS="EMPHASIS"
+ CLASS="EMPHASIS"
+ >ORed with the mask
+- (suplied by constVal).
+diff --git a/alliance/src/genlib/doc/genlib/man_dpgen_xnor2mask.html b/alliance/src/genlib/doc/genlib/man_dpgen_xnor2mask.html
+index 5755ff4..a969082 100644
+--- a/alliance/src/genlib/doc/genlib/man_dpgen_xnor2mask.html
++++ b/alliance/src/genlib/doc/genlib/man_dpgen_xnor2mask.html
+@@ -191,7 +191,7 @@ CLASS="EMPHASIS"
+ CLASS="EMPHASIS"
+ >XORed with the mask
+- (suplied by constVal).
+diff --git a/alliance/src/genlib/doc/genlib/man_genlib.html b/alliance/src/genlib/doc/genlib/man_genlib.html
+index 1da471e..f593896 100644
+--- a/alliance/src/genlib/doc/genlib/man_genlib.html
++++ b/alliance/src/genlib/doc/genlib/man_genlib.html
+@@ -331,7 +331,7 @@ CLASS="EMPHASIS"
+ The symbolic objects are segments (wires), vias (contacts),
+- connectors (I/Os), references and instances. For more informations,
++ connectors (I/Os), references and instances. For more information,
+ see
+
+
+- See the corresponding manual pages for further informations.
++ See the corresponding manual pages for further information.
+ In order to compile and execute a genlib source file.
+ The source file must have a .c extension, but the extension should
+- not be mentionned on the command line.
++ not be mentioned on the command line.
+
The names used in genlib, as arguments to genlib functions,
+@@ -1007,7 +1007,7 @@ CLASS="EMPHASIS"
+ > [--keep-log|-l] : do not erase the log file after a successfull
++> : do not erase the log file after a successful
+ completion (the log is keeped after a faulty run).
+
if the &cmd; signal is set to &one;, the mask IS
+ applied, the output is the