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alliance/alliance-tutorials.patch
Chitlesh GOORAH 4a6d8f2cdc *** empty log message ***
2007-08-13 20:54:39 +00:00

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diff -Naur documentation/tutorials/place_and_route/tex/place_and_route.tex tutorials/place_and_route/tex/place_and_route.tex
--- documentation/tutorials/place_and_route/tex/place_and_route.tex 2004-10-16 14:51:56.000000000 +0200
+++ tutorials/place_and_route/tex/place_and_route.tex 2007-08-02 18:37:05.000000000 +0200
@@ -2,6 +2,7 @@
% $Id: place_and_route.tex,v 1.5 2004/10/16 12:51:56 fred Exp $
% $Log: place_and_route.tex,v $
% Revision 1.5 2004/10/16 12:51:56 fred
+% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007)
% Erasing the psfig include from the file, changed the font to 10 pt
% instead of 12 (sparing trees and not being payed by the thickness of
% my production) and changing font to charter since I got tired of
@@ -11,14 +12,14 @@
\documentclass{article}
\usepackage[dvips]{graphics}
\usepackage[english]{babel}
-\usepackage{doublespace}
+\usepackage{setspace}
\usepackage{epsf}
\usepackage{fancybox}
\usepackage{fancyheadings}
\usepackage{float}
\usepackage{graphicx}
\usepackage{here}
-\usepackage{isolatin1}
+\usepackage[latin1]{inputenc}
\usepackage{charter}
\usepackage{picinpar}
\usepackage{rotate}
@@ -92,7 +93,8 @@
\date{}
\author{
Frederic AK\hspace{2cm} Kai-shing LAM\\
-Modified by LJ
+Modified by LJ\\
+Modified by Chitlesh GOORAH (18/07/2007)
}
\maketitle
@@ -121,7 +123,7 @@
{2.2} inverter Diagram
-{2.3} Buffer diagram
+{2.3} Buffer diagram
{2.4} sxlib gauge
@@ -149,8 +151,8 @@
{3.8} pads placement
\\
-{4} {\bf Annexes}
-
+{4} {\bf Annexes}
+
\newpage
{\huge
PART 3 : }
@@ -158,9 +160,9 @@
{\huge
Place and route
}
-
+
All the files used in this part are located under \\
-\texttt{/tutorial/place\_and\_route/src} directory.\\
+\texttt{/usr/share/doc/alliance-doc-5.0/tutorial/place\_and\_route/src} directory.\\
This directory contents three subdirectories and one Makefile :
\begin{itemize}\itemsep=-.8ex
@@ -169,7 +171,7 @@
\item inv
\begin{itemize}\itemsep=-.8ex
\item Makefile
- \item inv.vbe : behavioral description
+ \item inv.vbe : behavioral description
\item inv\_x1.ap : inverter cell design using GRAAL
\end{itemize}
\item buffer
@@ -178,7 +180,7 @@
\item buffer.vbe : behavioral description
\item buf\_x2.ap : buffer cell design using GRAAL
\end{itemize}
-\item amd2901
+\item amd2901
\begin{itemize}\itemsep=-.8ex
\item Makefile
\item amd2901\_ctl.vbe : behavioral description of control
@@ -212,9 +214,9 @@
The predefined cells concepts, model and
hierarchy will be introduced .\\
Then this tutorial contain the methodology used in Alliance to produce
-the amd2901 physical layout that you conceived in Alliance Tutorial
+the amd2901 physical layout that you conceived in Alliance Tutorial
PART 2 "Synthesis" (All the documents used will be provided to you).
-
+
\newpage
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -225,7 +227,7 @@
%------------------------
The library can be enriched by new cells with {\bf GRAAL} editor .\\
{ \bf GRAAL } is an editor of \/{\underline{symbolic }} {\it
-layout} integrating the drawing rules checker {\bf DRUC} and also
+layout} integrating the drawing rules checker {\bf DRUC} and also
a net extractor.
The first part here aims to draw an inverter cell inv\_x1 in the shape
of a predefined cell of sxlib complyiant with provided
@@ -236,7 +238,7 @@
Some tools of Alliance use a particular technological
environment. It is indicated by the environment variable {\bf
RDS\_TECHNO\_NAME} which must be set to
-{\bf/alliance/etc/cmos.rds}
+{\bf/etc/alliance/cmos.rds}
\subsubsection{GRAAL}
%--------------------
@@ -244,7 +246,7 @@
with the menu { \bf CREATE }:
\begin{itemize}\itemsep=-.4ex
\item The ''instance'' (physical cells importation)
-\item The abutment boxes which define the cell limits
+\item The abutment boxes which define the cell limits
\item Segments: DiffN, DiffP, Poly, Alu1, Alu2... CAluX is used to specify
a possible rectangle area for the connectors.
\item VIAs or contacts: ContDiffN, ContDiffP, ContPoly and
@@ -254,10 +256,10 @@
\end{itemize}
{\bf GRAAL} uses the environment variable {\bf
-GRAAL\_TECHNO\_NAME}. It must be set to {\bf/alliance/etc/cmos.graal}.
+GRAAL\_TECHNO\_NAME}. It must be set to {\bf/etc/alliance/cmos.graal}.
Steps to follow to create a sxlib cell by respecting the sxlib gauge :
-( cf 2.4 Sxlib gauge )
+( cf 2.4 Sxlib gauge )
\begin{itemize}\itemsep=-.4ex
\item place the supply Vdd and Vss using the menu CREATE->Segment
\item place the VIAs using the menu CREATE->VIA
@@ -267,7 +269,7 @@
\item link the transistor P and the transistor N with the Poly segment using the menu CREATE->Segment
\item supply each transistor by linking them with Ndiff and Pdiff segments and VIAs contacts
\item define the cell limit with an abutment box using the menu CREATE->Abutment Box
-\end{itemize}
+\end{itemize}
\subsubsection{COUGAR}
%--------------------
@@ -276,7 +278,7 @@
with the format { \bf ap }.
To extract a netlist at transistor level, use the following command :
\begin{commandline}
- > cougar -t file1 file2
+ > cougar -t file1 file2
\end{commandline}
{ \bf COUGAR } uses the environment variables { \bf MBK\_IN\_PH }
@@ -286,14 +288,14 @@
the following environment variables: \\
\begin{commandline}
- > MBK_IN_PH = ap
- > export MBK_IN_PH
- > MBK_OUT_LO = spi
+ > MBK_IN_PH = ap
+ > export MBK_IN_PH
+ > MBK_OUT_LO = spi
> export MBK_OUT_LO
\end{commandline}
\begin{commandline}
- > cougar -t circuit circuit
+ > cougar -t circuit circuit
\end{commandline}
The resulting spice netlist can be then simulated using a SPICE simulator and a given
@@ -301,7 +303,7 @@
The schematic of the transistor neltlist can also be displayed using {\bf XSCH} :
\begin{commandline}
- > xsch -I spi -l circuit
+ > xsch -I spi -l circuit
\end{commandline}
\subsection{inverter Diagram}
@@ -341,12 +343,12 @@
\begin{itemize}\itemsep=-.4ex
\item The sxlib cells have whole 50 lambdas height and a multiple of 5 lambdas width.
-\item The supply Vdd and Vss are carried out in Calu1; they have 6 lambdas width and are
+\item The supply Vdd and Vss are carried out in Calu1; they have 6 lambdas width and are
horizontally placed in top and bottom of the cell.
\item The transistors P are placed close to the Vdd while transistors N are placed close
to the Vss.
\item Box N must have 24 lambdas height .
-\item The special segments CAluX (CAlu1, Calu2, CAlu3...) form the cell interface (PORT\_MAP)
+\item The special segments CAluX (CAlu1, Calu2, CAlu3...) form the cell interface (PORT\_MAP)
and play the role of ''flat'' connectors. They must be placed on a 5x5 grid and can be anywhere in the cell.
\item The special segments TAlux (TAlu1, TAlu2...) are used to indicate the obstacles for the
router. When you want to protect AluX segment, it is necessary to cover them
@@ -356,7 +358,7 @@
\item The boxes N and P must be polarized. { \bf It should be respectively connected to Vdd and Vss }.
\end{itemize}
-You will find a summary of these constraints on the diagram
+You will find a summary of these constraints on the diagram
\ref{Fig:gabarit}:
\begin{figure}[H]\centering
@@ -443,7 +445,7 @@
\begin{itemize}\itemsep=-.4ex
\item The data-path contains the regular parts of Amd2901, the registers
and the arithmetic logic unit.
-\item The control part contains irregular logic,
+\item The control part contains irregular logic,
the instructions decoding and the `` flags '' computation.
\end{itemize}
@@ -463,7 +465,7 @@
The data-path and the control part will be placed and routed together and not separately. \\
You will use also {\bf lvx}, the netlists comparator. When the
system is too complex it is difficult to use {\bf proof}, the
-formal comparator (calculations too long). A netlists comparison
+formal comparator (calculations too long). A netlists comparison
then is used. Test the two methods ({\bf proof} and {\bf
lvx}).
@@ -499,7 +501,7 @@
%---------------------------------
Generally, the file describing a netlist must have the same
-name as the one describing its physical layout
+name as the one describing its physical layout
(but of course the file extention is not the same).
The file amd2901\_dpt.vst (LOFIG) must correspond to the file
amd2901\_dpt.ap (PHFIG). The same applies to the file
@@ -517,7 +519,7 @@
\noindent GENLIB\_SAVE\_LOFIG()\\
This permits to generate a structural description in a { \bf
-VST } file. At the same time, { \bf genlib } will generate
+VST } file. At the same time, { \bf genlib } will generate
physical descriptions of each column in { \bf AP } files.
It is up to you to place these columns explicitly. \\
Edit again the file amd2901\_dpt.c and include the lines :\\
@@ -526,7 +528,7 @@
\noindent /* add here you placement directives !! */ \\
\noindent GENLIB\_SAVE\_PHFIG()\\
-For this placement task, you have the following {\bf GENLIB} functions :
+For this placement task, you have the following {\bf GENLIB} functions :
\begin{itemize}\itemsep=-.4ex
\item GENLIB\_PLACE()
@@ -540,12 +542,12 @@
\end{itemize}
Use {\bf GENLIB} manual. The placement of the data-path columns
-should not be done randomly. The routing feasibility and the quality
+should not be done randomly. The routing feasibility and the quality
of the resulting layout depends on it !\\
Use genlib to generate all:
\begin{commandline}
- >genlib amd2901_dpt
+ >genlib amd2901_dpt
\end{commandline}
The figure \ref{Fig:preplacement} summarizes the followed process:
@@ -568,12 +570,12 @@
%---------------------------------
In the same manner, edit agin the file amd2901\_core.c and insert
- data-path explicitly. You should not place the part controls.
+ data-path explicitly. You should not place the part controls.
This one exists only in the form of a structural description.
-It is the placer { \bf ocp } that will undertake some
+It is the placer { \bf ocp } that will undertake some
(during the placement of the heart { \bf ocp } detects which are the
-cells not placed and supplements the placement).
-Nevertheless you should reserve enough space for the cells placement
+cells not placed and supplements the placement).
+Nevertheless you should reserve enough space for the cells placement
{ \bf to the top } of the data-path.
Include the lines:\\
@@ -583,28 +585,28 @@
Space necessary to the placer to place the cells of the control part
will be determined by successive approximations. You will have to
-adjust dimensions of the heart abutment box
+adjust dimensions of the heart abutment box
(GENLIB\_DEF\_AB()).
Use the command:
\begin{commandline}
- > genlib amd2901_core
+ > genlib amd2901_core
\end{commandline}
and
\begin{commandline}
- > ocp -partial amd2901_core -ioc amd2901_core amd2901_core amd2901_core_p
+ > ocp -partial amd2901_core -ioc amd2901_core amd2901_core amd2901_core_p
\end{commandline}
The option {\bf -- partial} indicates that you give a partial
-placement of the data-path.
+placement of the data-path.
The option { \bf -- ioc } permits to specify a placement for external
-connectors described in a .ioc file.
-This file, amd2901\_core.ioc is provided to you (Modify it according
+connectors described in a .ioc file.
+This file, amd2901\_core.ioc is provided to you (Modify it according
to your predefined placement.
The connectors must be in the north and in the south of your circuit).
-The third argument is the netlist heart filename, the fourth is the
+The third argument is the netlist heart filename, the fourth is the
name of the { \bf .ap } resulting file.
The figure \ref{Fig:placement} summarize the followed process:
@@ -620,7 +622,7 @@
Routing the heart by using { \bf NERO } in the following way:
\begin{commandline}
- > nero -v -3 -p amd2901_core_p amd2901_core amd2901_core
+ > nero -v -3 -p amd2901_core_p amd2901_core amd2901_core
\end{commandline}
%The option { \bf -- place } indicates that you transmit a placement, that of the heart.
@@ -639,10 +641,10 @@
\subsection{pads placement}
%---------------------------------
-The core of the AMD2001 is completed.
+The core of the AMD2001 is completed.
We focus now on the chip with pads description, placement and routing.
Those pads allow the connection of the inputs/outputs of the core with
-the external nets of the chip.
+the external nets of the chip.
The tool {\bf ring} instanciates pads that has been specified
in a {\bf vst} netlist, place them using a file { \bf .rin }
@@ -662,7 +664,7 @@
Name it `` amd2902\_chip.rin '' and apply the command \\
\begin{commandline}
- > ring amd2901_chip amd2901_chip
+ > ring amd2901_chip amd2901_chip
\end{commandline}
We will validate the work of {\bf ring} with the tools { \bf druc
@@ -682,7 +684,7 @@
> cougar -f amd2901_chip
\end{commandline}
-Compare two netlists :
+Compare two netlists :
\begin{commandline}
> lvx vst al amd2901_chip amd2901_chip -f
\end{commandline}
@@ -698,7 +700,7 @@
the circuit on the level transistor: \\
\begin{commandline}
-> cougar -t amd2901_chip amd2901_chip
+> cougar -t amd2901_chip amd2901_chip
\end{commandline}
\\
@@ -706,7 +708,7 @@
\begin{commandline}
> make view_ctl_logic
\end{commandline}
-
+
If you want to see the data-path physical layout:
\begin{commandline}
> make view_dpt_physic
@@ -723,7 +725,7 @@
\begin{commandline}
> make view_chip_simulation
\end{commandline}
-
+
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%\newpage
diff -Naur documentation/tutorials/simulation/tex/simulation.tex tutorials/simulation/tex/simulation.tex
--- documentation/tutorials/simulation/tex/simulation.tex 2004-10-16 14:52:05.000000000 +0200
+++ tutorials/simulation/tex/simulation.tex 2007-07-18 15:47:13.000000000 +0200
@@ -2,6 +2,7 @@
% $Id: simulation.tex,v 1.5 2004/10/16 12:52:05 fred Exp $
% $Log: simulation.tex,v $
% Revision 1.5 2004/10/16 12:52:05 fred
+% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007)
% Erasing the psfig include from the file, changed the font to 10 pt
% instead of 12 (sparing trees and not being payed by the thickness of
% my production) and changing font to charter since I got tired of
@@ -13,13 +14,13 @@
\documentclass{article}
\usepackage[dvips]{graphics}
\usepackage[english]{babel}
-\usepackage{doublespace}
+\usepackage{setspace}
\usepackage{fancybox}
\usepackage{fancyheadings}
\usepackage{float}
\usepackage{graphicx}
\usepackage{here}
-\usepackage{isolatin1}
+\usepackage[latin1]{inputenc}
\usepackage{charter}
\usepackage{picinpar}
\usepackage{rotate}
@@ -96,7 +97,8 @@
\date{}
\author{Frederic AK \hspace{2cm} Kai-shing LAM\\
-Modified by LJ
+Modified by LJ\\
+Modified by Chitlesh GOORAH (18/07/2007)
}
\maketitle
@@ -171,7 +173,7 @@
}
All the files used in this part are located in the \\
-\texttt{/tutorial/simulation/src} directory.\\
+\texttt{/usr/share/doc/alliance-doc-5.0/tutorial/simulation/src} directory.\\
This directory contains two subdirectories and one Makefile :
\begin{itemize}
\item The Makefile allows you to validate automatically the entire simulation part
@@ -626,13 +628,13 @@
\bf SXLIB }. For the functionality of the various cells and their
interface, the sxlib man is available. The behavioral
description of each cell is present in \\
-{\bf /alliance/cells/sxlib }.
+{\bf \$ALLIANCE\_TOP/cells/sxlib }.
You must set the environment variable { \bf MBK\_CATA\_LIB }
to be able to reach these cells.
\begin{commandline}
- > MBK_CATA_LIB=/alliance/cells/sxlib
+ > MBK_CATA_LIB=$ALLIANCE_TOP/cells/sxlib
> export MBK_CATA_LIB
\end{commandline}
diff -Naur documentation/tutorials/start/start.tex tutorials/start/start.tex
--- documentation/tutorials/start/start.tex 2004-10-16 14:52:13.000000000 +0200
+++ tutorials/start/start.tex 2007-07-18 13:28:50.000000000 +0200
@@ -4,12 +4,13 @@
% Original Version 1.0 in text form by Francois Pecheux
% Version for Alliance releases 2.0 and up by Frederic Petrot
% Modified by czo for Alliance release 4.0 (01/2000)
-% TODO : no fully working, needs some adjustements
+% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007)
+% TODO : no fully working, needs some adjustments
% $Id: start.tex,v 1.5 2004/10/16 12:52:13 fred Exp $
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\documentclass{article}
-\usepackage{charter,doublespace,here,fancybox}
+\usepackage{charter,setspace,here,fancybox}
\textwidth 15cm
\textheight 23cm
\oddsidemargin +0.75cm
@@ -20,7 +21,7 @@
% Since it is tt, any char is fine
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\newlength{\verbatimbox}
-\settowidth{\verbatimbox}{\scriptsize\tt
+\settowidth{\verbatimbox}{\scriptsize\tt
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
}
\newenvironment{framedverbatim}
@@ -33,8 +34,8 @@
\begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}%
{\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}%
\shadowbox{\TheSbox}\normalsize\par\noindent}
-
-
+
+
%%%%%%%%%%%%%%%%%%%%%%%%
%
@@ -56,9 +57,9 @@
\begin{quote}
\em
These tutorials introduce the design flow to be used in the
-\textbf{Alliance} CAD framework for the design and verification of a
+\textbf{Alliance} CAD framework for the design and verification of a
standard cells circuit, including the pads.
-Each step of the desgin flow is supported by one or more specific
+Each step of the desgin flow is supported by one or more specific
tools, whose use is briefly explained in the tutorials.
These texts are meant to be simple and comprehensive, and are to be used
@@ -77,7 +78,7 @@
proceeding, as it describes the main steps of the design conceptually.
\section{Before starting}
-In those tutorials you will learn the practical use of the following
+In those tutorials you will learn the practical use of the following
\textbf{Alliance} tools :
In the first tutorial (simulation/ directory) :
@@ -103,30 +104,32 @@
In the third tutorial (synthesis/ directory) :
\begin{itemize}
\item \textbf{syf} : Finite state machine synthesizer.
-\item \textbf{boom} : Boolean optimization of a logic level behavioral
+\item \textbf{boom} : Boolean optimization of a logic level behavioral
description (VHDL data flow).
-\item \textbf{boog} : Mapping of a behavioral descriptiononto a standard cell
+\item \textbf{boog} : Mapping of a behavioral descriptiononto a standard cell
library.
-\item \textbf{loon} : Fanout optimizer, global optimizer and timing analyser of
+\item \textbf{loon} : Fanout optimizer, global optimizer and timing analyser of
\item \textbf{scapin} : Scan Path insertion
\item \textbf{xsch} : Graphical schematic viewer.
\end{itemize}
-If you run a \texttt{c-like} shell, like \texttt{csh} or \texttt{tcsh},
+If you run a \texttt{c-like} shell, like \texttt{csh} or \texttt{tcsh},
try to run the following command :
\begin{phraseverbatim}
-~alp/addaccu %-) source /alliance/etc/alc_env.csh
+~alp/addaccu %-) source /etc/profile.d/alc_env.csh
\end{phraseverbatim}
-Otherwise, if you run a \texttt{sh-like} shell, try to run the following
+Otherwise, if you run a \texttt{sh-like} shell, try to run the following
command :
\begin{phraseverbatim}
-~alp/addaccu %-) source /alliance/alc_env.sh
+~alp/addaccu %-) source /etc/profile.d/alc_env.sh
\end{phraseverbatim}
\\
+When a user logs in, these environment variables are automatically set from various places.
+\\
Before we proceed to the tutorial, you must make sure that the
-\textbf{Alliance} tools are readilly available when invoking them at the
+\textbf{Alliance} tools are readilly available when invoking them at the
prompt.
The prompt in represented in the following text by the symbol~:
\begin{phraseverbatim}
@@ -136,7 +139,7 @@
directory, and \texttt{\%-)} is supposed to give us courage!
\section{Execution environment set up}
-Later, before you will start examining alliance tools, you will probably want
+Later, before you will start examining alliance tools, you will probably want
to know the environment variables setup.
To see it, please enter the following command :
@@ -147,18 +150,21 @@
\begin{figure}[H]\center\leavevmode
\begin{framedverbatim}
~alp/addaccu %-) env | grep MBK
-MBK_OUT_PH=ap
-MBK_CATAL_NAME=CATAL
+MBK_IN_PH=ap
MBK_SCALE_X=100
+MBK_CATAL_NAME=CATAL
+MBK_OUT_PH=ap
+MBK_OUT_LO=vst
MBK_VSS=vss
-MBK_CATA_LIB=.:/alliance/cells/sxlib:/alliance/cells/padlib
-MBK_WORK_LIB=.
-MBK_VDD=vdd
MBK_C4_LIB=./cellsC4
+MBK_VDD=vdd
+MBK_TARGET_LIB=\$ALLIANCE\_TOP/cells/sxlib
MBK_IN_LO=vst
-MBK_IN_PH=ap
-MBK_TARGET_LIB=/alliance/cells/sxlib
-MBK_OUT_LO=vst
+MBK_WORK_LIB=.
+MBK_CATA_LIB=.:/usr/lib/alliance/cells/sxlib:/usr/lib/alliance/cells/dp_sxlib:
+/usr/lib/alliance/cells/rflib:/usr/lib/alliance/cells/ramlib:
+/usr/lib/alliance/cells/romlib:/usr/lib/alliance/cells/pxlib:
+/usr/lib/alliance/cells/padlib
\end{framedverbatim}
\caption{\label{mbk} \texttt{MBK} environment variables.}
\end{figure}
@@ -167,12 +173,12 @@
variables are documented in each tutorial.
\section{File Formats}
-One of the interesting features of \textbf{Alliance} is that different
+One of the interesting features of \textbf{Alliance} is that different
file formats can be used for both netlist and layout view.
-However,
-in the design methodology we wish to promote, some formats are
+However,
+in the design methodology we wish to promote, some formats are
recommended.
-The \texttt{vst}, structural \textbf{VHDL}, is dedicated to netlist
+The \texttt{vst}, structural \textbf{VHDL}, is dedicated to netlist
specification.
The \texttt{al} format is dedicated to extracted layout representation.
The \texttt{ap} format is the usual layout format.
diff -Naur documentation/tutorials/synthesis/src/amd2901/Makefile tutorials/synthesis/src/amd2901/Makefile
--- documentation/tutorials/synthesis/src/amd2901/Makefile 2002-07-25 14:50:18.000000000 +0200
+++ tutorials/synthesis/src/amd2901/Makefile 2007-07-18 19:34:53.000000000 +0200
@@ -2,17 +2,17 @@
all: EXAMPLE VAR CATAL02 res.pat
-VAR:
+VAR:
MBK_IN_LO=vst;export MBK_IN_LO ;\
- MBK_CATA_LIB=/asim/alliance/cells/sxlib;export MBK_CATA_LIB
+ MBK_CATA_LIB=$ALLIANCE_TOP/cells/sxlib;export MBK_CATA_LIB
CATAL01:
- echo amd2901_ctl C >CATAL
+ echo amd2901_ctl C >CATAL
echo amd2901_dpt C >>CATAL
CATAL02:
echo amd2901_dpt C >CATAL
-
+
EXAMPLE:
genlib circuit
@@ -38,7 +38,7 @@
res2.pat: amd2901_chip.vst pattern.pat amd2901_core.vst CATAL
asimut amd2901_chip pattern res2
- touch amd2901_chip.vst
+ touch amd2901_chip.vst
clean :
rm -f Makefile-* \
diff -Naur documentation/tutorials/synthesis/tex/synthesis.tex tutorials/synthesis/tex/synthesis.tex
--- documentation/tutorials/synthesis/tex/synthesis.tex 2004-10-16 14:52:17.000000000 +0200
+++ tutorials/synthesis/tex/synthesis.tex 2007-07-18 15:46:54.000000000 +0200
@@ -2,6 +2,7 @@
% $Id: synthesis.tex,v 1.4 2004/10/16 12:52:17 fred Exp $
% $Log: synthesis.tex,v $
% Revision 1.4 2004/10/16 12:52:17 fred
+% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007)
% Erasing the psfig include from the file, changed the font to 10 pt
% instead of 12 (sparing trees and not being payed by the thickness of
% my production) and changing font to charter since I got tired of
@@ -11,13 +12,13 @@
\documentclass{article}
\usepackage[dvips]{graphics}
\usepackage[english]{babel}
-\usepackage{doublespace}
+\usepackage{setspace}
\usepackage{fancybox}
\usepackage{fancyheadings}
\usepackage{float}
\usepackage{graphicx}
\usepackage{here}
-\usepackage{isolatin1}
+\usepackage[latin1]{inputenc}
\usepackage{charter}
\usepackage{picinpar}
\usepackage{rotate}
@@ -89,7 +90,8 @@
\date{}
\author{
Ak Frederic\hspace{2cm} Lam Kai-shing\\
-Modified by LJ
+Modified by LJ\\
+Modified by Chitlesh GOORAH (18/07/2007)
}
\maketitle
@@ -220,7 +222,7 @@
}
All the files used in this part are located under \\
-\texttt{/tutorial/synthesis/src} directory.\\
+\texttt{/usr/share/doc/alliance-doc-5.0/tutorial/synthesis/src} directory.\\
This directory contents four subdirectories and one Makefile :
\begin{itemize}\itemsep=-.8ex
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