Adjust linker testsuite to account for compiler changes.

Fix ppc64 TLS optimization bug with -fno-plt code.
Solution for PR 32387 Resolves: 2324491 Signed-off-by: Björn Esser <besser82@fedoraproject.org>
2024-11-26 20:15:45 +00:00 · 2024-11-26 12:13:53 +01:00 · 2024-05-03 09:54:40 +00:00 · 2024-04-29 13:03:45 +01:00 · 2024-04-05 13:00:21 +01:00
41 changed files with 167375 additions and 1477 deletions
--- a/.gitignore
+++ b/.gitignore
@ -1,8 +1,6 @@
 *.diff
 *.orig
 *.rej
-*.sed
-*.xz

 *~
 .#*
@ -63,8 +61,13 @@ stamp-*
 /mpc*
 /gmp*
 /isl*
+/binutils-2.34.0-5dfc0c955dbe912cd328fc2688e5fceb3239ac2a.tar.xz
 /binutils-2.19.50.0.1-output-format.sed
-/binutils-2.44.50-13.fc43.src.rpm
-/binutils-with-gold-2.45.50-be970c68891.tar.gz
-/binutils-with-gold-2.45.50-ba5838a98fb.tar.gz
-/binutils-2.47.50-1.fc46.src.rpm
+/binutils-2.35.tar.xz
+/binutils-2.35.1.tar.xz
+/binutils-2.36.1.tar.xz
+/binutils-2.37.tar.xz
+/binutils-2.38.tar.xz
+/binutils-2.39.tar.xz
+/binutils-2.40.tar.xz
+/binutils-2.41.tar.xz
--- a/binutils-BPF-reloc-4.patch
+++ b/binutils-BPF-reloc-4.patch
@ -0,0 +1,38 @@
+diff -rup binutils.orig/bfd/bpf-reloc.def binutils-2.41/bfd/bpf-reloc.def
+--- binutils.orig/bfd/bpf-reloc.def	2023-10-30 10:41:59.114273359 +0000
+++ binutils-2.41/bfd/bpf-reloc.def	2023-10-30 11:09:41.316109162 +0000
+@@ -72,3 +72,20 @@
+         0xffffffff,            /* src_mask */
+         0xffffffff,            /* dst_mask */
+         true)                  /* pcrel_offset */
+
+  /* R_BPF_64_NODYLD32 is not used by GNU tools - but it is generated by LLVM.
+     We provide an entry here so that tools like strip can safely handle BPF
+     binaries generated by other tools.  */
+  BPF_HOWTO (R_BPF_64_NODYLD32,	/* type */
+	 0,			/* rightshift */
+	 0,			/* size */
+	 0,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bpf_elf_generic_reloc, /* special_function */
+	 "R_BPF_64_NODYLD32",	/* name */
+	 false,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0,			/* dst_mask */
+	 false)			/* pcrel_offset */
+diff -rup binutils.orig/include/elf/bpf.h binutils-2.41/include/elf/bpf.h
+--- binutils.orig/include/elf/bpf.h	2023-10-30 10:41:59.332273599 +0000
+++ binutils-2.41/include/elf/bpf.h	2023-10-30 10:59:44.475368448 +0000
+@@ -30,8 +30,8 @@ START_RELOC_NUMBERS (elf_bpf_reloc_type)
+   RELOC_NUMBER (R_BPF_64_64,       		1)
+   RELOC_NUMBER (R_BPF_64_ABS64,    		2)
+   RELOC_NUMBER (R_BPF_64_ABS32,    		3)
+-/* R_BPF_64_NODYLD32 is not used by GNU tools.
+- * It is kept in this file to remind that the value is already taken. */
+/* R_BPF_64_NODYLD32 is not used by GNU tools - but it is generated by LLVM.
+   It is kept in this file to remind that the value is already taken.  */
+   RELOC_NUMBER (R_BPF_64_NODYLD32, 		4)
+   RELOC_NUMBER (R_BPF_64_32,      		10)
+ END_RELOC_NUMBERS (R_BPF_max)
--- a/binutils-Intel-APX-CODE_6_GOTTPOFF.patch
+++ b/binutils-Intel-APX-CODE_6_GOTTPOFF.patch
@ -0,0 +1,662 @@
+diff -rup binutils.orig/bfd/bfd-in2.h binutils-2.41/bfd/bfd-in2.h
+--- binutils.orig/bfd/bfd-in2.h	2024-04-05 10:34:23.956241281 +0100
+++ binutils-2.41/bfd/bfd-in2.h	2024-04-05 10:59:44.555106927 +0100
+@@ -3840,6 +3840,12 @@ instruction.  */
+   BFD_RELOC_X86_64_CODE_4_GOTPCRELX,
+   BFD_RELOC_X86_64_CODE_4_GOTTPOFF,
+   BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC,
+  BFD_RELOC_X86_64_CODE_5_GOTPCRELX,
+  BFD_RELOC_X86_64_CODE_5_GOTTPOFF,
+  BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC,
+  BFD_RELOC_X86_64_CODE_6_GOTPCRELX,
+  BFD_RELOC_X86_64_CODE_6_GOTTPOFF,
+  BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC,
+ 
+ /* ns32k relocations  */
+   BFD_RELOC_NS32K_IMM_8,
+diff -rup binutils.orig/bfd/elf64-x86-64.c binutils-2.41/bfd/elf64-x86-64.c
+--- binutils.orig/bfd/elf64-x86-64.c	2024-04-05 10:34:23.956241281 +0100
+++ binutils-2.41/bfd/elf64-x86-64.c	2024-04-05 10:59:44.557106930 +0100
+@@ -179,12 +179,30 @@ static reloc_howto_type x86_64_elf_howto
+   HOWTO(R_X86_64_CODE_4_GOTPC32_TLSDESC, 0, 4, 32, true, 0,
+ 	complain_overflow_bitfield, bfd_elf_generic_reloc,
+ 	"R_X86_64_CODE_4_GOTPC32_TLSDESC", false, 0, 0xffffffff, true),
+  HOWTO(R_X86_64_CODE_5_GOTPCRELX, 0, 4, 32, true, 0,
+	complain_overflow_signed, bfd_elf_generic_reloc,
+	"R_X86_64_CODE_5_GOTPCRELX", false, 0, 0xffffffff, true),
+  HOWTO(R_X86_64_CODE_5_GOTTPOFF, 0, 4, 32, true, 0,
+	complain_overflow_signed, bfd_elf_generic_reloc,
+	"R_X86_64_CODE_5_GOTTPOFF", false, 0, 0xffffffff, true),
+  HOWTO(R_X86_64_CODE_5_GOTPC32_TLSDESC, 0, 4, 32, true, 0,
+	complain_overflow_bitfield, bfd_elf_generic_reloc,
+	"R_X86_64_CODE_5_GOTPC32_TLSDESC", false, 0, 0xffffffff, true),
+  HOWTO(R_X86_64_CODE_6_GOTPCRELX, 0, 4, 32, true, 0,
+	complain_overflow_signed, bfd_elf_generic_reloc,
+	"R_X86_64_CODE_6_GOTPCRELX", false, 0, 0xffffffff, true),
+  HOWTO(R_X86_64_CODE_6_GOTTPOFF, 0, 4, 32, true, 0,
+	complain_overflow_signed, bfd_elf_generic_reloc,
+	"R_X86_64_CODE_6_GOTTPOFF", false, 0, 0xffffffff, true),
+  HOWTO(R_X86_64_CODE_6_GOTPC32_TLSDESC, 0, 4, 32, true, 0,
+	complain_overflow_bitfield, bfd_elf_generic_reloc,
+	"R_X86_64_CODE_6_GOTPC32_TLSDESC", false, 0, 0xffffffff, true),
+ 
+   /* We have a gap in the reloc numbers here.
+      R_X86_64_standard counts the number up to this point, and
+      R_X86_64_vt_offset is the value to subtract from a reloc type of
+      R_X86_64_GNU_VT* to form an index into this table.  */
+-#define R_X86_64_standard (R_X86_64_CODE_4_GOTPC32_TLSDESC + 1)
+#define R_X86_64_standard (R_X86_64_CODE_6_GOTPC32_TLSDESC + 1)
+ #define R_X86_64_vt_offset (R_X86_64_GNU_VTINHERIT - R_X86_64_standard)
+ 
+ /* GNU extension to record C++ vtable hierarchy.  */
+@@ -256,6 +274,12 @@ static const struct elf_reloc_map x86_64
+   { BFD_RELOC_X86_64_CODE_4_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX, },
+   { BFD_RELOC_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTTPOFF, },
+   { BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC, R_X86_64_CODE_4_GOTPC32_TLSDESC, },
+  { BFD_RELOC_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTPCRELX, },
+  { BFD_RELOC_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTTPOFF, },
+  { BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_5_GOTPC32_TLSDESC, },
+  { BFD_RELOC_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTPCRELX, },
+  { BFD_RELOC_X86_64_CODE_6_GOTTPOFF, R_X86_64_CODE_6_GOTTPOFF, },
+  { BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPC32_TLSDESC, },
+   { BFD_RELOC_VTABLE_INHERIT,	R_X86_64_GNU_VTINHERIT, },
+   { BFD_RELOC_VTABLE_ENTRY,	R_X86_64_GNU_VTENTRY, },
+ };
+@@ -1283,6 +1307,23 @@ elf_x86_64_check_tls_transition (bfd *ab
+ 
+       goto check_gottpoff;
+ 
+    case R_X86_64_CODE_6_GOTTPOFF:
+      /* Check transition from IE access model:
+		add %reg1, foo@gottpoff(%rip), %reg2
+		where reg1/reg2 are one of r16 to r31.  */
+
+      if (offset < 6
+	  || (offset + 4) > sec->size
+	  || contents[offset - 6] != 0x62)
+	return false;
+
+      val = bfd_get_8 (abfd, contents + offset - 2);
+      if (val != 0x01 && val != 0x03)
+	return false;
+
+      val = bfd_get_8 (abfd, contents + offset - 1);
+      return (val & 0xc7) == 5;
+
+     case R_X86_64_GOTTPOFF:
+       /* Check transition from IE access model:
+ 		mov foo@gottpoff(%rip), %reg
+@@ -1417,6 +1458,7 @@ elf_x86_64_tls_transition (struct bfd_li
+     case R_X86_64_GOTTPOFF:
+     case R_X86_64_CODE_4_GOTPC32_TLSDESC:
+     case R_X86_64_CODE_4_GOTTPOFF:
+    case R_X86_64_CODE_6_GOTTPOFF:
+       if (bfd_link_executable (info))
+ 	{
+ 	  if (h == NULL)
+@@ -1464,6 +1506,8 @@ elf_x86_64_tls_transition (struct bfd_li
+   /* Return TRUE if there is no transition.  */
+   if (from_type == to_type
+       || (from_type == R_X86_64_CODE_4_GOTTPOFF
+	  && to_type == R_X86_64_GOTTPOFF)
+      || (from_type == R_X86_64_CODE_6_GOTTPOFF
+ 	  && to_type == R_X86_64_GOTTPOFF))
+     return true;
+ 
+@@ -2177,6 +2221,7 @@ elf_x86_64_scan_relocs (bfd *abfd, struc
+ 
+ 	case R_X86_64_GOTTPOFF:
+ 	case R_X86_64_CODE_4_GOTTPOFF:
+	case R_X86_64_CODE_6_GOTTPOFF:
+ 	  if (!bfd_link_executable (info))
+ 	    info->flags |= DF_STATIC_TLS;
+ 	  /* Fall through */
+@@ -2214,6 +2259,7 @@ elf_x86_64_scan_relocs (bfd *abfd, struc
+ 		break;
+ 	      case R_X86_64_GOTTPOFF:
+ 	      case R_X86_64_CODE_4_GOTTPOFF:
+	      case R_X86_64_CODE_6_GOTTPOFF:
+ 		tls_type = GOT_TLS_IE;
+ 		break;
+ 	      case R_X86_64_GOTPC32_TLSDESC:
+@@ -2503,6 +2549,26 @@ elf_x86_64_scan_relocs (bfd *abfd, struc
+ 	    }
+ 	  break;
+ 
+	case R_X86_64_CODE_5_GOTPCRELX:
+	case R_X86_64_CODE_5_GOTTPOFF:
+	case R_X86_64_CODE_5_GOTPC32_TLSDESC:
+	case R_X86_64_CODE_6_GOTPCRELX:
+	case R_X86_64_CODE_6_GOTPC32_TLSDESC:
+	    {
+	      /* These relocations are added only for completeness and
+		 aren't be used.  */
+	      if (h)
+		name = h->root.root.string;
+	      else
+		name = bfd_elf_sym_name (abfd, symtab_hdr, isym,
+					 NULL);
+	      _bfd_error_handler
+		/* xgettext:c-format */
+		(_("%pB: unsupported relocation %s against symbol `%s'"),
+		 abfd, x86_64_elf_howto_table[r_type].name, name);
+	    }
+	  break;
+
+ 	  /* This relocation describes the C++ object vtable hierarchy.
+ 	     Reconstruct it for later use during GC.  */
+ 	case R_X86_64_GNU_VTINHERIT:
+@@ -3570,6 +3636,7 @@ elf_x86_64_relocate_section (bfd *output
+ 	case R_X86_64_TLSDESC_CALL:
+ 	case R_X86_64_GOTTPOFF:
+ 	case R_X86_64_CODE_4_GOTTPOFF:
+	case R_X86_64_CODE_6_GOTTPOFF:
+ 	  tls_type = GOT_UNKNOWN;
+ 	  if (h == NULL && local_got_offsets)
+ 	    tls_type = elf_x86_local_got_tls_type (input_bfd) [r_symndx];
+@@ -3915,6 +3982,50 @@ elf_x86_64_relocate_section (bfd *output
+ 			     contents + roff - 2);
+ 		  bfd_put_8 (output_bfd, 0xc0 | reg,
+ 			     contents + roff - 1);
+		  bfd_put_32 (output_bfd,
+			      elf_x86_64_tpoff (info, relocation),
+			      contents + roff);
+		  continue;
+		}
+	      else if (r_type == R_X86_64_CODE_6_GOTTPOFF)
+		{
+		  /* IE->LE transition:
+		     Originally it is
+		     add %reg1, foo@gottpoff(%rip), %reg2
+		     or
+		     add foo@gottpoff(%rip), %reg1, %reg2
+		     We change it into:
+		     add $foo@tpoff, %reg1, %reg2
+		   */
+		  unsigned int reg, byte1;
+		  unsigned int updated_byte1;
+
+		  if (roff < 6)
+		    goto corrupt_input;
+
+		  /* Move the R bits to the B bits in EVEX payload
+		     byte 1.  */
+		  byte1 = bfd_get_8 (input_bfd, contents + roff - 5);
+		  updated_byte1 = byte1;
+
+		  /* Set the R bits since they is inverted.  */
+		  updated_byte1 |= 1 << 7 | 1 << 4;
+
+		  /* Update the B bits from the R bits.  */
+		  if ((byte1 & (1 << 7)) == 0)
+		    updated_byte1 &= ~(1 << 5);
+		  if ((byte1 & (1 << 4)) == 0)
+		    updated_byte1 |= 1 << 3;
+
+		  reg = bfd_get_8 (input_bfd, contents + roff - 1);
+		  reg >>= 3;
+
+		  bfd_put_8 (output_bfd, updated_byte1,
+			     contents + roff - 5);
+		  bfd_put_8 (output_bfd, 0x81,
+			     contents + roff - 2);
+		  bfd_put_8 (output_bfd, 0xc0 | reg,
+			     contents + roff - 1);
+ 		  bfd_put_32 (output_bfd,
+ 			      elf_x86_64_tpoff (info, relocation),
+ 			      contents + roff);
+diff -rup binutils.orig/bfd/libbfd.h binutils-2.41/bfd/libbfd.h
+--- binutils.orig/bfd/libbfd.h	2024-04-05 10:34:23.956241281 +0100
+++ binutils-2.41/bfd/libbfd.h	2024-04-05 10:59:44.559106933 +0100
+@@ -1470,6 +1470,12 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_X86_64_CODE_4_GOTPCRELX",
+   "BFD_RELOC_X86_64_CODE_4_GOTTPOFF",
+   "BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC",
+  "BFD_RELOC_X86_64_CODE_5_GOTPCRELX",
+  "BFD_RELOC_X86_64_CODE_5_GOTTPOFF",
+  "BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC",
+  "BFD_RELOC_X86_64_CODE_6_GOTPCRELX",
+  "BFD_RELOC_X86_64_CODE_6_GOTTPOFF",
+  "BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC",
+   "BFD_RELOC_NS32K_IMM_8",
+   "BFD_RELOC_NS32K_IMM_16",
+   "BFD_RELOC_NS32K_IMM_32",
+diff -rup binutils.orig/bfd/reloc.c binutils-2.41/bfd/reloc.c
+--- binutils.orig/bfd/reloc.c	2024-04-05 10:34:23.956241281 +0100
+++ binutils-2.41/bfd/reloc.c	2024-04-05 10:59:44.561106936 +0100
+@@ -2487,6 +2487,18 @@ ENUMX
+   BFD_RELOC_X86_64_CODE_4_GOTTPOFF
+ ENUMX
+   BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
+ENUMX
+  BFD_RELOC_X86_64_CODE_5_GOTPCRELX
+ENUMX
+  BFD_RELOC_X86_64_CODE_5_GOTTPOFF
+ENUMX
+  BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC
+ENUMX
+  BFD_RELOC_X86_64_CODE_6_GOTPCRELX
+ENUMX
+  BFD_RELOC_X86_64_CODE_6_GOTTPOFF
+ENUMX
+  BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC
+ ENUMDOC
+   x86-64/elf relocations
+ 
+diff -rup binutils.orig/elfcpp/x86_64.h binutils-2.41/elfcpp/x86_64.h
+--- binutils.orig/elfcpp/x86_64.h	2024-04-05 10:34:23.969241295 +0100
+++ binutils-2.41/elfcpp/x86_64.h	2024-04-05 10:59:44.561106936 +0100
+@@ -110,6 +110,30 @@ enum
+ 					// descriptor in GOT if the
+ 					// instruction starts at 4 bytes
+ 					// before the relocation offset.
+  R_X86_64_CODE_5_GOTPCRELX = 46, // 32 bit signed PC relative offset to
+				  // GOT if the instruction starts at 5
+				  // bytes before the relocation offset,
+				  // relaxable.
+  R_X86_64_CODE_5_GOTTPOFF = 47,  // 32 bit signed PC relative offset to
+				  // GOT entry for IE symbol if the
+				  // instruction starts at 5 bytes before
+				  // the relocation offset.
+  R_X86_64_CODE_5_GOTPC32_TLSDESC = 48, // 32-bit PC relative to TLS
+					// descriptor in GOT if the
+					// instruction starts at 5 bytes
+					// before the relocation offset.
+  R_X86_64_CODE_6_GOTPCRELX = 49, // 32 bit signed PC relative offset to
+				  // GOT if the instruction starts at 6
+				  // bytes before the relocation offset,
+				  // relaxable.
+  R_X86_64_CODE_6_GOTTPOFF = 50,  // 32 bit signed PC relative offset to
+				  // GOT entry for IE symbol if the
+				  // instruction starts at 6 bytes before
+				  // the relocation offset.
+  R_X86_64_CODE_6_GOTPC32_TLSDESC = 51, // 32-bit PC relative to TLS
+					// descriptor in GOT if the
+					// instruction starts at 6 bytes
+					// before the relocation offset.
+   // GNU vtable garbage collection extensions.
+   R_X86_64_GNU_VTINHERIT = 250,
+   R_X86_64_GNU_VTENTRY = 251
+diff -rup binutils.orig/gas/config/tc-i386.c binutils-2.41/gas/config/tc-i386.c
+--- binutils.orig/gas/config/tc-i386.c	2024-04-05 10:34:23.973241300 +0100
+++ binutils-2.41/gas/config/tc-i386.c	2024-04-05 10:59:44.561106936 +0100
+@@ -3640,6 +3640,7 @@ tc_i386_fix_adjustable (fixS *fixP)
+       || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
+       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
+       || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF
+      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTTPOFF
+       || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
+       || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
+       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
+@@ -5671,10 +5672,19 @@ md_assemble (char *line)
+       for (j = i.imm_operands; j < i.operands; ++j)
+ 	switch (i.reloc[j])
+ 	  {
+	  case BFD_RELOC_X86_64_GOTTPOFF:
+	    if (i.tm.mnem_off == MN_add
+		&& i.tm.opcode_space == SPACE_EVEXMAP4
+		&& i.mem_operands == 1
+		&& i.base_reg
+		&& i.base_reg->reg_num == RegIP
+		&& i.tm.operand_types[0].bitfield.class == Reg
+		&& i.tm.operand_types[2].bitfield.class == Reg)
+	      /* Allow APX: add %reg1, foo@gottpoff(%rip), %reg2.  */
+	      break;
+	    /* Fall through.  */
+ 	  case BFD_RELOC_386_TLS_GOTIE:
+ 	  case BFD_RELOC_386_TLS_LE_32:
+-	  case BFD_RELOC_X86_64_GOTTPOFF:
+-	  case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
+ 	  case BFD_RELOC_X86_64_TLSLD:
+ 	    as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm));
+ 	    return;
+@@ -10889,6 +10899,7 @@ output_disp (fragS *insn_start_frag, off
+ 		    case BFD_RELOC_X86_64_TLSLD:
+ 		    case BFD_RELOC_X86_64_GOTTPOFF:
+ 		    case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
+		    case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
+ 		    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
+ 		    case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
+ 		    case BFD_RELOC_X86_64_TLSDESC_CALL:
+@@ -10905,9 +10916,30 @@ output_disp (fragS *insn_start_frag, off
+ 		  && !i.prefix[ADDR_PREFIX])
+ 		fixP->fx_signed = 1;
+ 
+-	      /* Set fx_tcbit3 for REX2 prefix.  */
+-	      if (is_apx_rex2_encoding ())
+-		fixP->fx_tcbit3 = 1;
+	      if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF
+		  && i.tm.opcode_space == SPACE_EVEXMAP4)
+		{
+		  /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is
+		     allowed in md_assemble.  Set fx_tcbit2 for EVEX
+		     prefix.  */
+		  fixP->fx_tcbit2 = 1;
+		  continue;
+		}
+
+	      if (i.base_reg && i.base_reg->reg_num == RegIP)
+		{
+		  if (reloc_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
+		    {
+		      /* Set fx_tcbit for REX2 prefix.  */
+		      if (is_apx_rex2_encoding ())
+			fixP->fx_tcbit = 1;
+		      continue;
+		    }
+		}
+	      /* In 64-bit, i386_validate_fix updates only (%rip)
+		 relocations.  */
+	      else if (object_64bit)
+		continue;
+ 
+ 	      /* Check for "call/jmp *mem", "mov mem, %reg",
+ 		 "test %reg, mem" and "binop mem, %reg" where binop
+@@ -10932,10 +10964,22 @@ output_disp (fragS *insn_start_frag, off
+ 		{
+ 		  if (object_64bit)
+ 		    {
+-		      fixP->fx_tcbit = i.rex != 0;
+-		      if (i.base_reg
+-			  && (i.base_reg->reg_num == RegIP))
+-		      fixP->fx_tcbit2 = 1;
+		      if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF)
+			{
+			  /* Set fx_tcbit for REX2 prefix.  */
+			  if (is_apx_rex2_encoding ())
+			    fixP->fx_tcbit = 1;
+			}
+		      else
+			{
+			  /* Set fx_tcbit3 for REX2 prefix.  */
+			  if (is_apx_rex2_encoding ())
+			    fixP->fx_tcbit3 = 1;
+			  else if (i.rex)
+			    fixP->fx_tcbit2 = 1;
+			  else
+			    fixP->fx_tcbit = 1;
+			}
+ 		    }
+ 		  else
+ 		    fixP->fx_tcbit2 = 1;
+@@ -14405,6 +14449,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
+       case BFD_RELOC_X86_64_TLSLD:
+       case BFD_RELOC_X86_64_GOTTPOFF:
+       case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
+      case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
+       case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
+       case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
+ 	value = 0; /* Fully resolved at runtime.  No addend.  */
+@@ -15980,13 +16025,27 @@ i386_validate_fix (fixS *fixp)
+ 	   && (!S_IS_DEFINED (fixp->fx_addsy)
+ 	       || S_IS_EXTERNAL (fixp->fx_addsy));
+ 
+-  if (fixp->fx_tcbit3)
+  /* BFD_RELOC_X86_64_GOTTPOFF:
+      1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF
+      2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF
+    BFD_RELOC_X86_64_GOTPC32_TLSDESC:
+      1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
+    BFD_RELOC_32_PCREL:
+      1. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX
+      2. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX
+      3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX
+      4. else -> BFD_RELOC_X86_64_GOTPCREL
+   */
+  if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF)
+     {
+-      if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF)
+      if (fixp->fx_tcbit)
+ 	fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF;
+-      else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
+-	fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC;
+      else if (fixp->fx_tcbit2)
+	fixp->fx_r_type = BFD_RELOC_X86_64_CODE_6_GOTTPOFF;
+     }
+  else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
+	   && fixp->fx_tcbit)
+    fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC;
+ #endif
+ 
+   if (fixp->fx_subsy)
+@@ -15998,15 +16057,12 @@ i386_validate_fix (fixS *fixp)
+ 	      if (!object_64bit)
+ 		abort ();
+ #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+-	      if (fixp->fx_tcbit2)
+-		{
+-		  if (fixp->fx_tcbit3)
+-		    fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX;
+-		  else
+-		    fixp->fx_r_type = (fixp->fx_tcbit
+-				       ? BFD_RELOC_X86_64_REX_GOTPCRELX
+-				       : BFD_RELOC_X86_64_GOTPCRELX);
+-		}
+	      if (fixp->fx_tcbit)
+		fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCRELX;
+	      else if (fixp->fx_tcbit2)
+		fixp->fx_r_type = BFD_RELOC_X86_64_REX_GOTPCRELX;
+	      else if (fixp->fx_tcbit3)
+		fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX;
+ 	      else
+ #endif
+ 		fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
+@@ -16132,6 +16188,7 @@ tc_gen_reloc (asection *section ATTRIBUT
+     case BFD_RELOC_X86_64_DTPOFF64:
+     case BFD_RELOC_X86_64_GOTTPOFF:
+     case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
+    case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
+     case BFD_RELOC_X86_64_TPOFF32:
+     case BFD_RELOC_X86_64_TPOFF64:
+     case BFD_RELOC_X86_64_GOTOFF64:
+@@ -16276,6 +16333,7 @@ tc_gen_reloc (asection *section ATTRIBUT
+ 	  case BFD_RELOC_X86_64_TLSLD:
+ 	  case BFD_RELOC_X86_64_GOTTPOFF:
+ 	  case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
+	  case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
+ 	  case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
+ 	  case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
+ 	  case BFD_RELOC_X86_64_TLSDESC_CALL:
+diff -rup binutils.orig/gas/testsuite/gas/i386/x86-64-gottpoff.d binutils-2.41/gas/testsuite/gas/i386/x86-64-gottpoff.d
+--- binutils.orig/gas/testsuite/gas/i386/x86-64-gottpoff.d	2024-04-05 10:34:24.078241418 +0100
+++ binutils-2.41/gas/testsuite/gas/i386/x86-64-gottpoff.d	2024-04-05 10:59:44.561106936 +0100
+@@ -16,4 +16,8 @@ Disassembly of section .text:
+  +[a-f0-9]+:	48 8b 05 00 00 00 00 	mov    0x0\(%rip\),%rax        # 2c <_start\+0x2c>	28: R_X86_64_GOTTPOFF	foo-0x4
+  +[a-f0-9]+:	d5 48 03 05 00 00 00 00 	add    0x0\(%rip\),%r16        # 34 <_start\+0x34>	30: R_X86_64_CODE_4_GOTTPOFF	foo-0x4
+  +[a-f0-9]+:	d5 48 8b 25 00 00 00 00 	mov    0x0\(%rip\),%r20        # 3c <_start\+0x3c>	38: R_X86_64_CODE_4_GOTTPOFF	foo-0x4
+ +[a-f0-9]+:	62 74 fc 10 01 05 00 00 00 00 	add    %r8,0x0\(%rip\),%r16        # 46 <_start\+0x46>	42: R_X86_64_CODE_6_GOTTPOFF	foo-0x4
+ +[a-f0-9]+:	62 f4 9c 18 03 05 00 00 00 00 	add    0x0\(%rip\),%rax,%r12        # 50 <_start\+0x50>	4c: R_X86_64_CODE_6_GOTTPOFF	foo-0x4
+ +[a-f0-9]+:	62 74 fc 10 01 05 00 00 00 00 	add    %r8,0x0\(%rip\),%r16        # 5a <_start\+0x5a>	56: R_X86_64_CODE_6_GOTTPOFF	foo-0x4
+ +[a-f0-9]+:	62 f4 9c 18 03 05 00 00 00 00 	add    0x0\(%rip\),%rax,%r12        # 64 <_start\+0x64>	60: R_X86_64_CODE_6_GOTTPOFF	foo-0x4
+ #pass
+diff -rup binutils.orig/gas/testsuite/gas/i386/x86-64-gottpoff.s binutils-2.41/gas/testsuite/gas/i386/x86-64-gottpoff.s
+--- binutils.orig/gas/testsuite/gas/i386/x86-64-gottpoff.s	2024-04-05 10:34:24.078241418 +0100
+++ binutils-2.41/gas/testsuite/gas/i386/x86-64-gottpoff.s	2024-04-05 10:59:44.561106936 +0100
+@@ -13,3 +13,13 @@ _start:
+ 
+ 	addq	r16, QWORD PTR [rip + foo@GOTTPOFF]
+ 	movq	r20, QWORD PTR [rip + foo@GOTTPOFF]
+
+	.att_syntax prefix
+
+	addq	%r8, foo@GOTTPOFF(%rip), %r16
+	addq	foo@GOTTPOFF(%rip), %rax, %r12
+
+	.intel_syntax noprefix
+
+	addq	r16, QWORD PTR [rip + foo@GOTTPOFF], r8
+	addq	r12, rax, QWORD PTR [rip + foo@GOTTPOFF]
+diff -rup binutils.orig/gold/x86_64.cc binutils-2.41/gold/x86_64.cc
+--- binutils.orig/gold/x86_64.cc	2024-04-05 10:34:24.166241517 +0100
+++ binutils-2.41/gold/x86_64.cc	2024-04-05 10:59:44.563106939 +0100
+@@ -2920,6 +2920,11 @@ Target_x86_64<size>::optimize_tls_reloc(
+       // Another Local-Dynamic reloc.
+       return tls::TLSOPT_TO_LE;
+ 
+    case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+      if (r_offset <= 6 || *(reloc_view - 6) != 0x62)
+	return tls::TLSOPT_NONE;
+      goto handle_gottpoff;
+
+     case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+       if (r_offset <= 4 || *(reloc_view - 4) != 0xd5)
+ 	return tls::TLSOPT_NONE;
+@@ -2929,6 +2934,7 @@ Target_x86_64<size>::optimize_tls_reloc(
+       // from the GOT.  If we know that we are linking against the
+       // local symbol, we can switch to Local-Exec, which links the
+       // thread offset into the instruction.
+handle_gottpoff:
+       if (is_final)
+ 	return tls::TLSOPT_TO_LE;
+       return tls::TLSOPT_NONE;
+@@ -2997,6 +3003,7 @@ Target_x86_64<size>::Scan::get_reference
+     case elfcpp::R_X86_64_DTPOFF64:
+     case elfcpp::R_X86_64_GOTTPOFF:         // Initial-exec
+     case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+    case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+     case elfcpp::R_X86_64_TPOFF32:          // Local-exec
+       return Symbol::TLS_REF;
+ 
+@@ -3362,6 +3369,7 @@ need_got:
+       // These are initial tls relocs, which are expected when linking
+     case elfcpp::R_X86_64_CODE_4_GOTPC32_TLSDESC:
+     case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+    case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+       {
+ 	section_size_type stype;
+ 	reloc_view = object->section_contents(data_shndx, &stype, true);
+@@ -3464,6 +3472,7 @@ need_got:
+ 
+ 	  case elfcpp::R_X86_64_GOTTPOFF:    // Initial-exec
+ 	  case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+	  case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+ 	    layout->set_has_static_tls();
+ 	    if (optimized_type == tls::TLSOPT_NONE)
+ 	      {
+@@ -3902,6 +3911,7 @@ Target_x86_64<size>::Scan::global(Symbol
+       // These are initial tls relocs, which are expected for global()
+     case elfcpp::R_X86_64_CODE_4_GOTPC32_TLSDESC:
+     case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+    case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+       {
+ 	section_size_type stype;
+ 	reloc_view = object->section_contents(data_shndx, &stype, true);
+@@ -3920,7 +3930,8 @@ Target_x86_64<size>::Scan::global(Symbol
+ 	// when building an executable.
+ 	const bool is_final = (gsym->final_value_is_known() ||
+ 			       ((r_type == elfcpp::R_X86_64_GOTTPOFF ||
+-				 r_type == elfcpp::R_X86_64_CODE_4_GOTTPOFF) &&
+				 r_type == elfcpp::R_X86_64_CODE_4_GOTTPOFF||
+				 r_type == elfcpp::R_X86_64_CODE_6_GOTTPOFF) &&
+ 			        gsym->is_undefined() &&
+ 				parameters->options().output_is_executable()));
+ 	size_t r_offset = reloc.get_r_offset();
+@@ -4006,6 +4017,7 @@ Target_x86_64<size>::Scan::global(Symbol
+ 
+ 	  case elfcpp::R_X86_64_GOTTPOFF:    // Initial-exec
+ 	  case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+	  case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+ 	    layout->set_has_static_tls();
+ 	    if (optimized_type == tls::TLSOPT_NONE)
+ 	      {
+@@ -4608,6 +4620,7 @@ Target_x86_64<size>::Relocate::relocate(
+     case elfcpp::R_X86_64_DTPOFF64:
+     case elfcpp::R_X86_64_GOTTPOFF:         // Initial-exec
+     case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+    case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+     case elfcpp::R_X86_64_TPOFF32:          // Local-exec
+       this->relocate_tls(relinfo, target, relnum, rela, r_type, gsym, psymval,
+ 			 view, address, view_size);
+@@ -4894,6 +4907,7 @@ Target_x86_64<size>::Relocate::relocate_
+ 
+     case elfcpp::R_X86_64_GOTTPOFF:         // Initial-exec
+     case elfcpp::R_X86_64_CODE_4_GOTTPOFF:
+    case elfcpp::R_X86_64_CODE_6_GOTTPOFF:
+       if (gsym != NULL
+ 	  && gsym->is_undefined()
+ 	  && parameters->options().output_is_executable())
+@@ -5308,11 +5322,19 @@ Target_x86_64<size>::Relocate::tls_ie_to
+ 
+   // movq foo@gottpoff(%rip),%reg  ==>  movq $YY,%reg
+   // addq foo@gottpoff(%rip),%reg  ==>  addq $YY,%reg
+  // addq %reg1,foo@gottpoff(%rip),%reg2  ==>  addq $YY,%reg1,%reg2
+  // addq foo@gottpoff(%rip),%reg1,%reg2  ==>  addq $YY,%reg1,%reg2
+ 
+-  tls::check_range(relinfo, relnum, rela.get_r_offset(), view_size, -3);
+  int off1;
+  if (r_type == elfcpp::R_X86_64_CODE_6_GOTTPOFF)
+    off1 = -5;
+  else
+    off1 = -3;
+
+  tls::check_range(relinfo, relnum, rela.get_r_offset(), view_size, off1);
+   tls::check_range(relinfo, relnum, rela.get_r_offset(), view_size, 4);
+ 
+-  unsigned char op1 = view[-3];
+  unsigned char op1 = view[off1];
+   unsigned char op2 = view[-2];
+   unsigned char op3 = view[-1];
+   unsigned char reg = op3 >> 3;
+@@ -5350,7 +5372,7 @@ Target_x86_64<size>::Relocate::tls_ie_to
+ 	  view[-1] = 0x80 | reg | (reg << 3);
+ 	}
+     }
+-  else
+  else if (r_type == elfcpp::R_X86_64_CODE_4_GOTTPOFF)
+     {
+       if (op2 == 0x8b)
+ 	op2 = 0xc7;
+@@ -5362,6 +5384,23 @@ Target_x86_64<size>::Relocate::tls_ie_to
+       view[-2] = op2;
+       view[-1] = 0xc0 | reg;
+     }
+  else
+    {
+      unsigned char updated_op1 = op1;
+
+      // Set the R bits since they is inverted.
+      updated_op1 |= 1 << 7 | 1 << 4;
+
+      // Update the B bits from the R bits.
+      if ((op1 & (1 << 7)) == 0)
+	updated_op1 &= ~(1 << 5);
+      if ((op1 & (1 << 4)) == 0)
+	updated_op1 |= 1 << 3;
+
+      view[-5] = updated_op1;
+      view[-2] = 0x81;
+      view[-1] = 0xc0 | reg;
+    }
+ 
+   if (tls_segment != NULL)
+     value -= tls_segment->memsz();
+diff -rup binutils.orig/include/elf/x86-64.h binutils-2.41/include/elf/x86-64.h
+--- binutils.orig/include/elf/x86-64.h	2024-04-05 10:34:24.174241526 +0100
+++ binutils-2.41/include/elf/x86-64.h	2024-04-05 10:59:44.563106939 +0100
+@@ -92,6 +92,26 @@ START_RELOC_NUMBERS (elf_x86_64_reloc_ty
+      /* 32 bit signed pc relative offset to TLS descriptor in the GOT if
+ 	instruction starts at 4 bytes before the relocation offset.  */
+      RELOC_NUMBER (R_X86_64_CODE_4_GOTPC32_TLSDESC, 45)
+     /* Load from 32 bit signed pc relative offset to GOT entry if the
+	instruction starts at 5 bytes before the relocation offset,
+	relaxable.  */
+     RELOC_NUMBER (R_X86_64_CODE_5_GOTPCRELX, 46)
+     /* 32 bit signed pc relative offset to TLS descriptor in the GOT if
+	instruction starts at 5 bytes before the relocation offset.  */
+     RELOC_NUMBER (R_X86_64_CODE_5_GOTPC32_TLSDESC, 47)
+    /* PC relative offset to IE GOT entry if the instruction starts at
+       5 bytes before the relocation offset.  */
+     RELOC_NUMBER (R_X86_64_CODE_5_GOTTPOFF, 48)
+     /* Load from 32 bit signed pc relative offset to GOT entry if the
+	instruction starts at 6 bytes before the relocation offset,
+	relaxable.  */
+     RELOC_NUMBER (R_X86_64_CODE_6_GOTPCRELX, 49)
+    /* PC relative offset to IE GOT entry if the instruction starts at
+       6 bytes before the relocation offset.  */
+     RELOC_NUMBER (R_X86_64_CODE_6_GOTTPOFF, 50)
+     /* 32 bit signed pc relative offset to TLS descriptor in the GOT if
+	instruction starts at 6 bytes before the relocation offset.  */
+     RELOC_NUMBER (R_X86_64_CODE_6_GOTPC32_TLSDESC, 51)
+      RELOC_NUMBER (R_X86_64_GNU_VTINHERIT, 250)       /* GNU C++ hack  */
+      RELOC_NUMBER (R_X86_64_GNU_VTENTRY, 251)         /* GNU C++ hack  */
+ END_RELOC_NUMBERS (R_X86_64_max)
--- a/binutils-Intel-APX-part-1-fixes.patch
+++ b/binutils-Intel-APX-part-1-fixes.patch
@ -0,0 +1,871 @@
+diff -rupN binutils.orig/opcodes/i386-dis.c binutils-2.41/opcodes/i386-dis.c
+--- binutils.orig/opcodes/i386-dis.c	2024-02-12 15:55:21.578572835 +0000
+++ binutils-2.41/opcodes/i386-dis.c	2024-02-12 15:56:38.828623964 +0000
+@@ -8824,6 +8824,8 @@ get_valid_dis386 (const struct dis386 *d
+       break;
+ 
+     case USE_3BYTE_TABLE:
+      if (ins->last_rex2_prefix >= 0)
+	return &err_opcode;
+       if (!fetch_code (ins->info, ins->codep + 2))
+ 	return &err_opcode;
+       vindex = *ins->codep++;
+@@ -9540,8 +9542,6 @@ print_insn (bfd_vma pc, disassemble_info
+   /* REX2.M in rex2 prefix represents map0 or map1.  */
+   if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
+     {
+-      unsigned char threebyte;
+-
+       if (!ins.rex2)
+ 	{
+ 	  ins.codep++;
+@@ -9549,17 +9549,15 @@ print_insn (bfd_vma pc, disassemble_info
+ 	    goto fetch_error_out;
+ 	}
+ 
+-      threebyte = *ins.codep;
+-      dp = &dis386_twobyte[threebyte];
+-      ins.need_modrm = twobyte_has_modrm[threebyte];
+-      ins.codep++;
+      dp = &dis386_twobyte[*ins.codep];
+      ins.need_modrm = twobyte_has_modrm[*ins.codep];
+     }
+   else
+     {
+       dp = &dis386[*ins.codep];
+       ins.need_modrm = onebyte_has_modrm[*ins.codep];
+-      ins.codep++;
+     }
+  ins.codep++;
+ 
+   /* Save sizeflag for printing the extra ins.prefixes later before updating
+      it for mnemonic and operand processing.  The prefix names depend
+diff -rupN binutils.orig/opcodes/i386-opc.tbl binutils-2.41/opcodes/i386-opc.tbl
+--- binutils.orig/opcodes/i386-opc.tbl	2024-02-12 15:55:21.578572835 +0000
+++ binutils-2.41/opcodes/i386-opc.tbl	2024-02-12 15:56:28.955616704 +0000
+@@ -1586,7 +1586,9 @@ vandnp<sd>, 0x<sd:ppfx>55, AVX, Modrm|Ve
+ vandp<sd>, 0x<sd:ppfx>54, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+ vblendp<sd>, 0x660c | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+ vblendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+-vbroadcastf128, 0x661a, AVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
+vbroadcastf128, 0x661a, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
+// vbroadcastf32x4 in disguise (see vround{p,s}{s,d} comment)
+vbroadcastf128, 0x661a, APX_F&AVX512VL, Modrm|EVex256|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
+ vbroadcastsd, 0x6619, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM }
+ vbroadcastss, 0x6618, AVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM }
+ vcmp<frel>p<sd>, 0x<sd:ppfx>c2/0x<frel:imm>, AVX, Modrm|<frel:comm>|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+@@ -1614,7 +1616,9 @@ vdivp<sd>, 0x<sd:ppfx>5e, AVX, Modrm|Vex
+ vdivs<sd>, 0x<sd:spfx>5e, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+ vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+ vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+-vextractf128, 0x6619, AVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
+vextractf128, 0x6619, AVX, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
+// vextractf32x4 in disguise (see vround{p,s}{s,d} comment)
+vextractf128, 0x6619, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex }
+ vextractps, 0x6617, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex }
+ vextractps, 0x6617, x64&(AVX|AVX512F), RegMem|Vex128|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 }
+ vhaddpd, 0x667c, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+@@ -1622,6 +1626,8 @@ vhaddps, 0xf27c, AVX, Modrm|Vex|Space0F|
+ vhsubpd, 0x667d, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+ vhsubps, 0xf27d, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+ vinsertf128, 0x6618, AVX, Modrm|Vex256|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
+// vinsertf32x4 in disguise (see vround{p,s}{s,d} comment)
+vinsertf128, 0x6618, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|NoSuf, { Imm8, Xmmword|Unspecified|BaseIndex, RegYMM, RegYMM }
+ vinsertps, 0x6621, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+ vlddqu, 0xf2f0, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
+ vldmxcsr, 0xae/2, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex }
+@@ -1792,8 +1798,8 @@ vroundp<sd>, 0x6608 | <sd:opc>, AVX, Mod
+ vrounds<sd>, 0x660a | <sd:opc>, AVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+ // These are really clones of VRNDSCALE{P,S}{S,D}, with broadcast, masking, SAE,
+ // 512-bit operand size, and register sources dropped.
+-vroundp<sd>, 0x6608 | <sd:opc>, APX_F, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
+-vrounds<sd>, 0x660a | <sd:opc>, APX_F, Modrm|EVexLIG|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
+vroundp<sd>, 0x6608 | <sd:opc>, APX_F&AVX512VL, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
+vrounds<sd>, 0x660a | <sd:opc>, APX_F&AVX512F, Modrm|EVexLIG|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
+ vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+ vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+ vshufp<sd>, 0x<sd:ppfx>c6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+@@ -1828,7 +1834,9 @@ vpmovzxwq, 0x6634, AVX2|AVX512VL, Modrm|
+ 
+ // New AVX2 instructions.
+ 
+-vbroadcasti128, 0x665A, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
+vbroadcasti128, 0x665A, AVX2, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
+// vbroadcasti32x4 in disguise (see vround{p,s}{s,d} comment)
+vbroadcasti128, 0x665a, APX_F&AVX512VL, Modrm|EVex256|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
+ vbroadcastsd, 0x6619, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM }
+ vbroadcastss, 0x6618, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+ vpblendd, 0x6602, AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+@@ -1840,8 +1848,12 @@ vpermd, 0x6636, AVX2|AVX512F, Modrm|Vex2
+ vpermpd, 0x6601, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
+ vpermps, 0x6616, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
+ vpermq, 0x6600, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
+-vextracti128, 0x6639, AVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
+vextracti128, 0x6639, AVX2, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
+// vextracti32x4 in disguise (see vround{p,s}{s,d} comment)
+vextracti128, 0x6639, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex }
+ vinserti128, 0x6638, AVX2, Modrm|Vex256|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
+// vinserti32x4 in disguise (see vround{p,s}{s,d} comment)
+vinserti128, 0x6638, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|NoSuf, { Imm8, Xmmword|Unspecified|BaseIndex, RegYMM, RegYMM }
+ vpmaskmov<dq>, 0x668e, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
+ vpmaskmov<dq>, 0x668c, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+ vpsllv<dq>, 0x6647, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+@@ -2115,12 +2127,12 @@ xcryptofb, 0xf30fa7e8, PadLock, NoSuf|Re
+ xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {}
+ 
+ // Multy-precision Add Carry, rdseed instructions.
+-adcx, 0x6666, ADX&APX_F, C|Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
+adcx, 0x6666, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
+ adcx, 0x660f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+-adcx, 0x6666, ADX&APX_F, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+-adox, 0xf366, ADX&APX_F, C|Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
+adcx, 0x6666, ADX&APX_F, Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+adox, 0xf366, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
+ adox, 0xf30f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+-adox, 0xf366, ADX&APX_F, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+adox, 0xf366, ADX&APX_F, Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+ rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 }
+ 
+ // SMAP instructions.
+@@ -3098,11 +3110,11 @@ rdsspq, 0xf30f1e/1, SHSTK&x64, Modrm|NoS
+ saveprevssp, 0xf30f01ea, SHSTK, NoSuf, {}
+ rstorssp, 0xf30f01/5, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex }
+ wrssd, 0x0f38f6, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex }
+-wrssd, 0x66, SHSTK&APX_F, Modrm|IgnoreSize|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex }
+wrssd, 0x66, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex }
+ wrssq, 0x0f38f6, SHSTK&x64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex }
+ wrssq, 0x66, SHSTK&APX_F, Modrm|NoSuf|Size64|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex }
+ wrussd, 0x660f38f5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex }
+-wrussd, 0x6665, SHSTK&APX_F, Modrm|IgnoreSize|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex }
+wrussd, 0x6665, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex }
+ wrussq, 0x660f38f5, SHSTK&x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex }
+ wrussq, 0x6665, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex }
+ setssbsy, 0xf30f01e8, SHSTK, NoSuf, {}
+@@ -3152,7 +3164,7 @@ cldemote, 0x0f1c/0, CLDEMOTE, Modrm|Anys
+ // MOVDIR[I,64B] instructions.
+ 
+ movdiri, 0xf38f9, MOVDIRI, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+-movdiri, 0xf9, MOVDIRI&APX_F, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+movdiri, 0xf9, MOVDIRI&APX_F, Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+ movdir64b, 0x660f38f8, MOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+ movdir64b, 0x66f8, MOVDIR64B&APX_F, Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 }
+ 
+@@ -3459,13 +3471,13 @@ wrmsrlist, 0xf30f01c6, MSRLIST, NoSuf, {
+ // RAO-INT instructions.
+ 
+ aadd, 0xf38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+-aadd, 0xfc, RAO_INT&APX_F, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aadd, 0xfc, RAO_INT&APX_F, Modrm|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+ aand, 0x660f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+-aand, 0x66fc, RAO_INT&APX_F, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aand, 0x66fc, RAO_INT&APX_F, Modrm|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+ aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+-aor, 0xf2fc, RAO_INT&APX_F, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aor, 0xf2fc, RAO_INT&APX_F, Modrm|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+ axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+-axor, 0xf3fc, RAO_INT&APX_F, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+axor, 0xf3fc, RAO_INT&APX_F, Modrm|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+ 
+ // RAO-INT instructions end.
+ 
+diff -rupN binutils.orig/opcodes/i386-tbl.h binutils-2.41/opcodes/i386-tbl.h
+--- binutils.orig/opcodes/i386-tbl.h	2024-02-12 15:55:21.578572835 +0000
+++ binutils-2.41/opcodes/i386-tbl.h	2024-02-12 16:42:52.494835094 +0000
+@@ -15372,6 +15372,16 @@ static const insn_template i386_optab[]
+ 	  1, 0, 0, 0, 1, 0 } },
+       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vbroadcastf128, 0x1a, 2, SPACE_0F38, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0 },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+   { MN_vbroadcastsd, 0x19, 2, SPACE_0F38, None,
+     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+@@ -20804,6 +20814,18 @@ static const insn_template i386_optab[]
+ 	  0, 1, 0, 0, 0, 0 } },
+       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ 	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vextractf128, 0x19, 3, SPACE_0F3A, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0 },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+   { MN_vextractps, 0x17, 3, SPACE_0F3A, None,
+     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
+@@ -20890,6 +20912,20 @@ static const insn_template i386_optab[]
+ 	  0, 1, 0, 0, 0, 0 } },
+       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vinsertf128, 0x18, 4, SPACE_0F3A, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 1, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0 },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+   { MN_vinsertps, 0x21, 4, SPACE_0F3A, None,
+     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+@@ -25296,7 +25332,7 @@ static const insn_template i386_optab[]
+     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0,
+       0 },
+-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 0, 0, 0, 0, 0 } },
+@@ -25320,7 +25356,7 @@ static const insn_template i386_optab[]
+     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0,
+       0 },
+-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 0, 0, 0, 0, 0 } },
+@@ -25346,7 +25382,7 @@ static const insn_template i386_optab[]
+     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 1, 1, 1, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
+       0 },
+-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0 } },
+     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 0, 0, 0, 0, 0 } },
+@@ -25374,7 +25410,7 @@ static const insn_template i386_optab[]
+     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 1, 2, 1, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+       0 },
+-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0 } },
+     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 0, 0, 0, 0, 0 } },
+@@ -25884,6 +25920,16 @@ static const insn_template i386_optab[]
+ 	  1, 0, 0, 0, 1, 0 } },
+       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vbroadcasti128, 0x5a, 2, SPACE_0F38, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0 },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+   { MN_vpblendd, 0x02, 4, SPACE_0F3A, None,
+     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+@@ -26106,6 +26152,18 @@ static const insn_template i386_optab[]
+ 	  0, 1, 0, 0, 0, 0 } },
+       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ 	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vextracti128, 0x39, 3, SPACE_0F3A, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0 },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+   { MN_vinserti128, 0x38, 4, SPACE_0F3A, None,
+     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+@@ -26120,6 +26178,20 @@ static const insn_template i386_optab[]
+ 	  0, 1, 0, 0, 0, 0 } },
+       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vinserti128, 0x38, 4, SPACE_0F3A, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 1, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0 },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+   { MN_vpmaskmovd, 0x8e, 3, SPACE_0F38, None,
+     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+@@ -30933,7 +31005,7 @@ static const insn_template i386_optab[]
+     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 	  0, 0, 0, 0, 0, 0 } } } },
+   { MN_adcx, 0x66, 3, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 2, 0, 1, 0, 0, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 61, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -30955,7 +31027,7 @@ static const insn_template i386_optab[]
+       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 0, 0 } } } },
+   { MN_adcx, 0x66, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 61, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -30965,7 +31037,7 @@ static const insn_template i386_optab[]
+       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 0, 0 } } } },
+   { MN_adox, 0x66, 3, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 2, 0, 2, 0, 0, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 61, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -30987,7 +31059,7 @@ static const insn_template i386_optab[]
+       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 0, 0 } } } },
+   { MN_adox, 0x66, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 61, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -37497,7 +37569,7 @@ static const insn_template i386_optab[]
+       { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+ 	  0, 0, 0, 0, 1, 0 } } } },
+   { MN_wrssd, 0x66, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -37537,7 +37609,7 @@ static const insn_template i386_optab[]
+       { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+ 	  0, 0, 0, 0, 1, 0 } } } },
+   { MN_wrussd, 0x65, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -37697,7 +37769,7 @@ static const insn_template i386_optab[]
+       { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 1, 0 } } } },
+   { MN_movdiri, 0xf9, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 120, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -41093,7 +41165,7 @@ static const insn_template i386_optab[]
+       { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 1, 0 } } } },
+   { MN_aadd, 0xfc, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 95, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -41113,7 +41185,7 @@ static const insn_template i386_optab[]
+       { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 1, 0 } } } },
+   { MN_aand, 0xfc, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 95, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -41133,7 +41205,7 @@ static const insn_template i386_optab[]
+       { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 1, 0 } } } },
+   { MN_aor, 0xfc, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 3, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 95, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -41153,7 +41225,7 @@ static const insn_template i386_optab[]
+       { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0,
+ 	  0, 0, 0, 0, 1, 0 } } } },
+   { MN_axor, 0xfc, 2, SPACE_EVEXMAP4, None,
+-    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+       0, 0, 0, 0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       0 },
+     { { 95, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+@@ -41398,203 +41470,203 @@ static const i386_op_off_t i386_op_sets[
+   1540, 1541, 1542, 1544, 1546, 1548, 1550, 1552,
+   1554, 1556, 1558, 1560, 1562, 1564, 1566, 1568,
+   1570, 1572, 1574, 1576, 1578, 1579, 1580, 1582,
+-  1584, 1586, 1588, 1589, 1590, 1591, 1592, 1593,
+-  1596, 1598, 1600, 1602, 1604, 1606, 1608, 1610,
+-  1612, 1614, 1616, 1618, 1620, 1622, 1624, 1626,
+-  1628, 1630, 1632, 1634, 1636, 1638, 1640, 1642,
+-  1644, 1646, 1648, 1650, 1652, 1654, 1656, 1658,
+-  1660, 1662, 1664, 1666, 1668, 1670, 1672, 1674,
+-  1676, 1678, 1680, 1682, 1684, 1686, 1688, 1690,
+-  1692, 1694, 1696, 1698, 1700, 1702, 1704, 1706,
+-  1708, 1710, 1712, 1714, 1716, 1718, 1720, 1722,
+-  1724, 1726, 1728, 1730, 1732, 1734, 1736, 1738,
+-  1740, 1742, 1744, 1746, 1748, 1750, 1752, 1754,
+-  1756, 1758, 1760, 1762, 1764, 1766, 1768, 1770,
+-  1772, 1774, 1776, 1778, 1780, 1782, 1784, 1786,
+-  1788, 1790, 1792, 1794, 1796, 1798, 1800, 1802,
+-  1804, 1806, 1808, 1810, 1812, 1814, 1816, 1818,
+-  1820, 1822, 1824, 1826, 1828, 1830, 1832, 1834,
+-  1836, 1838, 1840, 1842, 1844, 1846, 1848, 1850,
+-  1852, 1854, 1856, 1858, 1860, 1862, 1864, 1866,
+-  1868, 1870, 1872, 1874, 1876, 1878, 1880, 1882,
+-  1884, 1886, 1888, 1890, 1892, 1894, 1896, 1898,
+-  1900, 1902, 1904, 1906, 1908, 1910, 1912, 1914,
+-  1916, 1918, 1920, 1922, 1924, 1926, 1928, 1930,
+-  1932, 1934, 1936, 1938, 1940, 1942, 1944, 1946,
+-  1948, 1950, 1952, 1954, 1956, 1958, 1960, 1962,
+-  1964, 1966, 1968, 1970, 1972, 1974, 1976, 1978,
+-  1983, 1985, 1990, 1992, 1994, 1999, 2001, 2003,
+-  2005, 2010, 2012, 2014, 2016, 2020, 2026, 2028,
+-  2033, 2035, 2037, 2039, 2041, 2043, 2045, 2047,
+-  2049, 2051, 2052, 2053, 2054, 2056, 2057, 2058,
+-  2059, 2060, 2061, 2063, 2064, 2065, 2066, 2068,
+-  2070, 2072, 2074, 2076, 2078, 2080, 2082, 2084,
+-  2086, 2088, 2090, 2092, 2096, 2097, 2098, 2100,
+-  2104, 2108, 2110, 2114, 2118, 2119, 2120, 2122,
+-  2124, 2126, 2128, 2133, 2137, 2141, 2143, 2145,
+-  2147, 2149, 2150, 2152, 2154, 2156, 2158, 2160,
+-  2162, 2164, 2166, 2168, 2170, 2172, 2174, 2176,
+-  2178, 2180, 2182, 2184, 2186, 2188, 2190, 2192,
+-  2194, 2195, 2196, 2198, 2200, 2201, 2202, 2205,
+-  2208, 2211, 2214, 2216, 2218, 2220, 2222, 2224,
+-  2226, 2227, 2228, 2229, 2231, 2235, 2237, 2239,
+-  2245, 2249, 2250, 2251, 2252, 2253, 2254, 2255,
+-  2256, 2260, 2262, 2264, 2268, 2270, 2272, 2274,
+-  2276, 2278, 2280, 2282, 2284, 2286, 2288, 2290,
+-  2292, 2294, 2296, 2297, 2300, 2303, 2308, 2313,
+-  2316, 2319, 2322, 2325, 2330, 2335, 2338, 2341,
+-  2343, 2345, 2347, 2349, 2351, 2353, 2355, 2356,
+-  2358, 2360, 2362, 2364, 2366, 2367, 2368, 2369,
+-  2373, 2377, 2379, 2383, 2387, 2391, 2395, 2399,
+-  2401, 2405, 2407, 2409, 2411, 2413, 2415, 2417,
+-  2419, 2421, 2422, 2424, 2426, 2428, 2430, 2432,
+-  2434, 2436, 2438, 2439, 2440, 2441, 2443, 2445,
+-  2447, 2449, 2450, 2451, 2453, 2455, 2457, 2459,
+-  2461, 2463, 2464, 2466, 2468, 2470, 2472, 2473,
+-  2474, 2476, 2478, 2480, 2482, 2484, 2486, 2488,
+-  2490, 2491, 2492, 2493, 2494, 2497, 2500, 2502,
+-  2505, 2506, 2507, 2509, 2510, 2512, 2513, 2514,
+-  2516, 2518, 2519, 2520, 2521, 2522, 2523, 2526,
+-  2531, 2536, 2541, 2546, 2549, 2554, 2559, 2561,
+-  2563, 2565, 2567, 2568, 2569, 2571, 2573, 2575,
+-  2577, 2579, 2581, 2583, 2584, 2585, 2586, 2587,
+-  2588, 2589, 2594, 2599, 2600, 2601, 2602, 2603,
+-  2604, 2605, 2606, 2607, 2608, 2609, 2610, 2611,
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+  3486, 3487, 3488, 3489, 3490, 3491, 3492, 3493,
+  3495, 3497, 3499, 3501, 3502, 3503, 3504, 3505,
+  3506, 3507, 3508, 3509, 3510, 3511, 3512, 3513,
+  3514, 3515, 3516, 3518, 3519, 3521, 3524, 3526,
+  3527, 3528, 3530, 3532, 3533, 3534, 3535, 3536,
+  3537, 3538, 3540, 3542, 3544, 3546, 3547, 3548,
+  3549, 3550, 3551, 3552, 3553, 3554, 3555, 3557,
+  3559, 3560, 3562, 3564, 3565, 3570, 3572, 3574,
+  3575, 3576, 3577, 3578, 3579, 3580, 3581, 3583,
+  3585, 3586, 3587, 3588, 3590, 3593, 3596, 3599,
+  3601, 3602, 3603, 3604, 3605, 3606, 3607, 3608,
+  3609, 3610, 3611, 3612, 3613, 3614, 3615, 3616,
+  3617, 3618, 3619, 3620, 3621, 3623, 3625, 3627,
+  3629, 3631, 3633, 3635, 3637, 3639, 3641, 3642,
+  3643, 3644, 3645, 3646, 3647, 3648, 3649, 3650,
+  3651, 3652, 3653, 3654, 3655, 3656, 3657, 3658,
+  3659, 3660, 3661, 3662, 3663, 3664, 3665, 3666,
+  3667, 3668, 3669, 3670, 3671, 3672, 3673, 3674,
+  3675, 3676, 3677, 3678, 3679, 3680, 3681, 3682,
+  3683, 3684, 3685, 3686, 3687, 3688, 3689, 3690,
+  3691, 3692, 3693, 3694, 3695, 3696, 3697, 3698,
+  3699, 3700, 3701, 3702, 3703, 3704, 3705, 3706,
+  3707, 3708, 3709, 3710, 3711, 3712, 3713, 3714,
+  3715, 3716, 3717, 3718, 3719, 3720, 3721, 3722,
+  3723, 3724, 3725, 3726, 3727, 3728, 3729, 3730,
+  3731, 3732, 3733, 3734, 3735, 3736, 3737, 3738,
+  3739, 3740, 3741, 3742, 3743, 3744, 3745, 3746,
+  3747, 3748, 3749, 3750, 3751, 3752, 3753, 3756,
+  3757, 3758, 3761, 3762, 3763, 3765, 3766, 3767,
+  3768, 3770, 3771, 3772, 3773, 3775, 3776, 3777,
+  3778, 3781, 3782, 3783, 3784, 3785, 3788, 3791,
+  3794, 3797, 3800, 3801, 3802, 3803, 3804, 3806,
+  3808, 3809, 3810, 3811, 3814, 3817, 3820, 3823,
+  3826, 3827, 3828, 3829, 3831, 3832, 3833, 3834,
+  3836, 3837, 3838, 3839, 3840, 3841, 3842, 3843,
+  3844, 3845, 3846, 3847, 3848, 3849, 3850, 3851,
+  3852, 3853, 3854, 3855, 3856, 3857, 3858, 3859,
+  3860, 3861, 3862, 3863, 3864, 3865, 3866, 3867,
+  3868, 3869, 3870, 3871, 3872, 3873, 3874, 3875,
+  3877, 3879, 3881, 3883, 3885, 3886, 3887, 3890,
+  3893, 3894, 3895, 3896, 3897
+ };
+ 
+ /* i386 mnemonics table.  */
+diff -rupN binutils.orig/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d binutils-2.41/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d
+--- binutils.orig/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d	2024-02-12 15:55:20.792572349 +0000
+++ binutils-2.41/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d	2024-02-12 15:56:07.355601128 +0000
+@@ -158,6 +158,12 @@ Disassembly of section \.text:
+ [	 ]*[a-f0-9]+:[	 ]*62 da 7f 08 4b b4 87 23 01 00 00[	 ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\]
+ [	 ]*[a-f0-9]+:[	 ]*62 da 7d 08 4b b4 87 23 01 00 00[	 ]+tileloaddt1 tmm6,\[r31\+rax\*4\+0x123\]
+ [	 ]*[a-f0-9]+:[	 ]*62 da 7e 08 4b b4 87 23 01 00 00[	 ]+tilestored[	 ]+\[r31\+rax\*4\+0x123\],tmm6
+[	 ]*[a-f0-9]+:[	 ]*62 fa 7d 28 1a 18[	 ]+vbroadcastf32x4 ymm3,XMMWORD PTR \[r16\]
+[	 ]*[a-f0-9]+:[	 ]*62 fa 7d 28 5a 18[	 ]+vbroadcasti32x4 ymm3,XMMWORD PTR \[r16\]
+[	 ]*[a-f0-9]+:[	 ]*62 fb 7d 28 19 18 01[	 ]+vextractf32x4 XMMWORD PTR \[r16\],ymm3,(0x)?1
+[	 ]*[a-f0-9]+:[	 ]*62 fb 7d 28 39 18 01[	 ]+vextracti32x4 XMMWORD PTR \[r16\],ymm3,(0x)?1
+[	 ]*[a-f0-9]+:[	 ]*62 7b 65 28 18 00 01[	 ]+vinsertf32x4 ymm8,ymm3,XMMWORD PTR \[r16\],(0x)?1
+[	 ]*[a-f0-9]+:[	 ]*62 7b 65 28 38 00 01[	 ]+vinserti32x4 ymm8,ymm3,XMMWORD PTR \[r16\],(0x)?1
+ [	 ]*[a-f0-9]+:[	 ]*62 db fd 08 09 30 01[	 ]+vrndscalepd xmm6,XMMWORD PTR \[r24\],(0x)?1
+ [	 ]*[a-f0-9]+:[	 ]*62 db 7d 08 08 30 02[	 ]+vrndscaleps xmm6,XMMWORD PTR \[r24\],(0x)?2
+ [	 ]*[a-f0-9]+:[	 ]*62 db cd 08 0b 18 03[	 ]+vrndscalesd xmm3,xmm6,QWORD PTR \[r24\],(0x)?3
+diff -rupN binutils.orig/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d binutils-2.41/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d
+--- binutils.orig/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d	2024-02-12 15:55:20.792572349 +0000
+++ binutils-2.41/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d	2024-02-12 15:56:07.355601128 +0000
+@@ -158,6 +158,12 @@ Disassembly of section \.text:
+ [	 ]*[a-f0-9]+:[	 ]*62 da 7f 08 4b b4 87 23 01 00 00[	 ]+tileloadd[	 ]+0x123\(%r31,%rax,4\),%tmm6
+ [	 ]*[a-f0-9]+:[	 ]*62 da 7d 08 4b b4 87 23 01 00 00[	 ]+tileloaddt1[	 ]+0x123\(%r31,%rax,4\),%tmm6
+ [	 ]*[a-f0-9]+:[	 ]*62 da 7e 08 4b b4 87 23 01 00 00[	 ]+tilestored[	 ]+%tmm6,0x123\(%r31,%rax,4\)
+[	 ]*[a-f0-9]+:[	 ]*62 fa 7d 28 1a 18[	 ]+vbroadcastf32x4 \(%r16\),%ymm3
+[	 ]*[a-f0-9]+:[	 ]*62 fa 7d 28 5a 18[	 ]+vbroadcasti32x4 \(%r16\),%ymm3
+[	 ]*[a-f0-9]+:[	 ]*62 fb 7d 28 19 18 01[	 ]+vextractf32x4 \$(0x)?1,%ymm3,\(%r16\)
+[	 ]*[a-f0-9]+:[	 ]*62 fb 7d 28 39 18 01[	 ]+vextracti32x4 \$(0x)?1,%ymm3,\(%r16\)
+[	 ]*[a-f0-9]+:[	 ]*62 7b 65 28 18 00 01[	 ]+vinsertf32x4 \$(0x)?1,\(%r16\),%ymm3,%ymm8
+[	 ]*[a-f0-9]+:[	 ]*62 7b 65 28 38 00 01[	 ]+vinserti32x4 \$(0x)?1,\(%r16\),%ymm3,%ymm8
+ [	 ]*[a-f0-9]+:[	 ]*62 db fd 08 09 30 01[	 ]+vrndscalepd \$0x1,\(%r24\),%xmm6
+ [	 ]*[a-f0-9]+:[	 ]*62 db 7d 08 08 30 02[	 ]+vrndscaleps \$0x2,\(%r24\),%xmm6
+ [	 ]*[a-f0-9]+:[	 ]*62 db cd 08 0b 18 03[	 ]+vrndscalesd \$0x3,\(%r24\),%xmm6,%xmm3
+diff -rupN binutils.orig/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s binutils-2.41/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s
+--- binutils.orig/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s	2024-02-12 15:55:20.792572349 +0000
+++ binutils-2.41/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s	2024-02-12 15:56:07.356601129 +0000
+@@ -152,6 +152,12 @@ _start:
+ 	tileloadd	0x123(%r31,%rax,4),%tmm6
+ 	tileloaddt1	0x123(%r31,%rax,4),%tmm6
+ 	tilestored	%tmm6,0x123(%r31,%rax,4)
+	vbroadcastf128	(%r16),%ymm3
+	vbroadcasti128	(%r16),%ymm3
+	vextractf128	$1,%ymm3,(%r16)
+	vextracti128	$1,%ymm3,(%r16)
+	vinsertf128	$1,(%r16),%ymm3,%ymm8
+	vinserti128	$1,(%r16),%ymm3,%ymm8
+ 	vroundpd $1,(%r24),%xmm6
+ 	vroundps $2,(%r24),%xmm6
+ 	vroundsd $3,(%r24),%xmm6,%xmm3
--- a/binutils-Intel-APX-part-1.patch
+++ b/binutils-Intel-APX-part-1.patch
--- a/binutils-LTO-restore-wrapper-symbol.patch
+++ b/binutils-LTO-restore-wrapper-symbol.patch
@ -1,154 +0,0 @@
-From 3221c470f0765886a49a1a3d2ec602e4104a377b Mon Sep 17 00:00:00 2001
-From: "H.J. Lu" <hjl.tools@gmail.com>
-Date: Fri, 2 Aug 2024 19:52:00 -0700
-Subject: [PATCH] LTO: Restore the wrapper symbol check for standard function
-
-Call unwrap_hash_lookup to restore the wrapper symbol check for standard
-function since reference to standard function may not show up in LTO
-symbol table:
-
-[hjl@gnu-tgl-3 pr31956-3]$ nm foo.o
-00000000 T main
-         U __real_malloc
-00000000 T __wrap_malloc
-[hjl@gnu-tgl-3 pr31956-3]$  lto-dump -list foo.o
-Type   Visibility  Size  Name
-function  default     0  malloc
-function  default     0  __real_malloc
-function  default     3  main
-function  default     5  __wrap_malloc
-[hjl@gnu-tgl-3 pr31956-3]$ make
-gcc -O2 -flto -Wall   -c -o foo.o foo.c
-gcc -Wl,--wrap=malloc -O2 -flto -Wall -o x foo.o
-/usr/local/bin/ld: /tmp/ccsPW0a9.ltrans0.ltrans.o: in function `main':
-<artificial>:(.text.startup+0xa): undefined reference to `__wrap_malloc'
-collect2: error: ld returned 1 exit status
-make: *** [Makefile:22: x] Error 1
-[hjl@gnu-tgl-3 pr31956-3]$
-
-Also add a test to verify that the unused wrapper is removed.
-
-	PR ld/31956
-	* plugin.c (get_symbols): Restore the wrapper symbol check for
-	standard function.
-	* testsuite/ld-plugin/lto.exp: Run the malloc test and the
-	unused test.
-	* testsuite/ld-plugin/pr31956c.c: New file.
-	* testsuite/ld-plugin/pr31956d.c: New file.
-	* testsuite/ld-plugin/pr31956d.d: New file.
-
-Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
---
- ld/plugin.c                       | 14 ++++++++++++--
- ld/testsuite/ld-plugin/lto.exp    | 16 ++++++++++++++++
- ld/testsuite/ld-plugin/pr31956c.c | 19 +++++++++++++++++++
- ld/testsuite/ld-plugin/pr31956d.c |  7 +++++++
- ld/testsuite/ld-plugin/pr31956d.d |  4 ++++
- 5 files changed, 58 insertions(+), 2 deletions(-)
- create mode 100644 ld/testsuite/ld-plugin/pr31956c.c
- create mode 100644 ld/testsuite/ld-plugin/pr31956d.c
- create mode 100644 ld/testsuite/ld-plugin/pr31956d.d
-
-diff --git a/ld/plugin.c b/ld/plugin.c
-index 03ee9880d10..51c4765cc5b 100644
--- a/ld/plugin.c
-+++ b/ld/plugin.c
-@@ -778,8 +778,18 @@ get_symbols (const void *handle, int nsyms, struct ld_plugin_symbol *syms,
- 	{
- 	  blhe = h;
- 	  /* Check if a symbol is a wrapper symbol.  */
-	  if (blhe && blhe->wrapper_symbol)
-	    wrap_status = wrapper;
-+	  if (blhe)
-+	    {
-+	      if (blhe->wrapper_symbol)
-+		wrap_status = wrapper;
-+	      else if (link_info.wrap_hash != NULL)
-+		{
-+		  struct bfd_link_hash_entry *unwrap
-+		    = unwrap_hash_lookup (&link_info, (bfd *) abfd, blhe);
-+		  if (unwrap != NULL && unwrap != h)
-+		    wrap_status = wrapper;
-+		}
-+	    }
- 	}
-       else
- 	{
-diff --git a/ld/testsuite/ld-plugin/lto.exp b/ld/testsuite/ld-plugin/lto.exp
-index ad59e2abd61..1a8c3736307 100644
--- a/ld/testsuite/ld-plugin/lto.exp
-+++ b/ld/testsuite/ld-plugin/lto.exp
-@@ -546,6 +546,22 @@ set lto_link_elf_tests [list \
-    {} \
-    "pr31956b" \
-   ] \
-+  [list \
-+   "PR ld/31956 (malloc)" \
-+   "-Wl,--wrap=malloc" \
-+   "-O2 -flto" \
-+   {pr31956c.c} \
-+   {} \
-+   "pr31956c" \
-+  ] \
-+  [list \
-+   "PR ld/31956 (unused)" \
-+   "-Wl,--wrap=parse_line" \
-+   "-O2 -flto" \
-+   {pr31956d.c} \
-+   {{"nm" {} "pr31956d.d"}} \
-+   "pr31956d" \
-+  ] \
-   [list \
-    "Build pr30281.so" \
-    "-shared -Wl,--version-script,pr30281.t \
-diff --git a/ld/testsuite/ld-plugin/pr31956c.c b/ld/testsuite/ld-plugin/pr31956c.c
-new file mode 100644
-index 00000000000..4a46b2b49a8
--- /dev/null
-+++ b/ld/testsuite/ld-plugin/pr31956c.c
-@@ -0,0 +1,19 @@
-+#include <stdlib.h>
-+
-+extern void *__real_malloc (size_t);
-+
-+void *
-+__wrap_malloc (size_t n)
-+{
-+  if (n == 0)
-+    return NULL;
-+  else
-+    return __real_malloc (n);
-+};
-+
-+int
-+main (void)
-+{
-+  void *ptr = malloc (30);
-+  return ptr == NULL ? 1 : 0;
-+}
-diff --git a/ld/testsuite/ld-plugin/pr31956d.c b/ld/testsuite/ld-plugin/pr31956d.c
-new file mode 100644
-index 00000000000..cb7f2d50643
--- /dev/null
-+++ b/ld/testsuite/ld-plugin/pr31956d.c
-@@ -0,0 +1,7 @@
-+void __wrap_parse_line(void) {};
-+
-+int
-+main (void)
-+{
-+  return 0;
-+}
-diff --git a/ld/testsuite/ld-plugin/pr31956d.d b/ld/testsuite/ld-plugin/pr31956d.d
-new file mode 100644
-index 00000000000..b579cdc7353
--- /dev/null
-+++ b/ld/testsuite/ld-plugin/pr31956d.d
-@@ -0,0 +1,4 @@
-+#failif
-+#...
-+[0-9a-f]+ T .*parse_line
-+#...
-- 
-2.45.2
-
--- a/binutils-aarch64-big-bti-programs.patch
+++ b/binutils-aarch64-big-bti-programs.patch
@ -0,0 +1,139 @@
+diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
+index 4592bd6da27..4faf642b422 100644
+--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
+@@ -3675,7 +3675,7 @@ group_sections (struct elf_aarch64_link_hash_table *htab,
+ /* True if the inserted stub does not break BTI compatibility.  */
+ 
+ static bool
+-aarch64_bti_stub_p (bfd *input_bfd,
+aarch64_bti_stub_p (struct bfd_link_info *info,
+ 		    struct elf_aarch64_stub_hash_entry *stub_entry)
+ {
+   /* Stubs without indirect branch are BTI compatible.  */
+@@ -3685,12 +3685,22 @@ aarch64_bti_stub_p (bfd *input_bfd,
+ 
+   /* Return true if the target instruction is compatible with BR x16.  */
+ 
+  struct elf_aarch64_link_hash_table *globals = elf_aarch64_hash_table (info);
+   asection *section = stub_entry->target_section;
+   bfd_byte loc[4];
+   file_ptr off = stub_entry->target_value;
+   bfd_size_type count = sizeof (loc);
+ 
+-  if (!bfd_get_section_contents (input_bfd, section, loc, off, count))
+  /* PLT code is not generated yet, so treat it specially.
+     Note: Checking elf_aarch64_obj_tdata.plt_type & PLT_BTI is not
+     enough because it only implies BTI in the PLT0 and tlsdesc PLT
+     entries. Normal PLT entries don't have BTI in a shared library
+     (because such PLT is normally not called indirectly and adding
+     the BTI when a stub targets a PLT would change the PLT layout
+     and it's too late for that here).  */
+  if (section == globals->root.splt)
+    memcpy (loc, globals->plt_entry, count);
+  else if (!bfd_get_section_contents (section->owner, section, loc, off, count))
+     return false;
+ 
+   uint32_t insn = bfd_getl32 (loc);
+@@ -4637,11 +4647,24 @@ _bfd_aarch64_add_call_stub_entries (bool *stub_changed, bfd *output_bfd,
+ 
+ 	      /* A stub with indirect jump may break BTI compatibility, so
+ 		 insert another stub with direct jump near the target then.  */
+-	      if (need_bti && !aarch64_bti_stub_p (input_bfd, stub_entry))
+	      if (need_bti && !aarch64_bti_stub_p (info, stub_entry))
+ 		{
+		  id_sec_bti = htab->stub_group[sym_sec->id].link_sec;
+
+		  /* If the stub with indirect jump and the BTI stub are in
+		     the same stub group: change the indirect jump stub into
+		     a BTI stub since a direct branch can reach the target.
+		     The BTI landing pad is still needed in case another
+		     stub indirectly jumps to it.  */
+		  if (id_sec_bti == id_sec)
+		    {
+		      stub_entry->stub_type = aarch64_stub_bti_direct_branch;
+		      goto skip_double_stub;
+		    }
+
+ 		  stub_entry->double_stub = true;
+ 		  htab->has_double_stub = true;
+-		  id_sec_bti = htab->stub_group[sym_sec->id].link_sec;
+
+ 		  stub_name_bti =
+ 		    elfNN_aarch64_stub_name (id_sec_bti, sym_sec, hash, irela);
+ 		  if (!stub_name_bti)
+@@ -4653,33 +4676,41 @@ _bfd_aarch64_add_call_stub_entries (bool *stub_changed, bfd *output_bfd,
+ 		  stub_entry_bti =
+ 		    aarch64_stub_hash_lookup (&htab->stub_hash_table,
+ 					      stub_name_bti, false, false);
+-		  if (stub_entry_bti == NULL)
+-		    stub_entry_bti =
+-		      _bfd_aarch64_add_stub_entry_in_group (stub_name_bti,
+-							    sym_sec, htab);
+-		  if (stub_entry_bti == NULL)
+		  if (stub_entry_bti != NULL)
+		    BFD_ASSERT (stub_entry_bti->stub_type
+				== aarch64_stub_bti_direct_branch);
+		  else
+ 		    {
+-		      free (stub_name);
+-		      free (stub_name_bti);
+-		      goto error_ret_free_internal;
+-		    }
+-
+-		  stub_entry_bti->target_value = sym_value + irela->r_addend;
+-		  stub_entry_bti->target_section = sym_sec;
+-		  stub_entry_bti->stub_type = aarch64_stub_bti_direct_branch;
+-		  stub_entry_bti->h = hash;
+-		  stub_entry_bti->st_type = st_type;
+		      stub_entry_bti =
+			_bfd_aarch64_add_stub_entry_in_group (stub_name_bti,
+							      sym_sec, htab);
+		      if (stub_entry_bti == NULL)
+			{
+			  free (stub_name);
+			  free (stub_name_bti);
+			  goto error_ret_free_internal;
+			}
+ 
+-		  len = sizeof (BTI_STUB_ENTRY_NAME) + strlen (sym_name);
+-		  stub_entry_bti->output_name = bfd_alloc (htab->stub_bfd, len);
+-		  if (stub_entry_bti->output_name == NULL)
+-		    {
+-		      free (stub_name);
+-		      free (stub_name_bti);
+-		      goto error_ret_free_internal;
+		      stub_entry_bti->target_value =
+			sym_value + irela->r_addend;
+		      stub_entry_bti->target_section = sym_sec;
+		      stub_entry_bti->stub_type =
+			aarch64_stub_bti_direct_branch;
+		      stub_entry_bti->h = hash;
+		      stub_entry_bti->st_type = st_type;
+
+		      len = sizeof (BTI_STUB_ENTRY_NAME) + strlen (sym_name);
+		      stub_entry_bti->output_name = bfd_alloc (htab->stub_bfd,
+							       len);
+		      if (stub_entry_bti->output_name == NULL)
+			{
+			  free (stub_name);
+			  free (stub_name_bti);
+			  goto error_ret_free_internal;
+			}
+		      snprintf (stub_entry_bti->output_name, len,
+				BTI_STUB_ENTRY_NAME, sym_name);
+ 		    }
+-		  snprintf (stub_entry_bti->output_name, len,
+-			    BTI_STUB_ENTRY_NAME, sym_name);
+ 
+ 		  /* Update the indirect call stub to target the BTI stub.  */
+ 		  stub_entry->target_value = 0;
+@@ -4688,7 +4719,7 @@ _bfd_aarch64_add_call_stub_entries (bool *stub_changed, bfd *output_bfd,
+ 		  stub_entry->h = NULL;
+ 		  stub_entry->st_type = STT_FUNC;
+ 		}
+-
+skip_double_stub:
+ 	      *stub_changed = true;
+ 	    }
+ 
--- a/binutils-aarch64-small-plt0.patch
+++ b/binutils-aarch64-small-plt0.patch
@ -1,12 +0,0 @@
--- binutils.orig/bfd/elfnn-aarch64.c	2025-02-07 13:42:20.961333141 +0000
-+++ binutils-with-gold-2.44/bfd/elfnn-aarch64.c	2025-02-07 13:42:29.781353740 +0000
-@@ -10162,7 +10162,8 @@ elfNN_aarch64_init_small_plt0_entry (bfd
-   /* PR 26312: Explicitly set the sh_entsize to 0 so that
-      consumers do not think that the section contains fixed
-      sized objects.  */
-  elf_section_data (htab->root.splt->output_section)->this_hdr.sh_entsize = 0;
-+  if (elf_section_data (htab->root.splt->output_section) != NULL)
-+    elf_section_data (htab->root.splt->output_section)->this_hdr.sh_entsize = 0;
- 
-   plt_got_2nd_ent = (htab->root.sgotplt->output_section->vma
- 		  + htab->root.sgotplt->output_offset
--- a/binutils-archive-DT_SYMTAB.patch
+++ b/binutils-archive-DT_SYMTAB.patch
@ -0,0 +1,37 @@
+--- binutils.orig/bfd/elflink.c
+++ binutils-2.41/bfd/elflink.c
+@@ -3571,12 +3571,6 @@ elf_link_is_defined_archive_symbol (bfd * abfd, carsym * symdef)
+   if (! bfd_check_format (abfd, bfd_object))
+     return false;
+ 
+-  if (elf_use_dt_symtab_p (abfd))
+-    {
+-      bfd_set_error (bfd_error_wrong_format);
+-      return false;
+-    }
+-
+   /* Select the appropriate symbol table.  If we don't know if the
+      object file is an IR object, give linker LTO plugin a chance to
+      get the correct symbol table.  */
+@@ -3592,10 +3586,19 @@ elf_link_is_defined_archive_symbol (bfd * abfd, carsym * symdef)
+       abfd = abfd->plugin_dummy_bfd;
+       hdr = &elf_tdata (abfd)->symtab_hdr;
+     }
+-  else if ((abfd->flags & DYNAMIC) == 0 || elf_dynsymtab (abfd) == 0)
+-    hdr = &elf_tdata (abfd)->symtab_hdr;
+   else
+-    hdr = &elf_tdata (abfd)->dynsymtab_hdr;
+    {
+      if (elf_use_dt_symtab_p (abfd))
+	{
+	  bfd_set_error (bfd_error_wrong_format);
+	  return false;
+	}
+
+      if ((abfd->flags & DYNAMIC) == 0 || elf_dynsymtab (abfd) == 0)
+	hdr = &elf_tdata (abfd)->symtab_hdr;
+      else
+	hdr = &elf_tdata (abfd)->dynsymtab_hdr;
+    }
+ 
+   symcount = hdr->sh_size / get_elf_backend_data (abfd)->s->sizeof_sym;
--- a/binutils-big-merge.patch
+++ b/binutils-big-merge.patch
@ -0,0 +1,29 @@
+--- binutils.orig/bfd/merge.c	2023-11-07 09:49:56.923358543 +0000
+++ binutils-2.41/bfd/merge.c	2023-11-07 09:51:47.031552039 +0000
+@@ -167,7 +167,7 @@ static bool
+ sec_merge_maybe_resize (struct sec_merge_hash *table, unsigned added)
+ {
+   struct bfd_hash_table *bfdtab = &table->table;
+-  if (bfdtab->count + added > table->nbuckets * 2 / 3)
+  if (bfdtab->count + added > table->nbuckets / 3 * 2)
+     {
+       unsigned i;
+       unsigned long newnb = table->nbuckets * 2;
+@@ -175,7 +175,7 @@ sec_merge_maybe_resize (struct sec_merge
+       uint64_t *newl;
+       unsigned long alloc;
+ 
+-      while (bfdtab->count + added > newnb * 2 / 3)
+      while (bfdtab->count + added > newnb / 3 * 2)
+ 	{
+ 	  newnb *= 2;
+ 	  if (!newnb)
+@@ -240,7 +240,7 @@ sec_merge_hash_insert (struct sec_merge_
+   hashp->u.suffix = NULL;
+   hashp->next = NULL;
+   // We must not need resizing, otherwise _index is wrong
+-  BFD_ASSERT (bfdtab->count + 1 <= table->nbuckets * 2 / 3);
+  BFD_ASSERT (bfdtab->count + 1 <= table->nbuckets / 3 * 2);
+   bfdtab->count++;
+   table->key_lens[_index] = (hash << 32) | (uint32_t)len;
+   table->values[_index] = hashp;
--- a/binutils-demangler-updates.patch
+++ b/binutils-demangler-updates.patch
@ -0,0 +1,374 @@
+--- binutils.orig/include/demangle.h	2024-01-17 09:54:10.945686323 +0000
+++ binutils-2.41/include/demangle.h	2024-01-17 09:54:55.696760281 +0000
+@@ -1,5 +1,5 @@
+ /* Defs for interface to demanglers.
+-   Copyright (C) 1992-2023 Free Software Foundation, Inc.
+   Copyright (C) 1992-2024 Free Software Foundation, Inc.
+ 
+    This program is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Library General Public License
+@@ -448,6 +448,8 @@ enum demangle_component_type
+   DEMANGLE_COMPONENT_TRANSACTION_SAFE,
+   /* A cloned function.  */
+   DEMANGLE_COMPONENT_CLONE,
+  /* A member-like friend function.  */
+  DEMANGLE_COMPONENT_FRIEND,
+   DEMANGLE_COMPONENT_NOEXCEPT,
+   DEMANGLE_COMPONENT_THROW_SPEC,
+ 
+@@ -464,6 +466,8 @@ enum demangle_component_type
+   DEMANGLE_COMPONENT_TEMPLATE_TEMPLATE_PARM,
+   DEMANGLE_COMPONENT_TEMPLATE_PACK_PARM,
+ 
+  DEMANGLE_COMPONENT_CONSTRAINTS,
+
+   /* A builtin type with argument.  This holds the builtin type
+      information.  */
+   DEMANGLE_COMPONENT_EXTENDED_BUILTIN_TYPE
+diff -rup binutils.orig/libiberty/cp-demangle.c binutils-2.41/libiberty/cp-demangle.c
+--- binutils.orig/libiberty/cp-demangle.c	2024-01-17 09:54:11.323686947 +0000
+++ binutils-2.41/libiberty/cp-demangle.c	2024-01-17 09:54:42.468738420 +0000
+@@ -1,5 +1,5 @@
+ /* Demangler for g++ V3 ABI.
+-   Copyright (C) 2003-2023 Free Software Foundation, Inc.
+   Copyright (C) 2003-2024 Free Software Foundation, Inc.
+    Written by Ian Lance Taylor <ian@wasabisystems.com>.
+ 
+    This file is part of the libiberty library, which is part of GCC.
+@@ -993,6 +993,7 @@ d_make_comp (struct d_info *di, enum dem
+     case DEMANGLE_COMPONENT_VECTOR_TYPE:
+     case DEMANGLE_COMPONENT_CLONE:
+     case DEMANGLE_COMPONENT_MODULE_ENTITY:
+    case DEMANGLE_COMPONENT_CONSTRAINTS:
+       if (left == NULL || right == NULL)
+ 	return NULL;
+       break;
+@@ -1036,6 +1037,7 @@ d_make_comp (struct d_info *di, enum dem
+     case DEMANGLE_COMPONENT_TEMPLATE_NON_TYPE_PARM:
+     case DEMANGLE_COMPONENT_TEMPLATE_TEMPLATE_PARM:
+     case DEMANGLE_COMPONENT_TEMPLATE_PACK_PARM:
+    case DEMANGLE_COMPONENT_FRIEND:
+       if (left == NULL)
+ 	return NULL;
+       break;
+@@ -1344,6 +1346,22 @@ is_ctor_dtor_or_conversion (struct deman
+     }
+ }
+ 
+/* [ Q <constraint-expression> ] */
+
+static struct demangle_component *
+d_maybe_constraints (struct d_info *di, struct demangle_component *dc)
+{
+  if (d_peek_char (di) == 'Q')
+    {
+      d_advance (di, 1);
+      struct demangle_component *expr = d_expression (di);
+      if (expr == NULL)
+	return NULL;
+      dc = d_make_comp (di, DEMANGLE_COMPONENT_CONSTRAINTS, dc, expr);
+    }
+  return dc;
+}
+
+ /* <encoding> ::= <(function) name> <bare-function-type>
+               ::= <(data) name>
+               ::= <special-name>
+@@ -1397,21 +1415,21 @@ d_encoding (struct d_info *di, int top_l
+ 	      struct demangle_component *ftype;
+ 
+ 	      ftype = d_bare_function_type (di, has_return_type (dc));
+-	      if (ftype)
+-		{
+-		  /* If this is a non-top-level local-name, clear the
+-		     return type, so it doesn't confuse the user by
+-		     being confused with the return type of whaever
+-		     this is nested within.  */
+-		  if (!top_level && dc->type == DEMANGLE_COMPONENT_LOCAL_NAME
+-		      && ftype->type == DEMANGLE_COMPONENT_FUNCTION_TYPE)
+-		    d_left (ftype) = NULL;
+	      if (!ftype)
+		return NULL;
+ 
+-		  dc = d_make_comp (di, DEMANGLE_COMPONENT_TYPED_NAME,
+-				    dc, ftype);
+-		}
+-	      else
+-		dc = NULL;
+	      /* If this is a non-top-level local-name, clear the
+		 return type, so it doesn't confuse the user by
+		 being confused with the return type of whaever
+		 this is nested within.  */
+	      if (!top_level && dc->type == DEMANGLE_COMPONENT_LOCAL_NAME
+		  && ftype->type == DEMANGLE_COMPONENT_FUNCTION_TYPE)
+		d_left (ftype) = NULL;
+
+	      ftype = d_maybe_constraints (di, ftype);
+
+	      dc = d_make_comp (di, DEMANGLE_COMPONENT_TYPED_NAME,
+				dc, ftype);
+ 	    }
+ 	}
+     }
+@@ -1681,6 +1699,7 @@ d_maybe_module_name (struct d_info *di,
+ /* <unqualified-name> ::= [<module-name>] <operator-name> [<abi-tags>]
+                       ::= [<module-name>] <ctor-dtor-name> [<abi-tags>]
+                       ::= [<module-name>] <source-name> [<abi-tags>]
+		      ::= [<module-name>] F <source-name> [<abi-tags>]
+ 		      ::= [<module-name>] <local-source-name>  [<abi-tags>]
+                       ::= [<module-name>] DC <source-name>+ E [<abi-tags>]
+     <local-source-name>	::= L <source-name> <discriminator> [<abi-tags>]
+@@ -1692,11 +1711,18 @@ d_unqualified_name (struct d_info *di, s
+ {
+   struct demangle_component *ret;
+   char peek;
+  int member_like_friend = 0;
+ 
+   if (!d_maybe_module_name (di, &module))
+     return NULL;
+ 
+   peek = d_peek_char (di);
+  if (peek == 'F')
+    {
+      member_like_friend = 1;
+      d_advance (di, 1);
+      peek = d_peek_char (di);
+    }
+   if (IS_DIGIT (peek))
+     ret = d_source_name (di);
+   else if (IS_LOWER (peek))
+@@ -1773,6 +1799,8 @@ d_unqualified_name (struct d_info *di, s
+     ret = d_make_comp (di, DEMANGLE_COMPONENT_MODULE_ENTITY, ret, module);
+   if (d_peek_char (di) == 'B')
+     ret = d_abi_tags (di, ret);
+  if (member_like_friend)
+    ret = d_make_comp (di, DEMANGLE_COMPONENT_FRIEND, ret, NULL);
+   if (scope)
+     ret = d_make_comp (di, DEMANGLE_COMPONENT_QUAL_NAME, scope, ret);
+ 
+@@ -3012,7 +3040,7 @@ d_parmlist (struct d_info *di)
+       struct demangle_component *type;
+ 
+       char peek = d_peek_char (di);
+-      if (peek == '\0' || peek == 'E' || peek == '.')
+      if (peek == '\0' || peek == 'E' || peek == '.' || peek == 'Q')
+ 	break;
+       if ((peek == 'R' || peek == 'O')
+ 	  && d_peek_next_char (di) == 'E')
+@@ -3248,7 +3276,7 @@ d_template_args (struct d_info *di)
+   return d_template_args_1 (di);
+ }
+ 
+-/* <template-arg>* E  */
+/* <template-arg>* [Q <constraint-expression>] E  */
+ 
+ static struct demangle_component *
+ d_template_args_1 (struct d_info *di)
+@@ -3284,13 +3312,17 @@ d_template_args_1 (struct d_info *di)
+ 	return NULL;
+       pal = &d_right (*pal);
+ 
+-      if (d_peek_char (di) == 'E')
+-	{
+-	  d_advance (di, 1);
+-	  break;
+-	}
+      char peek = d_peek_char (di);
+      if (peek == 'E' || peek == 'Q')
+	break;
+     }
+ 
+  al = d_maybe_constraints (di, al);
+
+  if (d_peek_char (di) != 'E')
+    return NULL;
+  d_advance (di, 1);
+
+   di->last_name = hold_last_name;
+ 
+   return al;
+@@ -4431,6 +4463,7 @@ d_count_templates_scopes (struct d_print
+     case DEMANGLE_COMPONENT_PACK_EXPANSION:
+     case DEMANGLE_COMPONENT_TAGGED_NAME:
+     case DEMANGLE_COMPONENT_CLONE:
+    case DEMANGLE_COMPONENT_CONSTRAINTS:
+     recurse_left_right:
+       /* PR 89394 - Check for too much recursion.  */
+       if (dpi->recursion > DEMANGLE_RECURSION_LIMIT)
+@@ -4459,6 +4492,7 @@ d_count_templates_scopes (struct d_print
+     case DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS:
+     case DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS:
+     case DEMANGLE_COMPONENT_MODULE_ENTITY:
+    case DEMANGLE_COMPONENT_FRIEND:
+       d_count_templates_scopes (dpi, d_left (dc));
+       break;
+ 
+@@ -5189,6 +5223,22 @@ d_print_comp_inner (struct d_print_info
+ 	    dpt.next = dpi->templates;
+ 	    dpi->templates = &dpt;
+ 	    dpt.template_decl = typed_name;
+
+	    /* Constraints are mangled as part of the template argument list,
+	       so they wrap the _TEMPLATE_ARGLIST.  But
+	       d_lookup_template_argument expects the RHS of _TEMPLATE to be
+	       the _ARGLIST, and constraints need to refer to these args.  So
+	       move the _CONSTRAINTS out of the _TEMPLATE and onto the type.
+	       This will result in them being printed after the () like a
+	       trailing requires-clause, but that seems like our best option
+	       given that we aren't printing a template-head.  */
+	    struct demangle_component *tnr = d_right (typed_name);
+	    if (tnr->type == DEMANGLE_COMPONENT_CONSTRAINTS)
+	      {
+		d_right (typed_name) = d_left (tnr);
+		d_left (tnr) = d_right (dc);
+		d_right (dc) = tnr;
+	      }
+ 	  }
+ 
+ 	d_print_comp (dpi, options, d_right (dc));
+@@ -6197,6 +6247,11 @@ d_print_comp_inner (struct d_print_info
+       d_append_char (dpi, ']');
+       return;
+ 
+    case DEMANGLE_COMPONENT_FRIEND:
+      d_print_comp (dpi, options, d_left (dc));
+      d_append_string (dpi, "[friend]");
+      return;
+
+     case DEMANGLE_COMPONENT_TEMPLATE_HEAD:
+       {
+ 	d_append_char (dpi, '<');
+@@ -6231,6 +6286,12 @@ d_print_comp_inner (struct d_print_info
+       d_append_string (dpi, "...");
+       return;
+ 
+    case DEMANGLE_COMPONENT_CONSTRAINTS:
+      d_print_comp (dpi, options, d_left (dc));
+      d_append_string (dpi, " requires ");
+      d_print_comp (dpi, options, d_right (dc));
+      return;
+
+     default:
+       d_print_error (dpi);
+       return;
+--- binutils.orig/include/demangle.h	2024-01-17 11:06:11.111229985 +0000
+++ binutils-2.41/include/demangle.h	2024-01-17 11:06:21.281242709 +0000
+@@ -314,6 +314,8 @@ enum demangle_component_type
+   /* C++11: An rvalue reference modifying a member function.  The one
+      subtree is the type which is being referenced.  */
+   DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS,
+  /* C++23: A member function with explict object parameter.  */
+  DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION,
+   /* A vendor qualifier.  The left subtree is the type which is being
+      qualified, and the right subtree is the name of the
+      qualifier.  */
+--- binutils.orig/libiberty/cp-demangle.c	2024-01-17 11:06:11.246230153 +0000
+++ binutils-2.41/libiberty/cp-demangle.c	2024-01-17 11:06:21.282242710 +0000
+@@ -581,6 +581,7 @@ static char *d_demangle (const char *, i
+     case DEMANGLE_COMPONENT_CONST_THIS:			\
+     case DEMANGLE_COMPONENT_REFERENCE_THIS:		\
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:	\
+    case DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION:	\
+     case DEMANGLE_COMPONENT_TRANSACTION_SAFE:		\
+     case DEMANGLE_COMPONENT_NOEXCEPT:			\
+     case DEMANGLE_COMPONENT_THROW_SPEC
+@@ -749,6 +750,9 @@ d_dump (struct demangle_component *dc, i
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+       printf ("rvalue reference this\n");
+       break;
+    case DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION:
+      printf ("explicit object parameter\n");
+      break;
+     case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+       printf ("transaction_safe this\n");
+       break;
+@@ -1547,6 +1551,8 @@ d_name (struct d_info *di, int substable
+ 
+ /* <nested-name> ::= N [<CV-qualifiers>] [<ref-qualifier>] <prefix> <unqualified-name> E
+                  ::= N [<CV-qualifiers>] [<ref-qualifier>] <template-prefix> <template-args> E
+                 ::= N H <prefix> <unqualified-name> E
+                 ::= N H <template-prefix> <template-args> E
+ */
+ 
+ static struct demangle_component *
+@@ -1559,13 +1565,24 @@ d_nested_name (struct d_info *di)
+   if (! d_check_char (di, 'N'))
+     return NULL;
+ 
+-  pret = d_cv_qualifiers (di, &ret, 1);
+-  if (pret == NULL)
+-    return NULL;
+  if (d_peek_char (di) == 'H')
+    {
+      d_advance (di, 1);
+      di->expansion += sizeof "this";
+      pret = &ret;
+      rqual = d_make_comp (di, DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION,
+			   NULL, NULL);
+    }
+  else
+    {
+      pret = d_cv_qualifiers (di, &ret, 1);
+      if (pret == NULL)
+	return NULL;
+ 
+-  /* Parse the ref-qualifier now and then attach it
+-     once we have something to attach it to.  */
+-  rqual = d_ref_qualifier (di, NULL);
+      /* Parse the ref-qualifier now and then attach it
+	 once we have something to attach it to.  */
+      rqual = d_ref_qualifier (di, NULL);
+    }
+ 
+   *pret = d_prefix (di, 1);
+   if (*pret == NULL)
+@@ -4427,6 +4444,7 @@ d_count_templates_scopes (struct d_print
+     case DEMANGLE_COMPONENT_CONST_THIS:
+     case DEMANGLE_COMPONENT_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+    case DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION:
+     case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+     case DEMANGLE_COMPONENT_NOEXCEPT:
+     case DEMANGLE_COMPONENT_THROW_SPEC:
+@@ -6521,6 +6539,8 @@ d_print_mod (struct d_print_info *dpi, i
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
+       d_append_string (dpi, "&&");
+       return;
+    case DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION:
+      return;
+     case DEMANGLE_COMPONENT_COMPLEX:
+       d_append_string (dpi, " _Complex");
+       return;
+@@ -6559,11 +6579,13 @@ d_print_function_type (struct d_print_in
+ {
+   int need_paren;
+   int need_space;
+  int xobj_memfn;
+   struct d_print_mod *p;
+   struct d_print_mod *hold_modifiers;
+ 
+   need_paren = 0;
+   need_space = 0;
+  xobj_memfn = 0;
+   for (p = mods; p != NULL; p = p->next)
+     {
+       if (p->printed)
+@@ -6586,7 +6608,8 @@ d_print_function_type (struct d_print_in
+ 	  need_space = 1;
+ 	  need_paren = 1;
+ 	  break;
+-	FNQUAL_COMPONENT_CASE:
+	case DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION:
+	  xobj_memfn = 1;
+ 	  break;
+ 	default:
+ 	  break;
+@@ -6617,6 +6640,8 @@ d_print_function_type (struct d_print_in
+     d_append_char (dpi, ')');
+ 
+   d_append_char (dpi, '(');
+  if (xobj_memfn)
+    d_append_string (dpi, "this ");
+ 
+   if (d_right (dc) != NULL)
+     d_print_comp (dpi, options, d_right (dc));
--- a/binutils-do-not-link-with-static-libstdc++.patch
+++ b/binutils-do-not-link-with-static-libstdc++.patch
@ -51,9 +51,10 @@ diff -rup binutils.orig/configure binutils-2.40/configure
 
 
 if test -n "$ac_tool_prefix"; then
--- binutils.orig/configure.ac	2024-11-26 15:08:50.162328683 +0000
-+++ binutils-2.43.50-1686dc7079f/configure.ac	2024-11-26 15:08:56.929374527 +0000
-@@ -1410,26 +1410,6 @@ if test -z "$LD"; then
+diff -rup binutils.orig/configure.ac binutils-2.40/configure.ac
+--- binutils.orig/configure.ac	2023-02-13 14:43:00.728877170 +0000
+++ binutils-2.40/configure.ac	2023-02-13 14:43:13.671864892 +0000
+@@ -1435,26 +1435,6 @@ if test -z "$LD"; then
   fi
 fi
 
@ -79,4 +80,6 @@ diff -rup binutils.orig/configure binutils-2.40/configure
 -
 ACX_PROG_GNAT
 ACX_PROG_GDC
- ACX_PROG_CARGO
+ ACX_PROG_CMP_IGNORE_INITIAL
+Only in binutils-2.40: configure.ac.orig
+Only in binutils-2.40: configure.orig
--- a/binutils-execstack-error.patch
+++ b/binutils-execstack-error.patch
--- a/binutils-fix-ar-test.patch
+++ b/binutils-fix-ar-test.patch
@ -1,11 +0,0 @@
--- binutils.orig/binutils/testsuite/binutils-all/ar.exp	2024-02-07 13:02:23.490031197 +0000
-+++ binutils-2.42/binutils/testsuite/binutils-all/ar.exp	2024-02-07 13:03:10.285034069 +0000
-@@ -1017,7 +1017,7 @@ symbol_table
- argument_parsing
- deterministic_archive
- replacing_deterministic_member
-replacing_non_deterministic_member
-+# replacing_non_deterministic_member
- replacing_sde_deterministic_member
- delete_an_element
- move_an_element
--- a/binutils-gold-powerpc.patch
+++ b/binutils-gold-powerpc.patch
@ -0,0 +1,71 @@
+diff -rup binutils.orig/gold/powerpc.cc binutils-2.41/gold/powerpc.cc
+--- binutils.orig/gold/powerpc.cc	2023-08-25 11:21:08.882071604 +0100
+++ binutils-2.41/gold/powerpc.cc	2023-08-25 11:21:26.050081034 +0100
+@@ -3714,12 +3714,7 @@ Target_powerpc<size, big_endian>::do_rel
+   unsigned int prev_brlt_size = 0;
+   if (pass == 1)
+     {
+-      bool thread_safe
+-	= this->abiversion() < 2 && parameters->options().plt_thread_safe();
+-      if (size == 64
+-	  && this->abiversion() < 2
+-	  && !thread_safe
+-	  && !parameters->options().user_set_plt_thread_safe())
+      if (size == 64 && this->abiversion() < 2)
+ 	{
+ 	  static const char* const thread_starter[] =
+ 	    {
+@@ -3747,29 +3742,37 @@ Target_powerpc<size, big_endian>::do_rel
+ 	      /* libgo */
+ 	      "__go_go",
+ 	    };
+	  bool thread_safe = parameters->options().plt_thread_safe();
+ 
+-	  if (parameters->options().shared())
+-	    thread_safe = true;
+-	  else
+	  if (!thread_safe
+	      && !parameters->options().user_set_plt_thread_safe())
+ 	    {
+-	      for (unsigned int i = 0;
+-		   i < sizeof(thread_starter) / sizeof(thread_starter[0]);
+-		   i++)
+	      if (parameters->options().shared())
+		thread_safe = true;
+	      else
+ 		{
+-		  Symbol* sym = symtab->lookup(thread_starter[i], NULL);
+-		  thread_safe = (sym != NULL
+-				 && sym->in_reg()
+-				 && sym->in_real_elf());
+-		  if (thread_safe)
+-		    break;
+		  for (unsigned int i = 0;
+		       i < sizeof(thread_starter) / sizeof(thread_starter[0]);
+		       i++)
+		    {
+		      Symbol* sym = symtab->lookup(thread_starter[i], NULL);
+		      thread_safe = (sym != NULL
+				     && sym->in_reg()
+				     && sym->in_real_elf());
+		      if (thread_safe)
+			break;
+		    }
+ 		}
+ 	    }
+	  this->plt_thread_safe_ = thread_safe;
+ 	}
+-      this->plt_thread_safe_ = thread_safe;
+ 
+-      if (parameters->options().output_is_position_independent())
+-	this->rela_dyn_size_
+-	  = this->rela_dyn_section(layout)->current_data_size();
+      if (size == 64
+	  && parameters->options().output_is_position_independent())
+	{
+	  gold_assert (this->rela_dyn_);
+	  this->rela_dyn_size_ = this->rela_dyn_->current_data_size();
+	}
+ 
+       this->stub_group_size_ = parameters->options().stub_group_size();
+       bool no_size_errors = true;
--- a/binutils-gold-s390-configure.patch
+++ b/binutils-gold-s390-configure.patch
@ -1,40 +0,0 @@
-# The gold linker does not build if the target list includes s390x-linux
-# but does not include s390-linux.  ie it needs the 32-bit target to be
-# enabled in order for the 64-bit target to work.  On the other hand the
-# BFD library does not support the 32-bit s390 target.  So this patch
-# "enhances" the gold configure script so that if s390x is listed, the
-# s390 target will automatically be added to the list as well.
-
-diff -upr orig/gold/configure binutils-2.47/gold/configure
--- orig/gold/configure	2026-07-27 09:38:54.907192013 +0100
-+++ binutils-2.47/gold/configure	2026-07-27 10:12:02.759629540 +0100
-@@ -5223,7 +5223,12 @@ if test -n "$enable_targets"; then
-   for targ in `echo $enable_targets | sed -e 's/,/ /g'`; do
-     result=`$ac_config_sub $targ 2>/dev/null`
-     if test -n "$result"; then
-      canon_targets="$canon_targets $result"
-+      canon_targets="$canon_targets $result" ;
-+      case "$result" in
-+      s390x-*)
-+            canon_targets="$canon_targets s390-gnu-linux"
-+	    ;;
-+      esac
-     else
-       # Permit unrecognized target names, like "all".
-       canon_targets="$canon_targets $targ"
-diff -upr orig/gold/configure.ac binutils-2.47/gold/configure.ac
--- orig/gold/configure.ac	2026-07-27 09:38:54.907192013 +0100
-+++ binutils-2.47/gold/configure.ac	2026-07-27 10:18:18.480766140 +0100
-@@ -133,6 +133,12 @@ if test -n "$enable_targets"; then
-     result=`$ac_config_sub $targ 2>/dev/null`
-     if test -n "$result"; then
-       canon_targets="$canon_targets $result"
-+      # Hack: Enable the s390-linux target if s390x-linux is enabled.
-+      case "$result" in
-+      s390x-*)
-+            canon_targets="$canon_targets s390-gnu-linux"
-+	    ;;
-+      esac
-     else
-       # Permit unrecognized target names, like "all".
-       canon_targets="$canon_targets $targ"
--- a/binutils-gold-warn-unsupported.patch
+++ b/binutils-gold-warn-unsupported.patch
@ -24,6 +24,26 @@ diff -rup binutils.orig/gold/configure.ac binutils-2.34/gold/configure.ac
     else
       targetobjs="$targetobjs ${targ_obj}.\$(OBJEXT)"
       if test "$targ_extra_obj" != ""; then
+--- binutils.orig/ld/configure.tgt	2020-04-20 12:35:12.465301359 +0100
+++ binutils-2.34/ld/configure.tgt	2020-04-20 14:17:52.123066333 +0100
+@@ -220,7 +220,7 @@ bfin-*-linux-uclibc*)	targ_emul=elf32bfi
+ 			targ_extra_emuls="elf32bfin"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+-bpf-*-*)		targ_emul=elf64bpf
+bpf-* | bpf-*-*)	targ_emul=elf64bpf
+ 			;;
+ cr16-*-elf*)		targ_emul=elf32cr16
+ 			;;
+@@ -1026,7 +1026,7 @@ z8k-*-coff)		targ_emul=z8002
+ 			targ_extra_ofiles=
+ 			;;
+ *)
+-  echo 2>&1 "*** ld does not support target ${targ}"
+  echo 2>&1 "*** ld does not support target '${targ}' NO REALLY"
+   echo 2>&1 "*** see ld/configure.tgt for supported targets"
+   exit 1
+ 
 --- binutils.orig/bfd/config.bfd	2020-04-20 12:35:13.038297375 +0100
 +++ binutils-2.34/bfd/config.bfd	2020-04-20 14:25:26.452869193 +0100
@@ -473,7 +473,7 @@ case "${targ}" in
@ -35,14 +55,12 @@ diff -rup binutils.orig/gold/configure.ac binutils-2.34/gold/configure.ac
     targ_defvec=bpf_elf64_le_vec
     targ_selvecs=bpf_elf64_be_vec
     targ_underscore=yes
--- binutils.orig/ld/configure.tgt	2026-01-05 08:51:02.908224792 +0000
-+++ binutils-with-gold-2.45.50-be970c68891/ld/configure.tgt	2026-01-05 08:51:55.852677409 +0000
-@@ -255,7 +255,7 @@ bfin-*-uclinux*)	targ_emul=elf32bfin;
- bfin-*-linux-uclibc*)	targ_emul=elf32bfinfd;
- 			targ_extra_libpath=elf32bfin
- 			;;
-bpf-*-*)		targ_emul=elf64bpf
-+bpf-* | bpf-*-*)	targ_emul=elf64bpf
- 			;;
- cr16-*-elf*)		targ_emul=elf32cr16
- 			;;
+@@ -1427,7 +1427,7 @@ case "${targ}" in
+     ;;
+ 
+   *)
+-    echo 1>&2 "*** BFD does not support target ${targ}."
+    echo 1>&2 "*** BFD does not support target '${targ}'.  Honest."
+     echo 1>&2 "*** Look in bfd/config.bfd for supported targets."
+     exit 1
+     ;;
--- a/binutils-handle-corrupt-version-info.patch
+++ b/binutils-handle-corrupt-version-info.patch
@ -0,0 +1,29 @@
+--- binutils.orig/bfd/elf.c	2023-10-13 11:38:25.159530287 +0100
+++ binutils-2.41/bfd/elf.c	2023-10-13 11:41:23.290898228 +0100
+@@ -9479,6 +9479,8 @@ _bfd_elf_slurp_version_tables (bfd *abfd
+ 	  if (elf_use_dt_symtab_p (abfd))
+ 	    iverneed->vn_filename
+ 	      = elf_tdata (abfd)->dt_strtab + iverneed->vn_file;
+	  else if (hdr == NULL)
+	    goto error_return_bad_verref;
+ 	  else
+ 	    iverneed->vn_filename
+ 	      = bfd_elf_string_from_elf_section (abfd, hdr->sh_link,
+@@ -9516,6 +9518,8 @@ _bfd_elf_slurp_version_tables (bfd *abfd
+ 	      if (elf_use_dt_symtab_p (abfd))
+ 		ivernaux->vna_nodename
+ 		  = elf_tdata (abfd)->dt_strtab + ivernaux->vna_name;
+	      else if (hdr == NULL)
+		goto error_return_bad_verref;
+ 	      else
+ 		ivernaux->vna_nodename
+ 		  = bfd_elf_string_from_elf_section (abfd, hdr->sh_link,
+@@ -9546,7 +9550,7 @@ _bfd_elf_slurp_version_tables (bfd *abfd
+ 	  iverneed->vn_nextref = NULL;
+ 	  if (iverneed->vn_next == 0)
+ 	    break;
+-	  if (i + 1 < hdr->sh_info)
+	  if (hdr != NULL && (i + 1 < hdr->sh_info))
+ 	    iverneed->vn_nextref = iverneed + 1;
+ 
+ 	  if (iverneed->vn_next
--- a/binutils-ld-default-z-text.patch
+++ b/binutils-ld-default-z-text.patch
@ -1,52 +0,0 @@
-diff -rup binutils.orig/bfd/elflink.c binutils-with-gold-2.45.50-be970c68891/bfd/elflink.c
--- binutils.orig/bfd/elflink.c	2026-01-14 09:21:14.835847967 +0000
-+++ binutils-with-gold-2.45.50-be970c68891/bfd/elflink.c	2026-01-14 09:23:48.780495205 +0000
-@@ -13786,7 +13786,7 @@ _bfd_elf_final_link (bfd *abfd, struct b
- 		{
- 		  if (info->textrel_check == textrel_check_error)
- 		    info->callbacks->einfo
-		      (_("%P%X: read-only segment has dynamic relocations\n"));
-+		      (_("%P%X: error: read-only segment has dynamic relocations\n"));
- 		  else if (bfd_link_dll (info))
- 		    info->callbacks->einfo
- 		      (_("%P: warning: creating DT_TEXTREL in a shared object\n"));
-diff -rup binutils.orig/ld/testsuite/ld-aarch64/dt-memtag-mode.d binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/dt-memtag-mode.d
--- binutils.orig/ld/testsuite/ld-aarch64/dt-memtag-mode.d	2026-01-14 09:21:15.248851537 +0000
-+++ binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/dt-memtag-mode.d	2026-01-14 09:22:24.603416270 +0000
-@@ -1,5 +1,5 @@
- #source: dt-memtag.s
-#ld: -shared -z memtag-mode=async
-+#ld: -shared -z memtag-mode=async -z notext
- #readelf: -d
- 
- #...
-diff -rup binutils.orig/ld/testsuite/ld-aarch64/dt-memtag-stack.d binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/dt-memtag-stack.d
--- binutils.orig/ld/testsuite/ld-aarch64/dt-memtag-stack.d	2026-01-14 09:21:15.248851537 +0000
-+++ binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/dt-memtag-stack.d	2026-01-14 09:24:19.594780414 +0000
-@@ -1,5 +1,5 @@
- #source: dt-memtag.s
-#ld: -shared -z memtag-stack
-+#ld: -shared -z memtag-stack -z notext
- #readelf: -d
- 
- #...
-diff -rup binutils.orig/ld/testsuite/ld-aarch64/relr-text-pie.d binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/relr-text-pie.d
--- binutils.orig/ld/testsuite/ld-aarch64/relr-text-pie.d	2026-01-14 09:21:15.246851520 +0000
-+++ binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/relr-text-pie.d	2026-01-14 09:24:45.363485698 +0000
-@@ -1,5 +1,5 @@
- #source: relr-text.s
-#ld: -pie -z pack-relative-relocs -T relocs.ld
-+#ld: -pie -z pack-relative-relocs -T relocs.ld -z notext
- #readelf: -drW
- 
- #...
-diff -rup binutils.orig/ld/testsuite/ld-aarch64/relr-text-shared.d binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/relr-text-shared.d
--- binutils.orig/ld/testsuite/ld-aarch64/relr-text-shared.d	2026-01-14 09:21:15.246851520 +0000
-+++ binutils-with-gold-2.45.50-be970c68891/ld/testsuite/ld-aarch64/relr-text-shared.d	2026-01-14 09:25:06.651664713 +0000
-@@ -1,5 +1,5 @@
- #source: relr-text.s
-#ld: -shared -z pack-relative-relocs -T relocs.ld
-+#ld: -shared -z pack-relative-relocs -T relocs.ld -z notext
- #readelf: -drW
- 
- #...
--- a/binutils-multilib.am.patch
+++ b/binutils-multilib.am.patch
@ -0,0 +1,49 @@
+diff -rupN binutils.orig/multilib.am binutils-2.41/multilib.am
+--- binutils.orig/multilib.am	1970-01-01 01:00:00.000000000 +0100
+++ binutils-2.41/multilib.am	2024-02-12 16:41:56.899838085 +0000
+@@ -0,0 +1,45 @@
+## automake - create Makefile.in from Makefile.am
+
+## Copyright (C) 1994-2017 Free Software Foundation, Inc.
+## This Makefile.in is free software; the Free Software Foundation
+## gives unlimited permission to copy and/or distribute it,
+## with or without modifications, as long as this notice is preserved.
+
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+
+MULTISRCTOP =
+MULTIBUILDTOP =
+MULTIDIRS =
+MULTISUBDIR =
+MULTIDO = true
+MULTICLEAN = true
+
+# GNU Make needs to see an explicit $(MAKE) variable in the command it
+# runs to enable its job server during parallel builds.  Hence the
+# comments below.
+all-multi:
+	$(MULTIDO) $(AM_MAKEFLAGS) DO=all multi-do # $(MAKE)
+install-multi:
+	$(MULTIDO) $(AM_MAKEFLAGS) DO=install multi-do # $(MAKE)
+mostlyclean-multi:
+	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=mostlyclean multi-clean # $(MAKE)
+clean-multi:
+	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=clean multi-clean # $(MAKE)
+distclean-multi:
+	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=distclean multi-clean # $(MAKE)
+maintainer-clean-multi:
+	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=maintainer-clean multi-clean # $(MAKE)
+
+.MAKE .PHONY: all-multi clean-multi distclean-multi install-am \
+	      install-multi maintainer-clean-multi mostlyclean-multi
+
+install-exec-local: install-multi
+
+all-local: all-multi
+mostlyclean-local: mostlyclean-multi
+clean-local: clean-multi
+distclean-local: distclean-multi
+maintainer-clean-local: maintainer-clean-multi
--- a/binutils-power-11.patch
+++ b/binutils-power-11.patch
@ -0,0 +1,83 @@
+diff -rup binutils,orig/binutils/doc/binutils.texi binutils-2.41/binutils/doc/binutils.texi
+--- binutils,orig/binutils/doc/binutils.texi	2024-02-12 10:03:46.609677213 +0000
+++ binutils-2.41/binutils/doc/binutils.texi	2024-02-12 10:03:55.976681219 +0000
+@@ -2651,11 +2651,12 @@ rather than @code{li}.  All of the @opti
+ @option{e300}, @option{e500}, @option{e500mc}, @option{e500mc64},
+ @option{e500x2}, @option{e5500}, @option{e6500}, @option{efs},
+ @option{power4}, @option{power5}, @option{power6}, @option{power7},
+-@option{power8}, @option{power9}, @option{power10}, @option{ppc},
+-@option{ppc32}, @option{ppc64}, @option{ppc64bridge}, @option{ppcps},
+-@option{pwr}, @option{pwr2}, @option{pwr4}, @option{pwr5}, @option{pwr5x},
+-@option{pwr6}, @option{pwr7}, @option{pwr8}, @option{pwr9}, @option{pwr10},
+-@option{pwrx}, @option{titan}, @option{vle}, and @option{future}.
+@option{power8}, @option{power9}, @option{power10}, @option{power11},
+@option{ppc}, @option{ppc32}, @option{ppc64}, @option{ppc64bridge},
+@option{ppcps}, @option{pwr}, @option{pwr2}, @option{pwr4}, @option{pwr5},
+@option{pwr5x}, @option{pwr6}, @option{pwr7}, @option{pwr8}, @option{pwr9},
+@option{pwr10}, @option{pwr11}, @option{pwrx}, @option{titan}, @option{vle},
+and @option{future}.
+ @option{32} and @option{64} modify the default or a prior CPU
+ selection, disabling and enabling 64-bit insns respectively.  In
+ addition, @option{altivec}, @option{any}, @option{lsp}, @option{htm},
+Only in binutils-2.41/binutils/doc: binutils.texi.orig
+diff -rup binutils,orig/gas/config/tc-ppc.c binutils-2.41/gas/config/tc-ppc.c
+--- binutils,orig/gas/config/tc-ppc.c	2024-02-12 10:03:46.742677270 +0000
+++ binutils-2.41/gas/config/tc-ppc.c	2024-02-12 10:03:55.977681219 +0000
+@@ -1392,6 +1392,8 @@ PowerPC options:\n"));
+   fprintf (stream, _("\
+ -mpower10, -mpwr10      generate code for Power10 architecture\n"));
+   fprintf (stream, _("\
+-mpower11, -mpwr11      generate code for Power11 architecture\n"));
+  fprintf (stream, _("\
+ -mlibresoc              generate code for Libre-SOC architecture\n"));
+   fprintf (stream, _("\
+ -mfuture                generate code for 'future' architecture\n"));
+diff -rup binutils,orig/gas/doc/c-ppc.texi binutils-2.41/gas/doc/c-ppc.texi
+--- binutils,orig/gas/doc/c-ppc.texi	2024-02-12 10:03:46.783677288 +0000
+++ binutils-2.41/gas/doc/c-ppc.texi	2024-02-12 10:03:55.977681219 +0000
+@@ -156,6 +156,9 @@ Generate code for Power9 architecture.
+ @item -mpower10, -mpwr10
+ Generate code for Power10 architecture.
+ 
+@item -mpower11, -mpwr11
+Generate code for Power11 architecture.
+
+ @item -mfuture
+ Generate code for 'future' architecture.
+ 
+diff -rup binutils,orig/opcodes/ppc-dis.c binutils-2.41/opcodes/ppc-dis.c
+--- binutils,orig/opcodes/ppc-dis.c	2024-02-12 10:03:47.836677739 +0000
+++ binutils-2.41/opcodes/ppc-dis.c	2024-02-12 10:03:55.977681219 +0000
+@@ -208,6 +208,11 @@ struct ppc_mopt ppc_opts[] = {
+ 		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ 		| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+     0 },
+  { "power11", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+		| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+    0 },
+   { "libresoc",(PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ 		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ 		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+@@ -267,6 +272,11 @@ struct ppc_mopt ppc_opts[] = {
+ 		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ 		| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+     0 },
+  { "pwr11",   (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+		| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+    0 },
+   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
+     0 },
+   { "raw",     PPC_OPCODE_PPC,
+@@ -396,7 +406,7 @@ powerpc_init_dialect (struct disassemble
+       break;
+     default:
+       if (info->arch == bfd_arch_powerpc)
+-	dialect = ppc_parse_cpu (dialect, &sticky, "power10") | PPC_OPCODE_ANY;
+	dialect = ppc_parse_cpu (dialect, &sticky, "power11") | PPC_OPCODE_ANY;
+       else
+ 	dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
+       break;
--- a/binutils-ppc-dt_relr-relocs.patch
+++ b/binutils-ppc-dt_relr-relocs.patch
@ -0,0 +1,114 @@
+--- binutils.orig/bfd/elf64-ppc.c	2024-01-16 10:39:26.903071936 +0000
+++ binutils-2.41/bfd/elf64-ppc.c	2024-01-16 10:39:38.650127903 +0000
+@@ -4749,6 +4749,21 @@ is_8byte_reloc (enum elf_ppc64_reloc_typ
+ 	  || r_type == R_PPC64_PLTCALL);
+ }
+ 
+/* The RELR encoding doesn't allow odd addresses, so RELR_ALIGN must
+   be at least 1.  R_PPC64_RELATIVE relocs require alignment of 2**3.
+   We use 3 here to avoid complexity in relocate_section.  PR30824.  */
+#define RELR_ALIGN 3
+
+static bool
+maybe_relr (enum elf_ppc64_reloc_type r_type,
+	    const Elf_Internal_Rela *rel,
+	    const asection *sec)
+{
+  return ((r_type == R_PPC64_ADDR64 || r_type == R_PPC64_TOC)
+	  && (rel->r_offset & ((1 << RELR_ALIGN) - 1)) == 0
+	  && sec->alignment_power >= RELR_ALIGN);
+}
+
+ /* Like bfd_reloc_offset_in_range but without a howto.  Return true
+    iff a field of SIZE bytes at OFFSET is within SEC limits.  */
+ 
+@@ -5401,9 +5416,7 @@ ppc64_elf_check_relocs (bfd *abfd, struc
+ 		  p->count += 1;
+ 		  if (!must_be_dyn_reloc (info, r_type))
+ 		    p->pc_count += 1;
+-		  if ((r_type == R_PPC64_ADDR64 || r_type == R_PPC64_TOC)
+-		      && rel->r_offset % 2 == 0
+-		      && sec->alignment_power != 0)
+		  if (maybe_relr (r_type, rel, sec))
+ 		    p->rel_count += 1;
+ 		}
+ 	      else
+@@ -5438,9 +5451,7 @@ ppc64_elf_check_relocs (bfd *abfd, struc
+ 		      p->ifunc = is_ifunc;
+ 		    }
+ 		  p->count += 1;
+-		  if ((r_type == R_PPC64_ADDR64 || r_type == R_PPC64_TOC)
+-		      && rel->r_offset % 2 == 0
+-		      && sec->alignment_power != 0)
+		  if (maybe_relr (r_type, rel, sec))
+ 		    p->rel_count += 1;
+ 		}
+ 	    }
+@@ -7291,9 +7302,7 @@ dec_dynrel_count (const Elf_Internal_Rel
+ 	    {
+ 	      if (!must_be_dyn_reloc (info, r_type))
+ 		p->pc_count -= 1;
+-	      if ((r_type == R_PPC64_ADDR64 || r_type == R_PPC64_TOC)
+-		  && rel->r_offset % 2 == 0
+-		  && sec->alignment_power != 0)
+	      if (maybe_relr (r_type, rel, sec))
+ 		p->rel_count -= 1;
+ 	      p->count -= 1;
+ 	      if (p->count == 0)
+@@ -7326,9 +7335,7 @@ dec_dynrel_count (const Elf_Internal_Rel
+ 	{
+ 	  if (p->sec == sec && p->ifunc == is_ifunc)
+ 	    {
+-	      if ((r_type == R_PPC64_ADDR64 || r_type == R_PPC64_TOC)
+-		  && rel->r_offset % 2 == 0
+-		  && sec->alignment_power != 0)
+	      if (maybe_relr (r_type, rel, sec))
+ 		p->rel_count -= 1;
+ 	      p->count -= 1;
+ 	      if (p->count == 0)
+@@ -13869,6 +13876,9 @@ ppc64_elf_size_stubs (struct bfd_link_in
+ 		  switch (r_type)
+ 		    {
+ 		    default:
+		      if (info->enable_dt_relr
+			  && maybe_relr (r_type, irela, section))
+			break;
+ 		      continue;
+ 
+ 		    case R_PPC64_REL24:
+@@ -13880,14 +13890,6 @@ ppc64_elf_size_stubs (struct bfd_link_in
+ 		      if ((section->flags & SEC_CODE) != 0)
+ 			break;
+ 		      continue;
+-
+-		    case R_PPC64_ADDR64:
+-		    case R_PPC64_TOC:
+-		      if (info->enable_dt_relr
+-			  && irela->r_offset % 2 == 0
+-			  && section->alignment_power != 0)
+-			break;
+-		      continue;
+ 		    }
+ 
+ 		  /* Now determine the call target, its name, value,
+@@ -15272,7 +15274,7 @@ ppc64_elf_build_stubs (struct bfd_link_i
+       while (i < htab->relr_count)
+ 	{
+ 	  bfd_vma base = relr_addr[i];
+-	  BFD_ASSERT (base % 2 == 0);
+	  BFD_ASSERT ((base & ((1 << RELR_ALIGN) - 1)) == 0);
+ 	  bfd_put_64 (htab->elf.dynobj, base, loc);
+ 	  loc += 8;
+ 	  i++;
+@@ -17510,9 +17512,8 @@ ppc64_elf_relocate_section (bfd *output_
+ 
+ 	      if (!(info->enable_dt_relr
+ 		    && ELF64_R_TYPE (outrel.r_info) == R_PPC64_RELATIVE
+-		    && rel->r_offset % 2 == 0
+-		    && input_section->alignment_power != 0
+-		    && ELF64_R_TYPE (orig_rel.r_info) != R_PPC64_UADDR64))
+		    && maybe_relr (ELF64_R_TYPE (orig_rel.r_info),
+				   rel, input_section)))
+ 		{
+ 		  sreloc = elf_section_data (input_section)->sreloc;
+ 		  if (h != NULL
--- a/binutils-ppc64-TLS-no_plt-optimization-bug.patch
+++ b/binutils-ppc64-TLS-no_plt-optimization-bug.patch
@ -0,0 +1,45 @@
+From 1686dc7079f1c03bdaffd2f779b92aa2b7ad97b5 Mon Sep 17 00:00:00 2001
+From: Alan Modra <amodra@gmail.com>
+Date: Tue, 26 Nov 2024 08:24:19 +1030
+Subject: [PATCH] PR32387 ppc64 TLS optimization bug with -fno-plt code
+
+The inline plt code emitted by gcc is incompatible with the
+linker/ld.so --tls-get-addr-optimize scheme.  This is the runtime
+optimisation where the first call to __tls_get_addr results in
+__tls_get_addr updating the tls_index pair, then the special linker
+stub using that to short-circuit second and subsequent calls for a
+given tls symbol.  Enabled by default when the linker sees
+__tls_get_addr_opt is preseent, and enabled in ld.so when DT_PPC64_OPT
+has PPC64_OPT_TLS set.  Note that this is distinct from link-time tls
+optimisation.
+
+	PR 32387
+	* elf64-ppc.c (ppc64_elf_check_relocs): Disable tls_get_addr_opt
+	on detecting inline plt calls to __tls_get_addr.
+---
+ bfd/elf64-ppc.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
+index 9674fcdd6be..f7debc1edbc 100644
+--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
+@@ -4915,6 +4915,15 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
+       tls_type = 0;
+       switch (r_type)
+ 	{
+	case R_PPC64_PLTSEQ:
+	case R_PPC64_PLTSEQ_NOTOC:
+	  /* Inline plt call code emitted by gcc doesn't support
+	     modifying the tls_index words to short-circuit
+	     __tls_get_addr calls.  See PR32387.  */
+	  if (h != NULL && (h == tga || h == dottga))
+	    htab->params->tls_get_addr_opt = 0;
+	  break;
+
+ 	case R_PPC64_TLSGD:
+ 	case R_PPC64_TLSLD:
+ 	  /* These special tls relocs tie a call to __tls_get_addr with
+-- 
+2.43.5
+
--- a/binutils-remove-ld-protected-func-2-test.patch
+++ b/binutils-remove-ld-protected-func-2-test.patch
@ -1,33 +0,0 @@
-diff -rup binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp binutils-with-gold-2.45.50-96b8a8a633a/ld/testsuite/ld-x86-64/x86-64.exp
--- binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp	2025-11-20 12:02:23.738336155 +0000
-+++ binutils-with-gold-2.45.50-96b8a8a633a/ld/testsuite/ld-x86-64/x86-64.exp	2025-11-20 12:03:17.894485264 +0000
-@@ -1413,14 +1413,6 @@ if { [isnative] && [check_compiler_avail
- 	    "libprotected-func-2b.so" \
- 	] \
- 	[list \
-	    "Build protected-func-2 without PIE" \
-	    "$NOPIE_LDFLAGS -Wl,--no-as-needed tmpdir/libprotected-func-2b.so" \
-	    "$DIRECT_EXTERN_ACCESS_CFLAGS $NOPIE_CFLAGS -Wa,-mx86-used-note=yes" \
-	    { protected-func-1b.c } \
-	    {} \
-	    "protected-func-2" \
-	] \
-	[list \
- 	    "Build libprotected-func-2c.so" \
- 	    "-shared" \
- 	    "-fPIC -Wa,-mx86-used-note=yes" \
-@@ -1429,14 +1421,6 @@ if { [isnative] && [check_compiler_avail
- 	    "libprotected-func-2c.so" \
- 	] \
- 	[list \
-	    "Build protected-func-2a without PIE" \
-	    "$NOPIE_LDFLAGS -Wl,--no-as-needed tmpdir/libprotected-func-2c.so" \
-	    "$DIRECT_EXTERN_ACCESS_CFLAGS $NOPIE_CFLAGS -Wa,-mx86-used-note=yes" \
-	    { protected-func-1b.c } \
-	    {} \
-	    "protected-func-2a" \
-	] \
-	[list \
- 	    "Build libprotected-data-1a.so" \
- 	    "-shared -z noindirect-extern-access" \
- 	    "-fPIC -Wa,-mx86-used-note=yes" \
--- a/binutils-riscv-SUB_ULEB128.patch
+++ b/binutils-riscv-SUB_ULEB128.patch
@ -0,0 +1,239 @@
+diff -rupN binutils.orig/bfd/elfnn-riscv.c binutils-2.41/bfd/elfnn-riscv.c
+--- binutils.orig/bfd/elfnn-riscv.c	2024-01-02 17:35:07.412218130 +0000
+++ binutils-2.41/bfd/elfnn-riscv.c	2024-01-02 17:36:52.274311071 +0000
+@@ -1737,7 +1737,10 @@ perform_relocation (const reloc_howto_ty
+ {
+   if (howto->pc_relative)
+     value -= sec_addr (input_section) + rel->r_offset;
+-  value += rel->r_addend;
+
+  /* PR31179, ignore the non-zero addend of R_RISCV_SUB_ULEB128.  */
+  if (ELFNN_R_TYPE (rel->r_info) != R_RISCV_SUB_ULEB128)
+    value += rel->r_addend;
+ 
+   switch (ELFNN_R_TYPE (rel->r_info))
+     {
+@@ -1818,10 +1821,7 @@ perform_relocation (const reloc_howto_ty
+ 	value = ENCODE_CITYPE_LUI_IMM (RISCV_CONST_HIGH_PART (value));
+       break;
+ 
+-    /* SUB_ULEB128 must be applied after SET_ULEB128, so we only write the
+-       value back for SUB_ULEB128 should be enough.  */
+-    case R_RISCV_SET_ULEB128:
+-      break;
+    /* R_RISCV_SET_ULEB128 won't go into here.  */
+     case R_RISCV_SUB_ULEB128:
+       {
+ 	unsigned int len = 0;
+@@ -2514,7 +2514,7 @@ riscv_elf_relocate_section (bfd *output_
+ 	  else
+ 	    {
+ 	      msg = ("Mismatched R_RISCV_SET_ULEB128, it must be paired with"
+-		     "and applied before R_RISCV_SUB_ULEB128");
+		     " and applied before R_RISCV_SUB_ULEB128");
+ 	      r = bfd_reloc_dangerous;
+ 	    }
+ 	  break;
+@@ -2523,14 +2523,40 @@ riscv_elf_relocate_section (bfd *output_
+ 	  if (uleb128_set_rel != NULL
+ 	      && uleb128_set_rel->r_offset == rel->r_offset)
+ 	    {
+-	      relocation = uleb128_set_vma - relocation;
+	      relocation = uleb128_set_vma - relocation
+			   + uleb128_set_rel->r_addend;
+ 	      uleb128_set_vma = 0;
+ 	      uleb128_set_rel = NULL;
+
+	      /* PR31179, the addend of SUB_ULEB128 should be zero if using
+		 .uleb128, but we make it non-zero by accident in assembler,
+		 so just ignore it in perform_relocation, and make assembler
+		 continue doing the right thing.  Don't reset the addend of
+		 SUB_ULEB128 to zero here since it will break the --emit-reloc,
+		 even though the non-zero addend is unexpected.
+
+		 We encourage people to rebuild their stuff to get the
+		 non-zero addend of SUB_ULEB128, but that might need some
+		 times, so report warnings to inform people need to rebuild
+		 if --check-uleb128 is enabled.  However, since the failed
+		 .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it
+		 may acceptable that stop supproting them until people rebuld
+		 their stuff, maybe half-year or one year later.  I believe
+		 this might be the least harmful option that we should go.
+
+		 Or maybe we should teach people that don't write the
+		 .reloc R_RISCV_SUB* with non-zero constant, and report
+		 warnings/errors in assembler.  */
+	      if (htab->params->check_uleb128
+		  && rel->r_addend != 0)
+		_bfd_error_handler (_("%pB: warning: R_RISCV_SUB_ULEB128 with"
+				      " non-zero addend, please rebuild by"
+				      " Fedora 40 binutils or up"), input_bfd);
+ 	    }
+ 	  else
+ 	    {
+ 	      msg = ("Mismatched R_RISCV_SUB_ULEB128, it must be paired with"
+-		     "and applied after R_RISCV_SET_ULEB128");
+		     " and applied after R_RISCV_SET_ULEB128");
+ 	      r = bfd_reloc_dangerous;
+ 	    }
+ 	  break;
+@@ -5123,7 +5149,13 @@ _bfd_riscv_relax_section (bfd *abfd, ase
+ 	  if (h != NULL && h->type == STT_GNU_IFUNC)
+ 	    continue;
+ 
+	  /* Maybe we should check UNDEFWEAK_NO_DYNAMIC_RELOC here?  But that
+	     will break the undefweak relaxation testcases, so just make sure
+	     we won't do relaxations for linker_def symbols in short-term.  */
+ 	  if (h->root.type == bfd_link_hash_undefweak
+	      /* The linker_def symbol like __ehdr_start that may be undefweak
+		 for now, but will be guaranteed to be defined later.  */
+	      && !h->root.linker_def
+ 	      && (relax_func == _bfd_riscv_relax_lui
+ 		  || relax_func == _bfd_riscv_relax_pc))
+ 	    {
+diff -rupN binutils.orig/bfd/elfxx-riscv.h binutils-2.41/bfd/elfxx-riscv.h
+--- binutils.orig/bfd/elfxx-riscv.h	2024-01-02 17:35:07.412218130 +0000
+++ binutils-2.41/bfd/elfxx-riscv.h	2024-01-02 17:35:24.252233056 +0000
+@@ -31,6 +31,8 @@ struct riscv_elf_params
+ {
+   /* Whether to relax code sequences to GP-relative addressing.  */
+   bool relax_gp;
+  /* Whether to check if SUB_ULEB128 relocation has non-zero addend.  */
+  bool check_uleb128;
+ };
+ 
+ extern void riscv_elf32_set_options (struct bfd_link_info *,
+diff -rupN binutils.orig/ld/NEWS binutils-2.41/ld/NEWS
+--- binutils.orig/ld/NEWS	2024-01-02 17:35:08.012218662 +0000
+++ binutils-2.41/ld/NEWS	2024-01-02 17:35:56.139261318 +0000
+@@ -1,5 +1,10 @@
+ -*- text -*-
+ 
+* On RISC-V, add ld target option --[no-]check-uleb128.  Should rebuild the
+  objects by binutils 2.42 and up if enabling the option and get warnings,
+  since the non-zero addend of SUB_ULEB128 shouldn't be generated from .uleb128
+  directives.
+
+ * Added --warn-execstack-objects to warn about executable stacks only when an
+   input object file requests one.  Also added --error-execstack and
+   --error-rxw-segments options to convert warnings about executable stacks and
+diff -rupN binutils.orig/ld/emultempl/riscvelf.em binutils-2.41/ld/emultempl/riscvelf.em
+--- binutils.orig/ld/emultempl/riscvelf.em	2024-01-02 17:35:07.699218385 +0000
+++ binutils-2.41/ld/emultempl/riscvelf.em	2024-01-02 17:35:24.252233056 +0000
+@@ -25,7 +25,8 @@ fragment <<EOF
+ #include "elf/riscv.h"
+ #include "elfxx-riscv.h"
+ 
+-static struct riscv_elf_params params = { .relax_gp = 1 };
+static struct riscv_elf_params params = { .relax_gp = 1,
+					  .check_uleb128 = 0};
+ EOF
+ 
+ # Define some shell vars to insert bits of code into the standard elf
+@@ -35,17 +36,23 @@ enum risccv_opt
+ {
+   OPTION_RELAX_GP = 321,
+   OPTION_NO_RELAX_GP,
+  OPTION_CHECK_ULEB128,
+  OPTION_NO_CHECK_ULEB128,
+ };
+ '
+ 
+ PARSE_AND_LIST_LONGOPTS=${PARSE_AND_LIST_LONGOPTS}'
+     { "relax-gp", no_argument, NULL, OPTION_RELAX_GP },
+     { "no-relax-gp", no_argument, NULL, OPTION_NO_RELAX_GP },
+    { "check-uleb128", no_argument, NULL, OPTION_CHECK_ULEB128 },
+    { "no-check-uleb128", no_argument, NULL, OPTION_NO_CHECK_ULEB128 },
+ '
+ 
+ PARSE_AND_LIST_OPTIONS=${PARSE_AND_LIST_OPTIONS}'
+   fprintf (file, _("  --relax-gp                  Perform GP relaxation\n"));
+   fprintf (file, _("  --no-relax-gp               Don'\''t perform GP relaxation\n"));
+  fprintf (file, _("  --check-uleb128             Check if SUB_ULEB128 has non-zero addend\n"));
+  fprintf (file, _("  --no-check-uleb128          Don'\''t check if SUB_ULEB128 has non-zero addend\n"));
+ '
+ 
+ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}'
+@@ -56,6 +63,14 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LI
+     case OPTION_NO_RELAX_GP:
+       params.relax_gp = 0;
+       break;
+
+    case OPTION_CHECK_ULEB128:
+      params.check_uleb128 = 1;
+      break;
+
+    case OPTION_NO_CHECK_ULEB128:
+      params.check_uleb128 = 0;
+      break;
+ '
+ 
+ fragment <<EOF
+diff -rupN binutils.orig/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp binutils-2.41/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+--- binutils.orig/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp	2024-01-02 17:35:07.942218600 +0000
+++ binutils-2.41/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp	2024-01-02 17:35:24.252233056 +0000
+@@ -173,6 +173,8 @@ if [istarget "riscv*-*-*"] {
+     run_dump_test "attr-phdr"
+     run_dump_test "relax-max-align-gp"
+     run_dump_test "uleb128"
+    run_dump_test "pr31179"
+    run_dump_test "pr31179-r"
+     run_ld_link_tests [list \
+ 	[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
+ 	    "-march=rv32i -mabi=ilp32" {weakref32.s} \
+diff -rupN binutils.orig/ld/testsuite/ld-riscv-elf/pr31179-r.d binutils-2.41/ld/testsuite/ld-riscv-elf/pr31179-r.d
+--- binutils.orig/ld/testsuite/ld-riscv-elf/pr31179-r.d	1970-01-01 01:00:00.000000000 +0100
+++ binutils-2.41/ld/testsuite/ld-riscv-elf/pr31179-r.d	2024-01-02 17:35:24.252233056 +0000
+@@ -0,0 +1,10 @@
+#source: pr31179.s
+#as:
+#readelf: -Wr
+
+Relocation section '.rela.text' at .*
+[ 	]+Offset[ 	]+Info[ 	]+Type[ 	]+.*
+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_SET_ULEB128[ 	]+[0-9a-f]+[ 	]+bar \+ 1
+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_SUB_ULEB128[ 	]+[0-9a-f]+[ 	]+foo \+ 0
+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_SET_ULEB128[ 	]+[0-9a-f]+[ 	]+bar \+ 1
+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_SUB_ULEB128[ 	]+[0-9a-f]+[ 	]+foo \+ 1
+diff -rupN binutils.orig/ld/testsuite/ld-riscv-elf/pr31179.d binutils-2.41/ld/testsuite/ld-riscv-elf/pr31179.d
+--- binutils.orig/ld/testsuite/ld-riscv-elf/pr31179.d	1970-01-01 01:00:00.000000000 +0100
+++ binutils-2.41/ld/testsuite/ld-riscv-elf/pr31179.d	2024-01-02 17:35:24.252233056 +0000
+@@ -0,0 +1,11 @@
+#source: pr31179.s
+#as:
+#ld: --check-uleb128
+#objdump: -sj .text
+#warning: .*R_RISCV_SUB_ULEB128 with non-zero addend, please rebuild by Fedora 40 binutils or up
+
+.*:[ 	]+file format .*
+
+Contents of section .text:
+
+[ 	]+[0-9a-f]+[ 	]+00000303[ 	]+.*
+diff -rupN binutils.orig/ld/testsuite/ld-riscv-elf/pr31179.s binutils-2.41/ld/testsuite/ld-riscv-elf/pr31179.s
+--- binutils.orig/ld/testsuite/ld-riscv-elf/pr31179.s	1970-01-01 01:00:00.000000000 +0100
+++ binutils-2.41/ld/testsuite/ld-riscv-elf/pr31179.s	2024-01-02 17:35:24.252233056 +0000
+@@ -0,0 +1,13 @@
+.globl _start
+_start:
+
+foo:
+.2byte 0
+bar:
+
+.uleb128 bar - foo + 1
+
+reloc:
+.reloc reloc, R_RISCV_SET_ULEB128, bar + 1
+.reloc reloc, R_RISCV_SUB_ULEB128, foo + 1
+.byte 0x0
+--- binutils.orig/gas/config/tc-riscv.c	2024-01-03 13:08:16.588286420 +0000
+++ binutils-2.41/gas/config/tc-riscv.c	2024-01-03 13:08:32.749297812 +0000
+@@ -4949,6 +4949,7 @@ riscv_insert_uleb128_fixes (bfd *abfd AT
+       fix_new_exp (fragP, fragP->fr_fix, 0,
+ 		   exp_dup, 0, BFD_RELOC_RISCV_SET_ULEB128);
+       exp_dup->X_add_symbol = exp->X_op_symbol;
+      exp_dup->X_add_number = 0; /* Set addend of SUB_ULEB128 to zero.  */
+       fix_new_exp (fragP, fragP->fr_fix, 0,
+ 		   exp_dup, 0, BFD_RELOC_RISCV_SUB_ULEB128);
+     }
--- a/binutils-riscv-testsuite-fixes.patch
+++ b/binutils-riscv-testsuite-fixes.patch
@ -30,8 +30,8 @@ diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d binutils-2.40/
@@ -11,5 +11,5 @@ Disassembly of section .text:
 [0-9a-f]+ <_start>:
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+a1.*
- .*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a0,gp.*<data_a>
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a1,a1.*<data_b>
+ .*:[ 	]+[0-9a-f]+[ 	]+addi?[ 	]+a0,gp.*<data_a>
+-.*:[ 	]+[0-9a-f]+[ 	]+addi?[ 	]+a1,a1.*<data_b>
 +.*:[ 	]+[0-9a-f]+[ 	]+mv[ 	]+a1,a1
 #pass
 diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d binutils-2.40/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d
@ -134,136 +134,3 @@ diff -rup binutils.orig/ld/testsuite/ld-elf/tls.exp binutils-2.40/ld/testsuite/l
 
 objcopy_test_without_global_symbol
 
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d binutils-2.43.50-1f4aee70ed1/ld/testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d	2024-10-03 15:21:47.926570551 +0100
-+++ binutils-2.43.50-1f4aee70ed1/ld/testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d	2024-10-03 15:24:26.152502612 +0100
-@@ -8,10 +8,10 @@
- Disassembly of section \.text:
- 
- 0+[0-9a-f]+ <_start>:
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a0,a0,\-[0-9]+
-+.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a0,a0,.*
- .*:[ 	]+[0-9a-f]+[ 	]+jal[ 	        ]+ra,[0-9a-f]+ <_start>
- .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+a1,0x[0-9a-f]+
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a1,a1,\-[0-9]+ # [0-9a-f]+ <data_g>
-+.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a1,a1,.*
- .*:[ 	]+[0-9a-f]+[ 	]+lui[ 	        ]+a2,0x[0-9a-f]+
- .*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a2,a2,[0-9]+ # [0-9a-f]+ <data_g>
- .*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a3,tp,0 # 0 <data_t>
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d binutils-2.43.50-1f4aee70ed1/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d	2024-10-03 15:21:47.926570551 +0100
-+++ binutils-2.43.50-1f4aee70ed1/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d	2024-10-03 15:23:54.512530979 +0100
-@@ -8,7 +8,7 @@
- Disassembly of section \.text:
- 
- 0+[0-9a-f]+ <_start>:
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a0,a0,\-[0-9]+
-+.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a0,a0,.*
- .*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+ra,[0-9a-f]+ <_start>
- .*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a1,gp,\-[0-9]+ # [0-9a-f]+ <data_g>
- .*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a2,gp,\-[0-9]+ # [0-9a-f]+ <data_g>
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d binutils-2.43.50-1f4aee70ed1/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d	2024-10-03 15:21:47.926570551 +0100
-+++ binutils-2.43.50-1f4aee70ed1/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d	2024-10-03 15:25:01.687468496 +0100
-@@ -11,5 +11,5 @@ Disassembly of section .text:
- [0-9a-f]+ <_start>:
- .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+a1.*
- .*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a0,gp.*<data_a>
-.*:[ 	]+[0-9a-f]+[ 	]+mv[ 	]+a1,a1
-+.*:[ 	]+[0-9a-f]+[ 	]+.*
- #pass
--- binutils-with-gold-2.45.50-79b2b564fec.orig/ld/testsuite/ld-riscv-elf/zicfilp-unlabeled-plt.d	2025-09-09 15:52:30.684689609 +0100
-+++ binutils-with-gold-2.45.50-79b2b564fec/ld/testsuite/ld-riscv-elf/zicfilp-unlabeled-plt.d	2025-09-09 15:53:12.837859447 +0100
-@@ -30,6 +30,6 @@ Disassembly of section \.plt:
- 
- [0-9a-f]+ <bar@plt>:
- .*:[ 	]+[0-9a-f]+[ 	]+lpad[ 	]+0x0
-.*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+t3,0x1
-+.*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+t3,0x[0-9a-f]+
- .*:[ 	]+[0-9a-f]+[ 	]+ld[ 	]+t3,[0-9]+\(t3\) # [0-9a-f]+ <bar>
- .*:[ 	]+[0-9a-f]+[ 	]+jalr[ 	]+t1,t3
-diff -rup binutils-with-gold-2.45.50-beab972c07d,orig/binutils/testsuite/binutils-all/objcopy.exp binutils-with-gold-2.45.50-beab972c07d/binutils/testsuite/binutils-all/objcopy.exp
--- binutils-with-gold-2.45.50-beab972c07d,orig/binutils/testsuite/binutils-all/objcopy.exp	2025-12-02 12:47:19.063123207 +0000
-+++ binutils-with-gold-2.45.50-beab972c07d/binutils/testsuite/binutils-all/objcopy.exp	2025-12-04 12:39:26.079989597 +0000
-@@ -602,14 +602,19 @@ proc strip_test { } {
-     set exec_output [binutils_run $STRIP "$STRIPFLAGS $objfile"]
-     set exec_output [prune_warnings $exec_output]
-     if ![string equal "" $exec_output] {
-	fail $test
-+	fail "$test (warnings in linker output)"
-+	verbose $exec_output
- 	return
-     }
- 
-     set exec_output [binutils_run $NM "-a $NMFLAGS $objfile"]
-     set exec_output [prune_warnings $exec_output]
-     if ![string match "*: no symbols*" $exec_output] {
-	fail $test
-+
-+	# The RISC-V target compiles with annotation enabled and these symbols remain after stripping.
-+	setup_xfail riscv*-*-* 
-+
-+	fail "$test (symbols in nm output)"
- 	return
-     }
- 
-@@ -659,6 +664,9 @@ proc strip_test_with_saving_a_symbol { }
-     pass $test
- }
- 
-+# The RISC-V target compiles with annotation enabled and these symbols remain after stripping.
-+setup_xfail riscv*-*-* 
-+
- strip_test_with_saving_a_symbol
- 
- # Test stripping an archive.
-@@ -1503,7 +1519,7 @@ proc objcopy_test_without_global_symbol
- # in object files, so they will fail this test.
- setup_xfail aarch64*-*-* arm*-*-*
- # The RISC-V target compiles with annotation enabled and these symbols remain after stripping.
-# setup_xfail riscv*-*-* 
-+setup_xfail riscv*-*-* 
- 
- objcopy_test_without_global_symbol
- 
-diff -rup binutils-with-gold-2.45.50-beab972c07d,orig/ld/testsuite/lib/ld-lib.exp binutils-with-gold-2.45.50-beab972c07d/ld/testsuite/lib/ld-lib.exp
--- binutils-with-gold-2.45.50-beab972c07d,orig/ld/testsuite/lib/ld-lib.exp	2025-12-02 12:47:19.201090894 +0000
-+++ binutils-with-gold-2.45.50-beab972c07d/ld/testsuite/lib/ld-lib.exp	2025-12-03 09:30:07.184360005 +0000
-@@ -1633,6 +1633,12 @@ proc compile_one_cc { src output additio
- proc check_ctf_available { } {
-     global ctf_available_saved
- 
-+    # Skip CTF tests for the Risc-V target for now, as the
-+    # tests have not been tweaked to support the riscv format.
-+    if { [istarget "riscv*-*-linux*"] } {
-+	return 0
-+    }
-+    
-     if {![info exists ctf_available_saved]} {
- 	set ctf_available_saved 0
- 
--- fred/binutils/testsuite/lib/binutils-common.exp	2026-03-16 09:18:37.205413649 +0000
-+++ binutils-with-gold-2.46.50-d712202846b/binutils/testsuite/lib/binutils-common.exp	2026-03-16 09:18:49.559358668 +0000
-@@ -803,6 +803,9 @@ proc prune_warnings_extra { text } {
-     # Ignore warnings about linking objects with an old sframe format
-     regsub -all {(^|\n)([^\n]* unexpected SFrame format version [^\n]*\n[^\n]* SFrame section ignored\n?)+} $text {\1} text
- 
-+    # Skip warnings about the LTO plugin being needed.
-+    regsub -all "(^|\n)(\[^\n\]*:\[^\n\]*plugin needed to handle lto object\[^\n\]*\n?)+" $text "\\1" text
-+    
-     return $text
- }
- 
--- binutils.orig/ld/testsuite/ld-elf/shared.exp	2026-06-10 15:32:21.012274073 +0100
-+++ binutils-with-gold-2.46.50-48997323b0f/ld/testsuite/ld-elf/shared.exp	2026-06-10 15:34:41.397899263 +0100
-@@ -1859,6 +1859,10 @@ run_cc_link_tests [list \
- 	"pr29655.so" \
-     ] \
- ]
-+
-+# FIXME: Find out why the Risc-V fails this test.
-+setup_xfail "riscv64-*-*"
-+
- # PR 29655 (cont.): Check that in PIC code linked as PDE taking the address
- # of a function defined in a DSO results in the function address (from GOT)
- # and not the "canonical PLT" address from the PDE.
--- a/binutils-special-sections-in-groups.patch
+++ b/binutils-special-sections-in-groups.patch
@ -0,0 +1,27 @@
+--- binutils.orig/bfd/elf.c	2018-10-19 11:42:10.107277490 +0100
+++ binutils-2.31.1/bfd/elf.c	2018-10-19 11:44:33.607105801 +0100
+@@ -830,7 +830,13 @@ setup_group (bfd *abfd, Elf_Internal_Shd
+ 	}
+     }
+ 
+-  if (elf_group_name (newsect) == NULL)
+  if (elf_group_name (newsect) == NULL
+      /* OS specific sections might be in a group (eg ARM's ARM_EXIDX section)
+	 but they will not have been added to the group because they do not
+	 have contents that the ELF code in the BFD library knows how to
+	 process.  This is OK though - we rely upon the target backends to
+	 handle these sections for us.  */
+      && hdr->sh_type < SHT_LOOS)
+     {
+       /* xgettext:c-format */
+       _bfd_error_handler (_("%pB: no group info for section '%pA'"),
+@@ -936,7 +942,8 @@ _bfd_elf_setup_sections (bfd *abfd)
+ 	  else if (idx->shdr->bfd_section)
+ 	    elf_sec_group (idx->shdr->bfd_section) = shdr->bfd_section;
+ 	  else if (idx->shdr->sh_type != SHT_RELA
+-		   && idx->shdr->sh_type != SHT_REL)
+		   && idx->shdr->sh_type != SHT_REL
+		   && idx->shdr->sh_type < SHT_LOOS)
+ 	    {
+ 	      /* There are some unknown sections in the group.  */
+ 	      _bfd_error_handler
--- a/binutils-testsuite-fixes.patch
+++ b/binutils-testsuite-fixes.patch
@ -27,6 +27,17 @@
     if ![regexp $want $got] then {
 	fail "$testname -s option $got\n"
     } else {
+--- binutils.orig/binutils/testsuite/binutils-all/objdump.exp	2023-08-03 13:09:07.631503783 +0100
+++ binutils-2.41/binutils/testsuite/binutils-all/objdump.exp	2023-08-03 14:51:54.621295727 +0100
+@@ -921,7 +921,7 @@ proc test_objdump_S { } {
+     }
+ }
+ 
+-test_objdump_S
+# test_objdump_S
+ 
+ # Test objdump --private
+ proc test_objdump_P {} {
 --- binutils.orig/ld/testsuite/ld-scripts/ld-version.d	2023-08-03 13:09:07.949504208 +0100
 +++ binutils-2.41/ld/testsuite/ld-scripts/ld-version.d	2023-08-03 15:13:01.374590134 +0100
@@ -4,4 +4,4 @@
@ -63,7 +74,7 @@
 +++ binutils-2.41/ld/testsuite/ld-x86-64/x86-64.exp	2023-08-03 15:46:29.537416942 +0100
@@ -1386,7 +1386,7 @@ if { [isnative] && [check_compiler_avail
 	    "$NOPIE_LDFLAGS -Wl,--no-as-needed tmpdir/libprotected-func-2b.so" \
- 	    "$DIRECT_EXTERN_ACCESS_CFLAGS $NOPIE_CFLAGS -Wa,-mx86-used-note=yes" \
+ 	    "$NOPIE_CFLAGS -Wa,-mx86-used-note=yes" \
 	    { protected-func-1b.c } \
 -	    {{error_output "pr28875-func.err"}} \
 +	    {} \
@ -72,13 +83,21 @@
 	[list \
@@ -1402,7 +1402,7 @@ if { [isnative] && [check_compiler_avail
 	    "$NOPIE_LDFLAGS -Wl,--no-as-needed tmpdir/libprotected-func-2c.so" \
- 	    "$DIRECT_EXTERN_ACCESS_CFLAGS $NOPIE_CFLAGS -Wa,-mx86-used-note=yes" \
+ 	    "$NOPIE_CFLAGS -Wa,-mx86-used-note=yes" \
 	    { protected-func-1b.c } \
 -	    {{error_output "pr28875-func.err"}} \
 +	    {} \
 	    "protected-func-2a" \
 	] \
 	[list \
+@@ -2155,7 +2155,6 @@ if { [isnative] && [check_compiler_avail
+ 	}
+     }
+ 
+-    undefined_weak "$NOPIE_CFLAGS" "$NOPIE_LDFLAGS"
+     undefined_weak "-fPIE" ""
+     undefined_weak "-fPIE" "-pie"
+     undefined_weak "-fPIE" "-Wl,-z,nodynamic-undefined-weak"
 --- binutils.orig/binutils/testsuite/binutils-all/addr2line.exp	2023-08-04 14:00:37.692356718 +0100
 +++ binutils-2.41/binutils/testsuite/binutils-all/addr2line.exp	2023-08-04 14:04:32.627697316 +0100
@@ -39,9 +39,9 @@ if ![regexp -line "^(\[0-9a-fA-F\]+)? +\
@ -170,6 +189,31 @@
    {pr29086.c} \
    {} \
    "pr29086" \
+diff -rup binutils.orig/ld/testsuite/ld-aarch64/bti-plt-5.d binutils-2.41/ld/testsuite/ld-aarch64/bti-plt-5.d
+--- binutils.orig/ld/testsuite/ld-aarch64/bti-plt-5.d	2023-08-15 09:03:21.676463687 +0100
+++ binutils-2.41/ld/testsuite/ld-aarch64/bti-plt-5.d	2023-08-15 09:17:56.751533569 +0100
+@@ -12,8 +12,8 @@ Disassembly of section \.plt:
+ [0-9a-f]+ <.*>:
+ .*:	d503245f 	bti	c
+ .*:	a9bf7bf0 	stp	x16, x30, \[sp, #-16\]!
+-.*:	90000090 	adrp	x16, 410000 <.*>
+-.*:	f9...... 	ldr	x17, \[x16, #....\]
+.*:	90000090 	adrp	x16, 4.0000 <.*>
+.*:	f9...... 	ldr	x17, \[x16, #.*\]
+ .*:	91...... 	add	x16, x16, #0x...
+ .*:	d61f0220 	br	x17
+ .*:	d503201f 	nop
+@@ -21,8 +21,8 @@ Disassembly of section \.plt:
+ 
+ [0-9a-f]+ <.*>:
+ .*:	d503245f 	bti	c
+-.*:	90000090 	adrp	x16, 410000 <.*>
+-.*:	f9...... 	ldr	x17, \[x16, #....\]
+.*:	90000090 	adrp	x16, 4.0000 <.*>
+.*:	f9...... 	ldr	x17, \[x16, #.*\]
+ .*:	91...... 	add	x16, x16, #0x...
+ .*:	d61f0220 	br	x17
+ .*:	d503201f 	nop
 diff -rup binutils.orig/ld/testsuite/ld-aarch64/erratum843419-far-full.d binutils-2.41/ld/testsuite/ld-aarch64/erratum843419-far-full.d
 --- binutils.orig/ld/testsuite/ld-aarch64/erratum843419-far-full.d	2023-08-15 09:03:21.683463694 +0100
 +++ binutils-2.41/ld/testsuite/ld-aarch64/erratum843419-far-full.d	2023-08-15 09:05:41.549608111 +0100
@ -723,6 +767,25 @@ diff -rup binutils.orig/ld/testsuite/ld-powerpc/tls32.d binutils-2.41/ld/testsui
     [list "pr26580-4" \
      "" "" \
      {pr26580-a.c} "pr26580-4" "pr26580-4.out" "-fcommon" "c" "" \
+@@ -1579,18 +1575,6 @@ if { [istarget *-*-linux*]
+ 	    "pr22393-2-static" \
+ 	    "pass.out" \
+ 	] \
+-	[list \
+-	    "Run pr21964-4" \
+-	    "" \
+-	    "" \
+-	    {pr21964-4.c} \
+-	    "pr21964-4" \
+-	    "pass.out" \
+-	    "" \
+-	    "" \
+-	    "" \
+-	    "-ldl" \
+-	] \
+     ]
+ }
+ 
 --- binutils.orig/ld/testsuite/ld-s390/s390.exp	2023-08-15 14:30:13.292890888 +0100
 +++ binutils-2.41/ld/testsuite/ld-s390/s390.exp	2023-08-15 14:48:38.327360916 +0100
@@ -35,6 +35,8 @@ if { !([istarget "s390-*-*"] || [istarge
@ -773,6 +836,19 @@ diff -rup binutils.orig/ld/testsuite/ld-powerpc/tls32.d binutils-2.41/ld/testsui
 # Check cross references for ld -r
 
 if { ![ld_compile "$CC_FOR_TARGET $NOSANITIZE_CFLAGS $NOLTO_CFLAGS" "$srcdir/$subdir/cross4.c" tmpdir/cross4.o] } {
+--- binutils.orig/ld/testsuite/ld-shared/shared.exp	2023-08-15 14:30:13.309890913 +0100
+++ binutils-2.41/ld/testsuite/ld-shared/shared.exp	2023-08-15 15:00:31.929701875 +0100
+@@ -204,6 +204,10 @@ if { [istarget mips*-*-*] && ! [at_least
+ }
+ verbose "Using $picflag to compile PIC code"
+ 
+if { [istarget "i686-*-*"] } {
+    return
+}
+
+ # Compile the main program.
+ if ![ld_compile "$CC_FOR_TARGET $SHCFLAG" $srcdir/$subdir/main.c $tmpdir/mainnp.o] {
+     unsupported "shared (non PIC)"
 --- binutils.orig/ld/testsuite/ld-srec/srec.exp	2023-08-15 14:30:13.315890922 +0100
 +++ binutils-2.41/ld/testsuite/ld-srec/srec.exp	2023-08-15 15:01:24.104806404 +0100
@@ -442,6 +442,9 @@ setup_xfail "csky*-*-*"
@ -908,242 +984,18 @@ diff -rup binutils.orig/ld/testsuite/ld-powerpc/tls32no.g binutils-2.41/ld/tests
 - 1810154 (0+01 f+8020 f+9030 0+01|010+ 2080f+ 3090f+ 010+)  .*
 - 1810164 0+ 0+ 0+ 0+0  .*
 +#pass
-diff -rup binutils.orig/ld/testsuite/ld-plugin/lto.exp binutils-2.42.50/ld/testsuite/ld-plugin/lto.exp
--- binutils.orig/ld/testsuite/ld-plugin/lto.exp	2024-04-02 16:57:57.645534485 +0100
-+++ binutils-2.42.50/ld/testsuite/ld-plugin/lto.exp	2024-04-02 17:03:44.467994669 +0100
-@@ -617,9 +617,6 @@ set lto_run_tests [list \
-   [list "LTO 14" \
-    "-O2 -flto -fuse-linker-plugin tmpdir/lto-14a.o -Wl,--whole-archive tmpdir/liblto-14.a -Wl,--no-whole-archive tmpdir/lto-14b.o" "" \
-    {dummy.c} "lto-14.exe" "lto-14.out" "" "c"] \
-  [list "LTO 15" \
-   "-O2 -flto -fuse-linker-plugin -Wl,--start-group tmpdir/liblto-15.a tmpdir/lto-15a.o -Wl,--end-group" "" \
-   {dummy.c} "lto-15.exe" "lto-15.out" "" "c"] \
-   [list "PR ld/13066" \
-    "-O2 -flto -fuse-linker-plugin" "" \
-    {pr13066.cc} "pr13066.exe" "pr13066.out" "" "c++"] \
--- binutils.orig/ld/testsuite/ld-plugin/lto.exp	2024-04-15 10:14:55.231310539 +0100
-+++ binutils-2.42.50/ld/testsuite/ld-plugin/lto.exp	2024-04-15 10:17:20.777735046 +0100
-@@ -645,12 +645,6 @@ set lto_run_tests [list \
-   [list "LTO 11" \
-    "-O -flto -fuse-linker-plugin tmpdir/liblto-11.a" "" \
-    {dummy.c} "lto-11.exe" "lto-11.out" "" "c"] \
-  [list "LTO 12a" \
-   "-O -flto -fuse-linker-plugin tmpdir/lto-12a.o tmpdir/liblto-12.a tmpdir/lto-12b.o" "" \
-   {dummy.c} "lto-12a.exe" "lto-12.out" "" "c"] \
-  [list "LTO 12b" \
-   "-O -flto -fuse-linker-plugin tmpdir/lto-12a.o tmpdir/lto-12b.o tmpdir/liblto-12.a" "" \
-   {dummy.c} "lto-12b.exe" "lto-12.out" "" "c"] \
-   [list "LTO 13" \
-    "-O -flto -fuse-linker-plugin tmpdir/lto-13a.o tmpdir/liblto-13.a tmpdir/lto-13b.o" "" \
-    {dummy.c} "lto-13.exe" "lto-13.out" "" "c"] \
-diff -rup binutils.orig/ld/testsuite/ld-powerpc/tls32.d binutils-2.42.50-6b19a26ee12/ld/testsuite/ld-powerpc/tls32.d
--- binutils.orig/ld/testsuite/ld-powerpc/tls32.d	2024-06-14 15:00:11.382013143 +0100
-+++ binutils-2.42.50-6b19a26ee12/ld/testsuite/ld-powerpc/tls32.d	2024-06-14 15:09:06.405840085 +0100
-@@ -12,7 +12,7 @@ Disassembly of section \.text:
- 0+18[0-9a-f]+ <_start>:
- .*:	(42 9f 00 05|05 00 9f 42) 	bcl     20,4\*cr7\+so,.* <_start\+0x4>
- .*:	(7f c8 02 a6|a6 02 c8 7f) 	mflr    r30
-.*:	(3f de 00 02|02 00 de 3f) 	addis   r30,r30,2
-+.*:	(3f de 00 0.|0. 00 de 3f) 	addis   r30,r30,.
- .*:	(3b de 80 a0|.. 80 de 3b) 	addi    r30,r30,.*
- .*:	(60 00 00 00|00 00 00 60) 	nop
- .*:	(38 62 90 3c|3c 90 62 38) 	addi    r3,r2,-28612
-diff -rup binutils.orig/ld/testsuite/ld-powerpc/tls32no.d binutils-2.42.50-6b19a26ee12/ld/testsuite/ld-powerpc/tls32no.d
--- binutils.orig/ld/testsuite/ld-powerpc/tls32no.d	2024-06-14 15:00:11.382013143 +0100
-+++ binutils-2.42.50-6b19a26ee12/ld/testsuite/ld-powerpc/tls32no.d	2024-06-14 15:08:54.270817909 +0100
-@@ -12,7 +12,7 @@ Disassembly of section \.text:
- 0+18..... <_start>:
- .*:	(42 9f 00 05|05 00 9f 42) 	bcl     .*
- .*:	(7f c8 02 a6|a6 02 c8 7f) 	mflr    r30
-.*:	(3f de 00 02|02 00 de 3f) 	addis   r30,r30,2
-+.*:	(3f de 00 0.|0. 00 de 3f) 	addis   r30,r30,.
- .*:	(3b de 80 a0|.. 80 de 3b) 	addi    r30,r30,-[0-9]+
- .*:	(38 7f ff e4|e4 ff 7f 38) 	addi    r3,r31,-28
- .*:	(48 00 00 6d|6d 00 00 48) 	bl      .*
-720,725d719
-<   [list "Run pr20267a" \
-<    "-O2 -flto -fcommon tmpdir/pr20267a.o tmpdir/libpr20267a.a" "" \
-<    {dummy.c} "pr20267a" "pass.out" "-flto -O2 -fcommon" "c"] \
-<   [list "Run pr20267b" \
-<    "-O2 -flto -fcommon tmpdir/pr20267a.o tmpdir/libpr20267b.a" "" \
-<    {dummy.c} "pr20267b" "pass.out" "-flto -O2 -fcommon" "c"] \
-diff -rup bin.orig/ld/testsuite/ld-x86-64/sframe-pltgot-1.d binutils-2.43.50-55e32b3c682/ld/testsuite/ld-x86-64/sframe-pltgot-1.d
--- bin.orig/ld/testsuite/ld-x86-64/sframe-pltgot-1.d	2024-11-04 13:34:33.522976068 +0000
-+++ binutils-2.43.50-55e32b3c682/ld/testsuite/ld-x86-64/sframe-pltgot-1.d	2024-11-04 13:37:17.985526186 +0000
-@@ -23,6 +23,6 @@ Contents of the SFrame section .sframe:
- 
-     func idx \[1\]: pc = 0x1010, size = 64 bytes
-     STARTPC\[m\] +CFA +FP +RA +
-    0+0000 +sp\+16 +u +f +
-+    0+0000 +sp\+[0-9]+ +u +f +
- 
- #...
-diff -rup bin.orig/ld/testsuite/ld-x86-64/sframe-pltgot-2.d binutils-2.43.50-55e32b3c682/ld/testsuite/ld-x86-64/sframe-pltgot-2.d
--- bin.orig/ld/testsuite/ld-x86-64/sframe-pltgot-2.d	2024-11-04 13:34:33.522976068 +0000
-+++ binutils-2.43.50-55e32b3c682/ld/testsuite/ld-x86-64/sframe-pltgot-2.d	2024-11-04 13:37:43.874611190 +0000
-@@ -23,6 +23,6 @@ Contents of the SFrame section .sframe:
- 
-     func idx \[1\]: pc = 0x1010, size = 32 bytes
-     STARTPC\[m\] +CFA +FP +RA +
-    0+0000 +sp\+16 +u +f +
-+    0+0000 +sp\+[0-9]+ +u +f +
- 
- #...
-diff -rup bin.orig/ld/testsuite/ld-x86-64/sframe-pltgot-2.d binutils-2.43.50-55e32b3c682/ld/testsuite/ld-x86-64/sframe-pltgot-2.d
--- bin.orig/ld/testsuite/ld-x86-64/sframe-pltgot-2.d	2024-11-04 14:26:07.983307843 +0000
-+++ binutils-2.43.50-55e32b3c682/ld/testsuite/ld-x86-64/sframe-pltgot-2.d	2024-11-04 14:26:18.781353913 +0000
-@@ -21,7 +21,7 @@ Contents of the SFrame section .sframe:
-     0+1000 +sp\+16 +u +f +
-     0+1006 +sp\+24 +u +f +
- 
-    func idx \[1\]: pc = 0x1010, size = 32 bytes
-+    func idx \[1\]: pc = 0x1010, size = [0-9]+ bytes
-     STARTPC\[m\] +CFA +FP +RA +
-     0+0000 +sp\+[0-9]+ +u +f +
- 
--- binutils.orig/ld/testsuite/ld-bootstrap/bootstrap.exp	2025-02-03 11:13:50.829608207 +0000
-+++ binutils-with-gold-2.44/ld/testsuite/ld-bootstrap/bootstrap.exp	2025-02-03 11:17:34.589136290 +0000
-@@ -29,6 +29,12 @@ if ![isnative] {
-     return
- }
- 
-+# FIXME: The AArch64 rawhide libz and libjanson libraries are built
-+# without GCS support and so cannot be linked.
-+if {[istarget "aarch64*-*-*"] } {
-+    return
-+}
-+
- # Skip if OFILES aren't provided, it can happen when lauching
- # the testsuites outside the build directory.
- if {![info exists OFILES]} {
--- binutils.orig/ld/testsuite/ld-vsb/vsb.exp	2025-02-07 11:24:06.084525843 +0000
-+++ binutils-with-gold-2.44/ld/testsuite/ld-vsb/vsb.exp	2025-02-07 11:26:34.984041584 +0000
-@@ -366,7 +366,6 @@ proc visibility_run {visibility} {
- 		 || [ string match $visibility "protected_weak" ]
- 		 || [ string match $visibility "normal" ] } {
- 		setup_xfail "powerpc-*-linux*"
-		setup_xfail "s390x-*-linux*"
- 		if { [istarget sparc*-*-linux*] && [is_elf64 $tmpdir/mainnp.o] } {
- 		    setup_xfail "sparc*-*-linux*"
- 		}
--- binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp	2025-03-31 09:24:34.260146421 +0100
-+++ binutils-with-gold-2.44.50-7109ea04ac7/ld/testsuite/ld-x86-64/x86-64.exp	2025-03-31 09:25:38.951438172 +0100
-@@ -2167,7 +2167,6 @@ if { [isnative] && [check_compiler_avail
- 	}
-     }
- 
-    undefined_weak "$DIRECT_EXTERN_ACCESS_CFLAGS $NOPIE_CFLAGS" "$NOPIE_LDFLAGS"
-     undefined_weak "-fPIE" "$NOPIE_LDFLAGS"
-     undefined_weak "-fPIE" "-pie"
-     undefined_weak "-fPIE" "$NOPIE_LDFLAGS -Wl,-z,nodynamic-undefined-weak"
--- binutils.orig/ld/testsuite/ld-shared/shared.exp	2025-03-31 11:25:50.792541423 +0100
-+++ binutils-with-gold-2.44.50-7109ea04ac7/ld/testsuite/ld-shared/shared.exp	2025-03-31 11:27:36.680868036 +0100
-@@ -205,6 +205,10 @@ if { [istarget mips*-*-*] && ! [at_least
- }
- verbose "Using $picflag to compile PIC code"
- 
-+if { [istarget "i686-*-*"] } {
-+    return
-+}
-+
- # Compile the main program.
- global PLT_CFLAGS NOPIE_CFLAGS NOPIE_LDFLAGS
- verbose "Using $NOPIE_CFLAGS to compile and $NOPIE_LDFLAGS to link non PIC code"
--- binutils.orig/ld/testsuite/ld-elf/shared.exp	2025-03-31 11:25:50.643275417 +0100
-+++ binutils-with-gold-2.44.50-7109ea04ac7/ld/testsuite/ld-elf/shared.exp	2025-03-31 11:28:38.353212702 +0100
-@@ -1612,18 +1612,6 @@ if { [istarget *-*-linux*]
- 	    "pr22393-2-static" \
- 	    "pass.out" \
- 	] \
-	[list \
-	    "Run pr21964-4" \
-	    "$NOPIE_LDFLAGS" \
-	    "" \
-	    {pr21964-4.c} \
-	    "pr21964-4" \
-	    "pass.out" \
-	    "$NOPIE_CFLAGS" \
-	    "" \
-	    "" \
-	    "-ldl" \
-	] \
-     ]
- }
- 
--- fred/binutils/testsuite/binutils-all/objdump.exp	2026-02-16 09:03:27.457277379 +0000
-+++ binutils-with-gold-2.46.50-2d306bf8a70/binutils/testsuite/binutils-all/objdump.exp	2026-02-16 09:03:30.592967621 +0000
-@@ -957,7 +957,7 @@ proc test_objdump_S { } {
-     }
- }
- 
-test_objdump_S
-+# test_objdump_S
- 
- # Test objdump --map-global-vars on file containing dwarf-2 encoding information.
- 
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pic.d binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pic.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pic.d	2026-03-20 13:02:05.468700958 +0000
-+++ binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pic.d	2026-03-20 13:05:31.155200130 +0000
-@@ -1,6 +1,6 @@
- #source: data-reloc.s
- #as: -march=rv32i -mabi=ilp32 -defsym __abs__=1 -defsym __addr__=1 -defsym __undef__=1
-#ld: -m[riscv_choose_ilp32_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared
-+#ld: -m[riscv_choose_ilp32_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared -z notext
- #objdump: -dR
- 
- .*:[ 	]+file format .*
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pie.d binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pie.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pie.d	2026-03-20 13:02:05.468700958 +0000
-+++ binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv32-pie.d	2026-03-20 13:05:52.846252771 +0000
-@@ -1,6 +1,6 @@
- #source: data-reloc.s
- #as: -march=rv32i -mabi=ilp32 -defsym __abs__=1 -defsym __addr__=1
-#ld: -m[riscv_choose_ilp32_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -pie
-+#ld: -m[riscv_choose_ilp32_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -pie -z notext
- #objdump: -dR
- 
- .*:[ 	]+file format .*
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv32-symbolic.d binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv32-symbolic.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv32-symbolic.d	2026-03-20 13:02:05.468700958 +0000
-+++ binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv32-symbolic.d	2026-03-20 13:06:01.427273593 +0000
-@@ -1,6 +1,6 @@
- #source: data-reloc.s
- #as: -march=rv32i -mabi=ilp32 -defsym __abs__=1 -defsym __addr__=1 -defsym __undef__=1
-#ld: -m[riscv_choose_ilp32_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared -Bsymbolic
-+#ld: -m[riscv_choose_ilp32_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared -Bsymbolic -z notext
- #objdump: -dR
- 
- .*:[ 	]+file format .*
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pic.d binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pic.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pic.d	2026-03-20 13:02:05.468700958 +0000
-+++ binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pic.d	2026-03-20 13:04:07.601997355 +0000
-@@ -1,6 +1,6 @@
- #source: data-reloc.s
- #as: -march=rv64i -mabi=lp64 -defsym __64_bit__=1 -defsym __abs__=1 -defsym __addr__=1 -defsym __undef__=1
-#ld: -m[riscv_choose_lp64_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared
-+#ld: -m[riscv_choose_lp64_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared -z notext
- #objdump: -dR
- 
- .*:[ 	]+file format .*
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pie.d binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pie.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pie.d	2026-03-20 13:02:05.468700958 +0000
-+++ binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv64-pie.d	2026-03-20 13:04:57.106117494 +0000
-@@ -1,6 +1,6 @@
- #source: data-reloc.s
- #as: -march=rv64i -mabi=lp64 -defsym __64_bit__=1 -defsym __abs__=1 -defsym __addr__=1
-#ld: -m[riscv_choose_lp64_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -pie
-+#ld: -m[riscv_choose_lp64_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -pie -z notext
- #objdump: -dR
- 
- .*:[ 	]+file format .*
-diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv64-symbolic.d binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv64-symbolic.d
--- binutils.orig/ld/testsuite/ld-riscv-elf/data-reloc-rv64-symbolic.d	2026-03-20 13:02:05.468700958 +0000
-+++ binutils-with-gold-2.46/ld/testsuite/ld-riscv-elf/data-reloc-rv64-symbolic.d	2026-03-20 13:05:14.650160073 +0000
-@@ -1,6 +1,6 @@
- #source: data-reloc.s
- #as: -march=rv64i -mabi=lp64 -defsym __64_bit__=1 -defsym __abs__=1 -defsym __addr__=1 -defsym __undef__=1
-#ld: -m[riscv_choose_lp64_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared -Bsymbolic
-+#ld: -m[riscv_choose_lp64_emul] -Ttext 0x8000 --defsym _start=0x0 --defsym abs=0x100 --defsym abs_local=0x200 -shared -Bsymbolic -z notext
- #objdump: -dR
- 
- .*:[ 	]+file format .*
+--- binutils.orig/ld/testsuite/ld-plugin/lto.exp	2024-11-26 16:03:01.214914908 +0000
+++ binutils-2.41/ld/testsuite/ld-plugin/lto.exp	2024-11-26 16:04:39.983307748 +0000
+@@ -638,12 +638,6 @@ set lto_run_tests [list \
+   [list "Run pr20276" \
+    "-O2 -flto tmpdir/pr20276a.o tmpdir/pr20276b.o" "" \
+    {dummy.c} "pr20276" "pass.out" "-flto -O2" "c"] \
+-  [list "Run pr20267a" \
+-   "-O2 -flto -fcommon tmpdir/pr20267a.o tmpdir/libpr20267a.a" "" \
+-   {dummy.c} "pr20267a" "pass.out" "-flto -O2 -fcommon" "c"] \
+-  [list "Run pr20267b" \
+-   "-O2 -flto -fcommon tmpdir/pr20267a.o tmpdir/libpr20267b.a" "" \
+-   {dummy.c} "pr20267b" "pass.out" "-flto -O2 -fcommon" "c"] \
+   [list "Run pr22502" \
+    "-O2 -flto tmpdir/pr22502a.o tmpdir/pr22502b.o" "" \
+    {dummy.c} "pr20267" "pass.out" "-flto -O2 -fcommon" "c"] \
--- a/binutils-update-linker-manual.patch
+++ b/binutils-update-linker-manual.patch
@ -0,0 +1,36 @@
+diff -rup binutils.orig/ld/ld.1 binutils-2.41/ld/ld.1
+--- binutils.orig/ld/ld.1	2023-08-03 12:47:14.427004953 +0100
+++ binutils-2.41/ld/ld.1	2023-08-03 12:49:10.672145873 +0100
+@@ -2669,7 +2669,7 @@ systems may not understand them. If you
+ \&\fB\-\-enable\-new\-dtags\fR, the new dynamic tags will be created as needed
+ and older dynamic tags will be omitted.
+ If you specify \fB\-\-disable\-new\-dtags\fR, no new dynamic tags will be
+-created. By default, the new dynamic tags are not created. Note that
+created. By default, the new dynamic tags are created. Note that
+ those options are only available for ELF systems.
+ .IP \fB\-\-hash\-size=\fR\fInumber\fR 4
+ .IX Item "--hash-size=number"
+diff -rup binutils.orig/ld/ld.info binutils-2.41/ld/ld.info
+--- binutils.orig/ld/ld.info	2023-08-03 12:47:14.427004953 +0100
+++ binutils-2.41/ld/ld.info	2023-08-03 12:49:58.829204257 +0100
+@@ -2366,7 +2366,7 @@ GNU linker:
+      ‘--enable-new-dtags’, the new dynamic tags will be created as
+      needed and older dynamic tags will be omitted.  If you specify
+      ‘--disable-new-dtags’, no new dynamic tags will be created.  By
+-     default, the new dynamic tags are not created.  Note that those
+     default, the new dynamic tags are created.  Note that those
+      options are only available for ELF systems.
+ 
+ ‘--hash-size=NUMBER’
+diff -rup binutils.orig/ld/ld.texi binutils-2.41/ld/ld.texi
+--- binutils.orig/ld/ld.texi	2023-08-03 12:50:58.176276215 +0100
+++ binutils-2.41/ld/ld.texi	2023-08-03 12:41:11.902610960 +0100
+@@ -2946,7 +2946,7 @@ systems may not understand them. If you
+ @option{--enable-new-dtags}, the new dynamic tags will be created as needed
+ and older dynamic tags will be omitted.
+ If you specify @option{--disable-new-dtags}, no new dynamic tags will be
+-created. By default, the new dynamic tags are not created. Note that
+created. By default, the new dynamic tags are created. Note that
+ those options are only available for ELF systems.
+ 
+ @kindex --hash-size=@var{number}
--- a/binutils-x86-64-v3.patch
+++ b/binutils-x86-64-v3.patch
@ -0,0 +1,33 @@
+diff --git a/ld/testsuite/ld-x86-64/property-3.r b/ld/testsuite/ld-x86-64/property-3.r
+index 1bdb47c7b6b..1e4a24c6fbe 100644
+--- a/ld/testsuite/ld-x86-64/property-3.r
+++ b/ld/testsuite/ld-x86-64/property-3.r
+@@ -4,5 +4,5 @@ Displaying notes found in: .note.gnu.property
+   GNU                  0x[0-9a-f]+	NT_GNU_PROPERTY_TYPE_0
+       Properties: stack size: 0x800000
+ #...
+-	x86 ISA needed: x86-64-baseline, x86-64-v2
+	x86 ISA needed: x86-64-baseline, x86-64-v2.*
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/property-4.r b/ld/testsuite/ld-x86-64/property-4.r
+index 8cc618cbfad..031a1d280ad 100644
+--- a/ld/testsuite/ld-x86-64/property-4.r
+++ b/ld/testsuite/ld-x86-64/property-4.r
+@@ -4,5 +4,5 @@ Displaying notes found in: .note.gnu.property
+   GNU                  0x[0-9a-f]+	NT_GNU_PROPERTY_TYPE_0
+       Properties: stack size: 0x800000
+ #...
+-	x86 ISA needed: x86-64-baseline, x86-64-v2, x86-64-v4
+	x86 ISA needed: x86-64-baseline, x86-64-v2,.*x86-64-v4
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/property-5.r b/ld/testsuite/ld-x86-64/property-5.r
+index e3ba4f659b9..58b274b9772 100644
+--- a/ld/testsuite/ld-x86-64/property-5.r
+++ b/ld/testsuite/ld-x86-64/property-5.r
+@@ -4,5 +4,5 @@ Displaying notes found in: .note.gnu.property
+   GNU                  0x[0-9a-f]+	NT_GNU_PROPERTY_TYPE_0
+       Properties: stack size: 0x900000
+ #...
+-	x86 ISA needed: x86-64-baseline, x86-64-v2, x86-64-v4
+	x86 ISA needed: x86-64-baseline, x86-64-v2,.*x86-64-v4
+ #pass
--- a/binutils.spec
+++ b/binutils.spec
--- a/i686-AVX10.1-part-1.patch
+++ b/i686-AVX10.1-part-1.patch
@ -0,0 +1,209 @@
+From e30e95759268ce5a5a1f752b3c9fa3e4a182db99 Mon Sep 17 00:00:00 2001
+From: Jan Beulich <jbeulich@suse.com>
+Date: Fri, 1 Sep 2023 12:28:57 +0200
+Subject: [PATCH] x86: correct source used for two non-AVX512 VEXWIG tests
+
+These shouldn't wrongly include the AVX512VL sources. Obviously the
+expectations therefore also need to change.
+---
+ gas/testsuite/gas/i386/vaes-wig1.d       | 118 ++++-------------------
+ gas/testsuite/gas/i386/vpclmulqdq-wig1.d |  44 +++------
+ 2 files changed, 32 insertions(+), 130 deletions(-)
+
+diff --git a/gas/testsuite/gas/i386/vaes-wig1.d b/gas/testsuite/gas/i386/vaes-wig1.d
+index 8e8567e01df..9d37e52b49e 100644
+--- a/gas/testsuite/gas/i386/vaes-wig1.d
+++ b/gas/testsuite/gas/i386/vaes-wig1.d
+@@ -1,7 +1,7 @@
+ #as: -mvexwig=1
+ #objdump: -dw
+ #name: i386 AVX/VAES wig insns
+-#source: avx512vl_vaes.s
+#source: vaes.s
+ 
+ .*: +file format .*
+ 
+@@ -9,100 +9,24 @@
+ Disassembly of section \.text:
+ 
+ 00000000 <_start>:
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 de f4[ 	]*vaesdec %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 de b2 f0 07 00 00[ 	]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 de f4[ 	]*vaesdec %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 de b2 e0 0f 00 00[ 	]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 df f4[ 	]*vaesdeclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 df b2 f0 07 00 00[ 	]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 df f4[ 	]*vaesdeclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 df b2 e0 0f 00 00[ 	]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dc f4[ 	]*vaesenc %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dc b2 f0 07 00 00[ 	]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dc f4[ 	]*vaesenc %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dc b2 e0 0f 00 00[ 	]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dd f4[ 	]*vaesenclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dd b2 f0 07 00 00[ 	]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dd f4[ 	]*vaesenclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dd b2 e0 0f 00 00[ 	]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 de f4[ 	]*vaesdec %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 de b2 f0 07 00 00[ 	]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 de f4[ 	]*vaesdec %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 de b2 e0 0f 00 00[ 	]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 df f4[ 	]*vaesdeclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 df b2 f0 07 00 00[ 	]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 df f4[ 	]*vaesdeclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 df b2 e0 0f 00 00[ 	]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dc f4[ 	]*vaesenc %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dc b2 f0 07 00 00[ 	]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dc f4[ 	]*vaesenc %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dc b2 e0 0f 00 00[ 	]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dd f4[ 	]*vaesenclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d1 dd b2 f0 07 00 00[ 	]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dd f4[ 	]*vaesenclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e2 d5 dd b2 e0 0f 00 00[ 	]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:	c4 e2 cd dc d4       	vaesenc %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd dc 39       	vaesenc \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd dd d4       	vaesenclast %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd dd 39       	vaesenclast \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd de d4       	vaesdec %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd de 39       	vaesdec \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd df d4       	vaesdeclast %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd df 39       	vaesdeclast \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd dc d4       	vaesenc %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd dc 39       	vaesenc \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd dc 39       	vaesenc \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd dd d4       	vaesenclast %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd dd 39       	vaesenclast \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd dd 39       	vaesenclast \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd de d4       	vaesdec %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd de 39       	vaesdec \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd de 39       	vaesdec \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd df d4       	vaesdeclast %ymm4,%ymm6,%ymm2
+[ 	]*[a-f0-9]+:	c4 e2 cd df 39       	vaesdeclast \(%ecx\),%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e2 cd df 39       	vaesdeclast \(%ecx\),%ymm6,%ymm7
+ #pass
+diff --git a/gas/testsuite/gas/i386/vpclmulqdq-wig1.d b/gas/testsuite/gas/i386/vpclmulqdq-wig1.d
+index 843bf56bc21..52bb1651201 100644
+--- a/gas/testsuite/gas/i386/vpclmulqdq-wig1.d
+++ b/gas/testsuite/gas/i386/vpclmulqdq-wig1.d
+@@ -1,7 +1,7 @@
+ #as: -mvexwig=1
+ #objdump: -dw
+ #name: i386 AVX/VPCLMULQDQ wig insns
+-#source: avx512vl_vpclmulqdq.s
+#source: vpclmulqdq.s
+ 
+ .*: +file format .*
+ 
+@@ -9,36 +9,14 @@
+ Disassembly of section \.text:
+ 
+ 00000000 <_start>:
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 e9 44 da ab[ 	]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 e9 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 e9 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 e1 ab[ 	]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 a2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 da ab[ 	]*\{evex\} vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*\{evex\} vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 65 08 44 e2 11[ 	]*\{evex\} vpclmulhqhqdq %xmm2,%xmm3,%xmm4
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 08 44 eb 01[ 	]*\{evex\} vpclmulhqlqdq %xmm3,%xmm4,%xmm5
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 f4 10[ 	]*\{evex\} vpclmullqhqdq %xmm4,%xmm5,%xmm6
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 4d 08 44 fd 00[ 	]*\{evex\} vpclmullqlqdq %xmm5,%xmm6,%xmm7
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d9 11[ 	]*\{evex\} vpclmulhqhqdq %ymm1,%ymm2,%ymm3
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 65 28 44 e2 01[ 	]*\{evex\} vpclmulhqlqdq %ymm2,%ymm3,%ymm4
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 28 44 eb 10[ 	]*\{evex\} vpclmullqhqdq %ymm3,%ymm4,%ymm5
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 f4 00[ 	]*\{evex\} vpclmullqlqdq %ymm4,%ymm5,%ymm6
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 d1 44 db ab[ 	]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 d1 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 d1 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 ed 44 d2 ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 ed 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+-[ 	]*[a-f0-9]+:[ 	]*c4 e3 ed 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 db ab[ 	]*\{evex\} vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d2 ab[ 	]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 52 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 ed 44 d9 11[ 	]*vpclmulhqhqdq %ymm1,%ymm2,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 e5 44 e2 01[ 	]*vpclmulhqlqdq %ymm2,%ymm3,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 dd 44 eb 10[ 	]*vpclmullqhqdq %ymm3,%ymm4,%ymm5
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 f4 00[ 	]*vpclmullqlqdq %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 d5 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+ #pass
+-- 
+2.43.0
+
--- a/i686-AVX10.1-part-2.patch
+++ b/i686-AVX10.1-part-2.patch
@ -0,0 +1,379 @@
+From dfab07b9ead66f08661325c03175e1df9210ccd7 Mon Sep 17 00:00:00 2001
+From: Jan Beulich <jbeulich@suse.com>
+Date: Fri, 1 Sep 2023 12:29:44 +0200
+Subject: [PATCH] x86: unindent most of set_cpu_arch()
+
+Inverting the initial if()'s condition allows to move out the bulk of
+the function by a level, improving readability at least a bit. While
+doing that also pull the push/pop handling up first, such that "else if"
+after "return" isn't needed anymore; the order in which special cases
+are checked doesn't really matter.
+---
+ gas/config/tc-i386.c | 305 ++++++++++++++++++++++---------------------
+ 1 file changed, 154 insertions(+), 151 deletions(-)
+
+diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
+index 19a5f2d61e5..00abfc78264 100644
+--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
+@@ -2793,29 +2793,134 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
+     bool no_cond_jump_promotion;
+   } arch_stack_entry;
+   static const arch_stack_entry *arch_stack_top;
+  char *s;
+  int e;
+  const char *string;
+  unsigned int j = 0;
+  i386_cpu_flags flags;
+ 
+   SKIP_WHITESPACE ();
+ 
+-  if (!is_end_of_line[(unsigned char) *input_line_pointer])
+  if (is_end_of_line[(unsigned char) *input_line_pointer])
+    {
+      as_bad (_("missing cpu architecture"));
+      input_line_pointer++;
+      return;
+    }
+
+  e = get_symbol_name (&s);
+  string = s;
+
+  if (strcmp (string, "push") == 0)
+    {
+      arch_stack_entry *top = XNEW (arch_stack_entry);
+
+      top->name = cpu_arch_name;
+      if (cpu_sub_arch_name)
+	top->sub_name = xstrdup (cpu_sub_arch_name);
+      else
+	top->sub_name = NULL;
+      top->flags = cpu_arch_flags;
+      top->isa = cpu_arch_isa;
+      top->isa_flags = cpu_arch_isa_flags;
+      top->flag_code = flag_code;
+      top->stackop_size = stackop_size;
+      top->no_cond_jump_promotion = no_cond_jump_promotion;
+
+      top->prev = arch_stack_top;
+      arch_stack_top = top;
+
+      (void) restore_line_pointer (e);
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+  if (strcmp (string, "pop") == 0)
+     {
+-      char *s;
+-      int e = get_symbol_name (&s);
+-      const char *string = s;
+-      unsigned int j = 0;
+-      i386_cpu_flags flags;
+      const arch_stack_entry *top = arch_stack_top;
+ 
+-      if (strcmp (string, "default") == 0)
+      if (!top)
+	as_bad (_(".arch stack is empty"));
+      else if (top->flag_code != flag_code
+	       || top->stackop_size != stackop_size)
+	{
+	  static const unsigned int bits[] = {
+	    [CODE_16BIT] = 16,
+	    [CODE_32BIT] = 32,
+	    [CODE_64BIT] = 64,
+	  };
+
+	  as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
+		  bits[top->flag_code],
+		  top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : "");
+	}
+      else
+	{
+	  arch_stack_top = top->prev;
+
+	  cpu_arch_name = top->name;
+	  free (cpu_sub_arch_name);
+	  cpu_sub_arch_name = top->sub_name;
+	  cpu_arch_flags = top->flags;
+	  cpu_arch_isa = top->isa;
+	  cpu_arch_isa_flags = top->isa_flags;
+	  no_cond_jump_promotion = top->no_cond_jump_promotion;
+
+	  XDELETE (top);
+	}
+
+      (void) restore_line_pointer (e);
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+  if (strcmp (string, "default") == 0)
+    {
+      if (strcmp (default_arch, "iamcu") == 0)
+	string = default_arch;
+      else
+ 	{
+-	  if (strcmp (default_arch, "iamcu") == 0)
+-	    string = default_arch;
+	  static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS;
+
+	  cpu_arch_name = NULL;
+	  free (cpu_sub_arch_name);
+	  cpu_sub_arch_name = NULL;
+	  cpu_arch_flags = cpu_unknown_flags;
+	  if (flag_code == CODE_64BIT)
+	    {
+	      cpu_arch_flags.bitfield.cpu64 = 1;
+	      cpu_arch_flags.bitfield.cpuno64 = 0;
+	    }
+ 	  else
+ 	    {
+-	      static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS;
+	      cpu_arch_flags.bitfield.cpu64 = 0;
+	      cpu_arch_flags.bitfield.cpuno64 = 1;
+	    }
+	  cpu_arch_isa = PROCESSOR_UNKNOWN;
+	  cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
+	  if (!cpu_arch_tune_set)
+	    {
+	      cpu_arch_tune = cpu_arch_isa;
+	      cpu_arch_tune_flags = cpu_arch_isa_flags;
+	    }
+
+	  j = ARRAY_SIZE (cpu_arch) + 1;
+	}
+    }
+
+  for (; j < ARRAY_SIZE (cpu_arch); j++)
+    {
+      if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0
+	  && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE))
+	{
+	  if (*string != '.')
+	    {
+	      check_cpu_arch_compatible (string, cpu_arch[j].enable);
+ 
+-	      cpu_arch_name = NULL;
+	      cpu_arch_name = cpu_arch[j].name;
+ 	      free (cpu_sub_arch_name);
+ 	      cpu_sub_arch_name = NULL;
+-	      cpu_arch_flags = cpu_unknown_flags;
+	      cpu_arch_flags = cpu_arch[j].enable;
+ 	      if (flag_code == CODE_64BIT)
+ 		{
+ 		  cpu_arch_flags.bitfield.cpu64 = 1;
+@@ -2826,173 +2931,71 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
+ 		  cpu_arch_flags.bitfield.cpu64 = 0;
+ 		  cpu_arch_flags.bitfield.cpuno64 = 1;
+ 		}
+-	      cpu_arch_isa = PROCESSOR_UNKNOWN;
+-	      cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
+	      cpu_arch_isa = cpu_arch[j].type;
+	      cpu_arch_isa_flags = cpu_arch[j].enable;
+ 	      if (!cpu_arch_tune_set)
+ 		{
+ 		  cpu_arch_tune = cpu_arch_isa;
+ 		  cpu_arch_tune_flags = cpu_arch_isa_flags;
+ 		}
+-
+-	      j = ARRAY_SIZE (cpu_arch) + 1;
+	      pre_386_16bit_warned = false;
+	      break;
+ 	    }
+-	}
+-      else if (strcmp (string, "push") == 0)
+-	{
+-	  arch_stack_entry *top = XNEW (arch_stack_entry);
+ 
+-	  top->name = cpu_arch_name;
+-	  if (cpu_sub_arch_name)
+-	    top->sub_name = xstrdup (cpu_sub_arch_name);
+-	  else
+-	    top->sub_name = NULL;
+-	  top->flags = cpu_arch_flags;
+-	  top->isa = cpu_arch_isa;
+-	  top->isa_flags = cpu_arch_isa_flags;
+-	  top->flag_code = flag_code;
+-	  top->stackop_size = stackop_size;
+-	  top->no_cond_jump_promotion = no_cond_jump_promotion;
+	  if (cpu_flags_all_zero (&cpu_arch[j].enable))
+	    continue;
+ 
+-	  top->prev = arch_stack_top;
+-	  arch_stack_top = top;
+	  flags = cpu_flags_or (cpu_arch_flags, cpu_arch[j].enable);
+ 
+-	  (void) restore_line_pointer (e);
+-	  demand_empty_rest_of_line ();
+-	  return;
+-	}
+-      else if (strcmp (string, "pop") == 0)
+-	{
+-	  const arch_stack_entry *top = arch_stack_top;
+-
+-	  if (!top)
+-	    as_bad (_(".arch stack is empty"));
+-	  else if (top->flag_code != flag_code
+-		   || top->stackop_size != stackop_size)
+	  if (!cpu_flags_equal (&flags, &cpu_arch_flags))
+ 	    {
+-	      static const unsigned int bits[] = {
+-	        [CODE_16BIT] = 16,
+-	        [CODE_32BIT] = 32,
+-	        [CODE_64BIT] = 64,
+-	      };
+-
+-	      as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
+-		      bits[top->flag_code],
+-		      top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : "");
+	      extend_cpu_sub_arch_name (string + 1);
+	      cpu_arch_flags = flags;
+	      cpu_arch_isa_flags = flags;
+ 	    }
+ 	  else
+-	    {
+-	      arch_stack_top = top->prev;
+-
+-	      cpu_arch_name = top->name;
+-	      free (cpu_sub_arch_name);
+-	      cpu_sub_arch_name = top->sub_name;
+-	      cpu_arch_flags = top->flags;
+-	      cpu_arch_isa = top->isa;
+-	      cpu_arch_isa_flags = top->isa_flags;
+-	      no_cond_jump_promotion = top->no_cond_jump_promotion;
+-
+-	      XDELETE (top);
+-	    }
+	    cpu_arch_isa_flags
+	      = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[j].enable);
+ 
+ 	  (void) restore_line_pointer (e);
+ 	  demand_empty_rest_of_line ();
+ 	  return;
+ 	}
+    }
+ 
+-      for (; j < ARRAY_SIZE (cpu_arch); j++)
+-	{
+-	  if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0
+-	     && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE))
+-	    {
+-	      if (*string != '.')
+-		{
+-		  check_cpu_arch_compatible (string, cpu_arch[j].enable);
+-
+-		  cpu_arch_name = cpu_arch[j].name;
+-		  free (cpu_sub_arch_name);
+-		  cpu_sub_arch_name = NULL;
+-		  cpu_arch_flags = cpu_arch[j].enable;
+-		  if (flag_code == CODE_64BIT)
+-		    {
+-		      cpu_arch_flags.bitfield.cpu64 = 1;
+-		      cpu_arch_flags.bitfield.cpuno64 = 0;
+-		    }
+-		  else
+-		    {
+-		      cpu_arch_flags.bitfield.cpu64 = 0;
+-		      cpu_arch_flags.bitfield.cpuno64 = 1;
+-		    }
+-		  cpu_arch_isa = cpu_arch[j].type;
+-		  cpu_arch_isa_flags = cpu_arch[j].enable;
+-		  if (!cpu_arch_tune_set)
+-		    {
+-		      cpu_arch_tune = cpu_arch_isa;
+-		      cpu_arch_tune_flags = cpu_arch_isa_flags;
+-		    }
+-		  pre_386_16bit_warned = false;
+-		  break;
+-		}
+-
+-	      if (cpu_flags_all_zero (&cpu_arch[j].enable))
+-	        continue;
+-
+-	      flags = cpu_flags_or (cpu_arch_flags,
+-				    cpu_arch[j].enable);
+-
+-	      if (!cpu_flags_equal (&flags, &cpu_arch_flags))
+-		{
+-		  extend_cpu_sub_arch_name (string + 1);
+-		  cpu_arch_flags = flags;
+-		  cpu_arch_isa_flags = flags;
+-		}
+-	      else
+-		cpu_arch_isa_flags
+-		  = cpu_flags_or (cpu_arch_isa_flags,
+-				  cpu_arch[j].enable);
+-	      (void) restore_line_pointer (e);
+-	      demand_empty_rest_of_line ();
+-	      return;
+-	    }
+-	}
+-
+-      if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch))
+-	{
+-	  /* Disable an ISA extension.  */
+-	  for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
+-	    if (cpu_arch[j].type == PROCESSOR_NONE
+-	        && strcmp (string + 3, cpu_arch[j].name) == 0)
+  if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch))
+    {
+      /* Disable an ISA extension.  */
+      for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
+	if (cpu_arch[j].type == PROCESSOR_NONE
+	    && strcmp (string + 3, cpu_arch[j].name) == 0)
+	  {
+	    flags = cpu_flags_and_not (cpu_arch_flags, cpu_arch[j].disable);
+	    if (!cpu_flags_equal (&flags, &cpu_arch_flags))
+ 	      {
+-		flags = cpu_flags_and_not (cpu_arch_flags,
+-					   cpu_arch[j].disable);
+-		if (!cpu_flags_equal (&flags, &cpu_arch_flags))
+-		  {
+-		    extend_cpu_sub_arch_name (string + 1);
+-		    cpu_arch_flags = flags;
+-		    cpu_arch_isa_flags = flags;
+-		  }
+-		(void) restore_line_pointer (e);
+-		demand_empty_rest_of_line ();
+-		return;
+		extend_cpu_sub_arch_name (string + 1);
+		cpu_arch_flags = flags;
+		cpu_arch_isa_flags = flags;
+ 	      }
+-	}
+-
+-      if (j == ARRAY_SIZE (cpu_arch))
+-	as_bad (_("no such architecture: `%s'"), string);
+ 
+-      *input_line_pointer = e;
+	    (void) restore_line_pointer (e);
+	    demand_empty_rest_of_line ();
+	    return;
+	  }
+     }
+-  else
+-    as_bad (_("missing cpu architecture"));
+
+  if (j == ARRAY_SIZE (cpu_arch))
+    as_bad (_("no such architecture: `%s'"), string);
+
+  *input_line_pointer = e;
+ 
+   no_cond_jump_promotion = 0;
+   if (*input_line_pointer == ','
+       && !is_end_of_line[(unsigned char) input_line_pointer[1]])
+     {
+-      char *string;
+-      char e;
+-
+       ++input_line_pointer;
+-      e = get_symbol_name (&string);
+      e = get_symbol_name (&s);
+      string = s;
+ 
+       if (strcmp (string, "nojumps") == 0)
+ 	no_cond_jump_promotion = 1;
+-- 
+2.43.0
+
--- a/i686-AVX10.1-part-3.patch
+++ b/i686-AVX10.1-part-3.patch
@ -0,0 +1,160 @@
+diff -rup fred/gas/config/tc-i386.c binutils-2.41/gas/config/tc-i386.c
+--- fred/gas/config/tc-i386.c	2023-12-07 10:00:21.013005830 +0000
+++ binutils-2.41/gas/config/tc-i386.c	2023-12-07 10:00:28.037015037 +0000
+@@ -1053,8 +1053,8 @@ static const arch_entry cpu_arch[] =
+   SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false),
+   SUBARCH (xsaves, XSAVES, ANY_XSAVES, false),
+   SUBARCH (aes, AES, ANY_AES, false),
+-  SUBARCH (pclmul, PCLMUL, ANY_PCLMUL, false),
+-  SUBARCH (clmul, PCLMUL, ANY_PCLMUL, true),
+  SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false),
+  SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true),
+   SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false),
+   SUBARCH (rdrnd, RDRND, RDRND, false),
+   SUBARCH (f16c, F16C, ANY_F16C, false),
+@@ -1861,7 +1861,7 @@ cpu_flags_match (const insn_template *t)
+ 		      || (sse2avx && !i.prefix[DATA_PREFIX]))
+ 		  && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
+ 		  && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
+-		  && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
+		  && (!x.bitfield.cpupclmulqdq || cpu.bitfield.cpupclmulqdq))
+ 		match |= CPU_FLAGS_ARCH_MATCH;
+ 	    }
+ 	  else if (x.bitfield.cpuavx512f)
+diff -rup fred/opcodes/i386-gen.c binutils-2.41/opcodes/i386-gen.c
+--- fred/opcodes/i386-gen.c	2023-12-07 10:00:22.092007244 +0000
+++ binutils-2.41/opcodes/i386-gen.c	2023-12-07 10:00:28.038015039 +0000
+@@ -79,7 +79,7 @@ static const dependency isa_dependencies
+   { "AMDFAM10",
+     "K8|FISTTP|SSE4A|ABM|MONITOR" },
+   { "BDVER1",
+-    "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
+    "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMULQDQ|PRFCHW" },
+   { "BDVER2",
+     "BDVER1|FMA|BMI|TBM|F16C" },
+   { "BDVER3",
+@@ -87,7 +87,7 @@ static const dependency isa_dependencies
+   { "BDVER4",
+     "BDVER3|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
+   { "ZNVER1",
+-    "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
+    "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMULQDQ|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
+   { "ZNVER2",
+     "ZNVER1|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
+   { "ZNVER3",
+@@ -97,7 +97,7 @@ static const dependency isa_dependencies
+   { "BTVER1",
+     "GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
+   { "BTVER2",
+-    "BTVER1|AVX|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" },
+    "BTVER1|AVX|BMI|F16C|AES|PCLMULQDQ|Movbe|Xsaveopt|PRFCHW" },
+   { "286",
+     "186" },
+   { "386",
+@@ -132,7 +132,7 @@ static const dependency isa_dependencies
+     "XSAVE" },
+   { "AES",
+     "SSE2" },
+-  { "PCLMUL",
+  { "PCLMULQDQ",
+     "SSE2" },
+   { "FMA",
+     "AVX" },
+@@ -307,7 +307,7 @@ static bitfield cpu_flags[] =
+   BITFIELD (Xsave),
+   BITFIELD (Xsaveopt),
+   BITFIELD (AES),
+-  BITFIELD (PCLMUL),
+  BITFIELD (PCLMULQDQ),
+   BITFIELD (FMA),
+   BITFIELD (FMA4),
+   BITFIELD (XOP),
+diff -rup fred/opcodes/i386-init.h binutils-2.41/opcodes/i386-init.h
+--- fred/opcodes/i386-init.h	2023-12-07 10:00:22.092007244 +0000
+++ binutils-2.41/opcodes/i386-init.h	2023-12-07 10:00:51.260045479 +0000
+@@ -432,7 +432,7 @@
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
+ 
+-#define CPU_PCLMUL_FLAGS \
+#define CPU_PCLMULQDQ_FLAGS \
+   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+@@ -1791,7 +1791,7 @@
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
+ 
+-#define CPU_ANY_PCLMUL_FLAGS \
+#define CPU_ANY_PCLMULQDQ_FLAGS \
+   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+diff -rup fred/opcodes/i386-opc.h binutils-2.41/opcodes/i386-opc.h
+--- fred/opcodes/i386-opc.h	2023-12-07 10:00:22.093007246 +0000
+++ binutils-2.41/opcodes/i386-opc.h	2023-12-07 10:00:28.038015039 +0000
+@@ -121,8 +121,8 @@ enum
+   CpuXsaveopt,
+   /* AES support required */
+   CpuAES,
+-  /* PCLMUL support required */
+-  CpuPCLMUL,
+  /* PCLMULQDQ support required */
+  CpuPCLMULQDQ,
+   /* FMA support required */
+   CpuFMA,
+   /* FMA4 support required */
+@@ -374,7 +374,7 @@ typedef union i386_cpu_flags
+       unsigned int cpuxsave:1;
+       unsigned int cpuxsaveopt:1;
+       unsigned int cpuaes:1;
+-      unsigned int cpupclmul:1;
+      unsigned int cpupclmulqdq:1;
+       unsigned int cpufma:1;
+       unsigned int cpufma4:1;
+       unsigned int cpuxop:1;
+diff -rup fred/opcodes/i386-opc.tbl binutils-2.41/opcodes/i386-opc.tbl
+--- fred/opcodes/i386-opc.tbl	2023-12-07 10:00:22.093007246 +0000
+++ binutils-2.41/opcodes/i386-opc.tbl	2023-12-07 10:00:28.038015039 +0000
+@@ -1448,15 +1448,15 @@ vaesdeclast, 0x66df, VAES, Modrm|Vex256|
+ vaesenc, 0x66dc, VAES, Modrm|Vex256|Space0F38|VexVVVV|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
+ vaesenclast, 0x66dd, VAES, Modrm|Vex256|Space0F38|VexVVVV|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
+ 
+-// PCLMUL
+// PCLMULQDQ
+ 
+ <pclmul:cpu:attr, $avx:AVX|:Vex128|VexW0|SSE2AVX|VexVVVV, $sse::>
+ 
+-pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM }
+-pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+-pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+-pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+-pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM }
+pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
+ 
+ // GFNI
+ 
+@@ -1771,13 +1771,13 @@ vaesenclast, 0x66dd, AVX|AES, Modrm|Vex|
+ vaesimc, 0x66db, AVX|AES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
+ vaeskeygenassist, 0x66df, AVX|AES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
+ 
+-// PCLMUL + AVX
+// PCLMULQDQ + AVX
+ 
+-vpclmulqdq, 0x6644, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+-vpclmullqlqdq, 0x6644/0x00, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+-vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+-vpclmullqhqdq, 0x6644/0x10, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+-vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vpclmulqdq, 0x6644, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vpclmullqlqdq, 0x6644/0x00, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vpclmullqhqdq, 0x6644/0x10, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+ 
+ // GFNI + AVX
+ 
--- a/i686-AVX10.1-part-4.patch
+++ b/i686-AVX10.1-part-4.patch
--- a/i686-AVX10.1-part-5.patch
+++ b/i686-AVX10.1-part-5.patch
--- a/i686-AVX10.1-part-6.patch
+++ b/i686-AVX10.1-part-6.patch
--- a/plans/build-gating.fmf
+++ b/plans/build-gating.fmf
@ -5,14 +5,14 @@
 /common:
  plan:
    import:
-      url: https://gitlab.com/redhat/centos-stream/tests/binutils.git
+      url: https://src.fedoraproject.org/tests/binutils.git
      ref: main
      name: /plans/build-gating/common

 /kernel-rebuild:
  plan:
    import:
-      url: https://gitlab.com/redhat/centos-stream/tests/binutils.git
+      url: https://src.fedoraproject.org/tests/binutils.git
      ref: main
      name: /plans/build-gating/kernel-rebuild

--- a/plans/regression.fmf
+++ b/plans/regression.fmf
@ -5,7 +5,7 @@
 /common:
  plan:
    import:
-      url: https://gitlab.com/redhat/centos-stream/tests/binutils.git
+      url: https://src.fedoraproject.org/tests/binutils.git
      ref: main
      name: /plans/regression

--- a/2
+++ b/2
@ -1,2 +1,2 @@
-SHA512 (binutils-with-gold-2.47.50-48c933a69a8.tar.xz) = c4300e4881227c431c0bbbb949a5ee5bc113701f993766418b152df7d46d9df378ebace9efffcb6e1f0b7e72ad716bbcccf5b6aa55851dc28216555b242d18a0
+SHA512 (binutils-2.41.tar.xz) = 5df45d0bd6ddabdce4f35878c041e46a92deef01e7dea5facc97fd65cc06b59abc6fba0eb454b68e571c7e14038dc823fe7f2263843e6e627b7444eaf0fe9374
 SHA512 (binutils-2.19.50.0.1-output-format.sed) = 2f8686b0c8af13c98cda056824c2820416f6e2d003f70b78ccf5314525b9ee3684d421dfa83e638a2d42d06ea4d4bdaf5226b64d6ec26f7ff59c44ffb2a23dd2
--- a/spec.binutils.cross
+++ b/spec.binutils.cross
@ -0,0 +1,67 @@
+
+# Note - this is an rpm spec file, but it has been renamed in order to avoid
+# conflict with the real binutils.spec file.
+#
+# Its only use is to build a set of cross-binutils rpms by putting it into
+# the SPECS directory of an rpmbuild tree, installing the binutils source
+# rpm into the SOURCES directory and then running:
+#
+#    rpmbuild -bb spec.binutils.cross
+
+Summary: A meta collection of GNU binutils executables for cross builds
+Name: cross-binutils
+License: GPLv3+
+URL: https://sourceware.org/binutils
+
+#----------------------------------------------------------------------------
+#
+# Configurable settings - adjust to match your needs:
+#
+
+Version: 2.30
+Release: 89.el8
+
+# The list of cross architectures to build.
+# Note: this list assumes that we are building on an x86_64-linux-gnu host.
+
+%define arch_list  aarch64-linux-gnu  ppc64le-linux-gnu  s390x-linux-gnu
+
+#----------------------------------------------------------------------------
+
+%define binutils_source_rpm   binutils-%{version}-%{release}.src.rpm
+
+Source: %{binutils_source_rpm}
+
+# Provides: bundled(libiberty)
+
+BuildRequires: autoconf automake
+BuildRequires: perl, sed, coreutils
+BuildRequires: gcc, bison
+BuildRequires: gettext, flex, zlib-devel
+BuildRequires: findutils, texinfo
+BuildRequires: dejagnu, zlib-static, glibc-static, sharutils, bc
+# BuildRequires: elfutils-debuginfod-client-devel
+BuildRequires: rpm-build
+
+#----------------------------------------------------------------------------
+
+%description
+Provides a collection of cross built binutils for the targets
+supported by RHEL (aarch64, ppc64le, s390x).
+
+#----------------------------------------------------------------------------
+
+%build
+
+# Install the binutils sources.
+rpm -ivh %{_sourcedir}/%{binutils_source_rpm}
+
+# Build each set of cross binutils individually.
+for f in %{arch_list}; do
+  rpmbuild -bb --define "binutils_target $f" %{_specdir}/binutils.spec --without testsuite --without gold
+done
+
+#----------------------------------------------------------------------------
+%changelog
+* Wed Nov 11 2020 Nick Clifton  <nickc@redhat.com> - 2.35.1-14
+- First release of cross binutils rpm.
Author	SHA1	Message	Date
Nick Clifton	86b0f88b28	Adjust linker testsuite to account for compiler changes.	2024-11-26 20:15:45 +00:00
Björn Esser	75094e5df5	Fix ppc64 TLS optimization bug with -fno-plt code. Solution for PR 32387 Resolves: 2324491 Signed-off-by: Björn Esser <besser82@fedoraproject.org>	2024-11-26 12:13:53 +01:00
Benjamin Gilbert	e1c965554e	Backport commit bac5753ca24 to fix ld crash on LLVM-produced archives Resolves: #2278106	2024-05-03 09:54:40 +00:00
Nick Clifton	c76e72c911	Spec File: Stop %%verify(mtime) for ld.bfd. (#2277349 )	2024-04-29 13:03:45 +01:00
Nick Clifton	580d2a5659	Backport commit 5bc71c2a6b8 to fix APX support for R_X86_64_CODE_6_GOTTPOFF Resolves: #2273298	2024-04-05 13:00:21 +01:00