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1 commit
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ac510e7355 |
2 changed files with 229 additions and 1 deletions
221
capstone-x86-endbr.patch
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221
capstone-x86-endbr.patch
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@ -0,0 +1,221 @@
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From 1428c6813eb9708e2379a0a451d48ac8d424c2de Mon Sep 17 00:00:00 2001
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From: rpm-build <rpm-build>
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Date: Tue, 19 Feb 2019 11:13:06 +0100
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Subject: [PATCH] capstone-x86-endbr.patch
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---
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MCInst.c | 1 +
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MCInst.h | 1 +
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arch/X86/X86ATTInstPrinter.c | 5 ++++
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arch/X86/X86Disassembler.c | 38 +++++++++++++++++++++++++++
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arch/X86/X86GenInstrInfo.inc | 4 ++-
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arch/X86/X86IntelInstPrinter.c | 6 +++++
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arch/X86/X86Mapping.c | 2 ++
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bindings/java/capstone/X86_const.java | 6 +++--
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bindings/ocaml/x86_const.ml | 4 ++-
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bindings/python/capstone/x86_const.py | 4 ++-
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include/x86.h | 2 ++
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11 files changed, 68 insertions(+), 5 deletions(-)
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diff --git a/MCInst.c b/MCInst.c
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index 2c27f5e..0ab3159 100644
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--- a/MCInst.c
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+++ b/MCInst.c
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@@ -29,6 +29,7 @@ void MCInst_Init(MCInst *inst)
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inst->has_imm = false;
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inst->op1_size = 0;
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inst->writeback = false;
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+ inst->assembly[0] = '\0';
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}
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void MCInst_clear(MCInst *inst)
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diff --git a/MCInst.h b/MCInst.h
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index b98f37f..54f88fe 100644
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--- a/MCInst.h
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+++ b/MCInst.h
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@@ -106,6 +106,7 @@ struct MCInst {
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uint8_t x86_prefix[4];
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uint8_t imm_size; // immediate size for X86_OP_IMM operand
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bool writeback; // writeback for ARM
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+ char assembly[8]; // for special instruction, so that we dont need printer
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};
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void MCInst_Init(MCInst *inst);
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diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
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index f9a7c4a..152f2d1 100644
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--- a/arch/X86/X86ATTInstPrinter.c
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+++ b/arch/X86/X86ATTInstPrinter.c
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@@ -706,6 +706,11 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
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x86_reg reg, reg2;
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int i;
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+ if (MI->assembly[0]) {
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+ strncpy(OS->buffer, MI->assembly, sizeof(MI->assembly));
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+ return;
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+ }
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+
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// Output CALLpcrel32 as "callq" in 64-bit mode.
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// In Intel annotation it's always emitted as "call".
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//
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diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
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index 2c2d680..9fb17cb 100644
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--- a/arch/X86/X86Disassembler.c
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+++ b/arch/X86/X86Disassembler.c
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@@ -833,6 +833,44 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len,
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if (ret) {
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*size = (uint16_t)(insn.readerCursor - address);
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+ switch (*size) {
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+ default:
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+ break;
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+ case 4:
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+ if (handle->mode != CS_MODE_16) {
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+ unsigned char b1 = 0, b2 = 0, b3 = 0, b4 = 0;
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+
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+ reader(&info, &b1, address);
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+ reader(&info, &b2, address + 1);
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+ reader(&info, &b3, address + 2);
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+ reader(&info, &b4, address + 3);
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+ if (b1 == 0xf3 && b2 == 0x0f && b3 == 0x1e && b4 == 0xfa) {
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+ instr->Opcode = X86_ENDBR64;
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+ instr->OpcodePub = X86_INS_ENDBR64;
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+ strncpy(instr->assembly, "endbr64", 8);
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+ if (instr->flat_insn->detail) {
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+ instr->flat_insn->detail->x86.opcode[0] = b1;
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+ instr->flat_insn->detail->x86.opcode[1] = b2;
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+ instr->flat_insn->detail->x86.opcode[2] = b3;
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+ instr->flat_insn->detail->x86.opcode[3] = b4;
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+ }
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+ return true;
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+ } else if (b1 == 0xf3 && b2 == 0x0f && b3 == 0x1e && b4 == 0xfb) {
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+ instr->Opcode = X86_ENDBR32;
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+ instr->OpcodePub = X86_INS_ENDBR32;
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+ strncpy(instr->assembly, "endbr32", 8);
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+ if (instr->flat_insn->detail) {
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+ instr->flat_insn->detail->x86.opcode[0] = b1;
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+ instr->flat_insn->detail->x86.opcode[1] = b2;
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+ instr->flat_insn->detail->x86.opcode[2] = b3;
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+ instr->flat_insn->detail->x86.opcode[3] = b4;
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+ }
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+ return true;
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+ }
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+ }
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+ return false;
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+ }
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+
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return false;
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} else {
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*size = (uint16_t)insn.length;
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diff --git a/arch/X86/X86GenInstrInfo.inc b/arch/X86/X86GenInstrInfo.inc
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index ff50129..1a22066 100644
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--- a/arch/X86/X86GenInstrInfo.inc
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+++ b/arch/X86/X86GenInstrInfo.inc
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@@ -6281,7 +6281,9 @@ enum {
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X86_XSHA256 = 6264,
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X86_XSTORE = 6265,
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X86_XTEST = 6266,
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- X86_INSTRUCTION_LIST_END = 6267
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+ X86_ENDBR32 = 6267,
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+ X86_ENDBR64 = 6268,
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+ X86_INSTRUCTION_LIST_END = 6269
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};
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#endif // GET_INSTRINFO_ENUM
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diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
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index cc10141..06fe00f 100644
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--- a/arch/X86/X86IntelInstPrinter.c
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+++ b/arch/X86/X86IntelInstPrinter.c
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@@ -484,6 +484,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
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void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
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{
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x86_reg reg, reg2;
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+
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+ if (MI->assembly[0]) {
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+ strncpy(O->buffer, MI->assembly, sizeof(MI->assembly));
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+ return;
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+ }
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+
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#ifndef CAPSTONE_DIET
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char *mnem;
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diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c
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index 9b3609d..4515988 100644
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--- a/arch/X86/X86Mapping.c
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+++ b/arch/X86/X86Mapping.c
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@@ -2113,6 +2113,8 @@ static const name_map insn_name_maps[] = {
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{ X86_INS_XSHA256, "xsha256" },
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{ X86_INS_XSTORE, "xstore" },
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{ X86_INS_XTEST, "xtest" },
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+ { X86_INS_ENDBR32, "endbr32" },
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+ { X86_INS_ENDBR64, "endbr64" },
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};
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#endif
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diff --git a/bindings/java/capstone/X86_const.java b/bindings/java/capstone/X86_const.java
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index 6129e5f..936af67 100644
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--- a/bindings/java/capstone/X86_const.java
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+++ b/bindings/java/capstone/X86_const.java
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@@ -1631,7 +1631,9 @@ public class X86_const {
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public static final int X86_INS_XSHA256 = 1292;
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public static final int X86_INS_XSTORE = 1293;
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public static final int X86_INS_XTEST = 1294;
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- public static final int X86_INS_ENDING = 1295;
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+ public static final int X86_INS_ENDBR32 = 1295;
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+ public static final int X86_INS_ENDBR64 = 1296;
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+ public static final int X86_INS_ENDING = 1297;
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// Group of X86 instructions
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@@ -1687,4 +1689,4 @@ public class X86_const {
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public static final int X86_GRP_SMAP = 167;
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public static final int X86_GRP_NOVLX = 168;
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public static final int X86_GRP_ENDING = 169;
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-}
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\ No newline at end of file
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+}
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diff --git a/bindings/ocaml/x86_const.ml b/bindings/ocaml/x86_const.ml
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index 74b11ff..f2b97af 100644
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--- a/bindings/ocaml/x86_const.ml
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+++ b/bindings/ocaml/x86_const.ml
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@@ -1628,7 +1628,9 @@ let _X86_INS_XSHA1 = 1291;;
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let _X86_INS_XSHA256 = 1292;;
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let _X86_INS_XSTORE = 1293;;
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let _X86_INS_XTEST = 1294;;
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-let _X86_INS_ENDING = 1295;;
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+let _X86_INS_ENDBR32 = 1295;;
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+let _X86_INS_ENDBR64 = 1296;;
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+let _X86_INS_ENDING = 1297;;
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(* Group of X86 instructions *)
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diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py
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index 88bb60a..8430173 100644
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--- a/bindings/python/capstone/x86_const.py
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+++ b/bindings/python/capstone/x86_const.py
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@@ -1628,7 +1628,9 @@ X86_INS_XSHA1 = 1291
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X86_INS_XSHA256 = 1292
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X86_INS_XSTORE = 1293
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X86_INS_XTEST = 1294
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-X86_INS_ENDING = 1295
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+X86_INS_ENDBR32 = 1295
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+X86_INS_ENDBR64 = 1296
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+X86_INS_ENDING = 1297
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# Group of X86 instructions
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diff --git a/include/x86.h b/include/x86.h
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index 2dd162b..026a5bf 100644
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--- a/include/x86.h
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+++ b/include/x86.h
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@@ -1559,6 +1559,8 @@ typedef enum x86_insn {
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X86_INS_XSHA256,
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X86_INS_XSTORE,
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X86_INS_XTEST,
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+ X86_INS_ENDBR32,
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+ X86_INS_ENDBR64,
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X86_INS_ENDING, // mark the end of the list of insn
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} x86_insn;
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--
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2.20.1
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@ -1,6 +1,6 @@
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Name: capstone
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Version: 3.0.5
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Release: 1%{?dist}
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Release: 2%{?dist}
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Summary: A lightweight multi-platform, multi-architecture disassembly framework
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%global gituser aquynh
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@ -15,6 +15,9 @@ Source0: https://github.com/%{gituser}/%{gitname}/archive/%{commit}/%{nam
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# Fedora 29 makes python executable separate from python2 and python3. This patch makes
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# it possible to specify PYTHON2 and PYTHON3 binary to be explicit that by "python" we mean "python2"
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Patch0: capstone-python.patch
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# Add x86 endbr instructions that are very common in Fedora binaries because
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# they are compiled with support for Intel CET
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Patch1: capstone-x86-endbr.patch
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%if 0%{?fedora} > 12
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%global with_python3 1
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@ -173,6 +176,10 @@ make check LD_LIBRARY_PATH="`pwd`"
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%{_javadir}/
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%changelog
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* Tue Feb 19 2019 Riccardo Schirone <rschirone91@gmail.com> - 3.0.5-2
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- patch capstone to support endbr64/endbr32 instructions that were added in
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capstone 4.0
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* Mon Aug 27 2018 Michal Ambroz <rebus _AT seznam.cz> - 3.0.5-1
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- bump to 3.0.5
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