Linux v5.0.4
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Laura Abbott
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3 changed files with 5 additions and 533 deletions
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Sat, 12 Jan 2019 21:17:21 -0500 (EST)
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From: Samuel Holland <samuel@sholland.org>
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To: Catalin Marinas <catalin.marinas@arm.com>,
|
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Will Deacon <will.deacon@arm.com>,
|
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Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
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Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
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Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
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Subject: [PATCH v3 1/2] arm64: arch_timer: Workaround for Allwinner A64 timer
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instability
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Date: Sat, 12 Jan 2019 20:17:18 -0600
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The Allwinner A64 SoC is known[1] to have an unstable architectural
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timer, which manifests itself most obviously in the time jumping forward
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a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a
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timer frequency of 24 MHz, implying that the time went slightly backward
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(and this was interpreted by the kernel as it jumping forward and
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wrapping around past the epoch).
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Investigation revealed instability in the low bits of CNTVCT at the
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point a high bit rolls over. This leads to power-of-two cycle forward
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and backward jumps. (Testing shows that forward jumps are about twice as
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likely as backward jumps.) Since the counter value returns to normal
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after an indeterminate read, each "jump" really consists of both a
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forward and backward jump from the software perspective.
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Unless the kernel is trapping CNTVCT reads, a userspace program is able
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to read the register in a loop faster than it changes. A test program
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running on all 4 CPU cores that reported jumps larger than 100 ms was
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run for 13.6 hours and reported the following:
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Count | Event
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-------+---------------------------
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9940 | jumped backward 699ms
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268 | jumped backward 1398ms
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1 | jumped backward 2097ms
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16020 | jumped forward 175ms
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6443 | jumped forward 699ms
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2976 | jumped forward 1398ms
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9 | jumped forward 356516ms
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9 | jumped forward 357215ms
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4 | jumped forward 714430ms
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1 | jumped forward 3578440ms
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This works out to a jump larger than 100 ms about every 5.5 seconds on
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each CPU core.
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The largest jump (almost an hour!) was the following sequence of reads:
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0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
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Note that the middle bits don't necessarily all read as all zeroes or
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all ones during the anomalous behavior; however the low 10 bits checked
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by the function in this patch have never been observed with any other
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value.
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Also note that smaller jumps are much more common, with backward jumps
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of 2048 (2^11) cycles observed over 400 times per second on each core.
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(Of course, this is partially explained by lower bits rolling over more
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frequently.) Any one of these could have caused the 95 year time skip.
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Similar anomalies were observed while reading CNTPCT (after patching the
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kernel to allow reads from userspace). However, the CNTPCT jumps are
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much less frequent, and only small jumps were observed. The same program
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as before (except now reading CNTPCT) observed after 72 hours:
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Count | Event
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-------+---------------------------
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17 | jumped backward 699ms
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52 | jumped forward 175ms
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2831 | jumped forward 699ms
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5 | jumped forward 1398ms
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Further investigation showed that the instability in CNTPCT/CNTVCT also
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affected the respective timer's TVAL register. The following values were
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observed immediately after writing CNVT_TVAL to 0x10000000:
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CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
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--------------------+------------+--------------------+-----------------
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0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000
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0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000
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0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000
|
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0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000
|
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|
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The pattern of errors in CNTV_TVAL seemed to depend on exactly which
|
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value was written to it. For example, after writing 0x10101010:
|
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|
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CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
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--------------------+------------+--------------------+-----------------
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0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000
|
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0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000
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0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000
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0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000
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0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000
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0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000
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I was also twice able to reproduce the issue covered by Allwinner's
|
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workaround[4], that writing to TVAL sometimes fails, and both CVAL and
|
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TVAL are left with entirely bogus values. One was the following values:
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|
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CNTVCT | CNTV_TVAL | CNTV_CVAL
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--------------------+------------+--------------------------------------
|
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0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past)
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========================================================================
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Because the CPU can read the CNTPCT/CNTVCT registers faster than they
|
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change, performing two reads of the register and comparing the high bits
|
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(like other workarounds) is not a workable solution. And because the
|
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timer can jump both forward and backward, no pair of reads can
|
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distinguish a good value from a bad one. The only way to guarantee a
|
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good value from consecutive reads would be to read _three_ times, and
|
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take the middle value only if the three values are 1) each unique and
|
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2) increasing. This takes at minimum 3 counter cycles (125 ns), or more
|
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if an anomaly is detected.
|
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|
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However, since there is a distinct pattern to the bad values, we can
|
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optimize the common case (1022/1024 of the time) to a single read by
|
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simply ignoring values that match the error pattern. This still takes no
|
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more than 3 cycles in the worst case, and requires much less code. As an
|
||||
additional safety check, we still limit the loop iteration to the number
|
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of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods.
|
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|
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For the TVAL registers, the simple solution is to not use them. Instead,
|
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read or write the CVAL and calculate the TVAL value in software.
|
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|
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Although the manufacturer is aware of at least part of the erratum[4],
|
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there is no official name for it. For now, use the kernel-internal name
|
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"UNKNOWN1".
|
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|
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[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
|
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[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
|
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[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
|
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[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272
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|
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
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Tested-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
|
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---
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Documentation/arm64/silicon-errata.txt | 2 +
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drivers/clocksource/Kconfig | 10 +++++
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drivers/clocksource/arm_arch_timer.c | 55 ++++++++++++++++++++++++++
|
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3 files changed, 67 insertions(+)
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diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
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index 8f9577621144..4a269732d2a0 100644
|
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--- a/Documentation/arm64/silicon-errata.txt
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+++ b/Documentation/arm64/silicon-errata.txt
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@@ -44,6 +44,8 @@ stable kernels.
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| Implementor | Component | Erratum ID | Kconfig |
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+----------------+-----------------+-----------------+-----------------------------+
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+| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+| | | | |
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
|
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
|
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diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
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index 55c77e44bb2d..d20ff4da07c3 100644
|
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
|
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@@ -364,6 +364,16 @@ config ARM64_ERRATUM_858921
|
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The workaround will be dynamically enabled when an affected
|
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core is detected.
|
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|
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+config SUN50I_ERRATUM_UNKNOWN1
|
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+ bool "Workaround for Allwinner A64 erratum UNKNOWN1"
|
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+ default y
|
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+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
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+ select ARM_ARCH_TIMER_OOL_WORKAROUND
|
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+ help
|
||||
+ This option enables a workaround for instability in the timer on
|
||||
+ the Allwinner A64 SoC. The workaround will only be active if the
|
||||
+ allwinner,erratum-unknown1 property is found in the timer node.
|
||||
+
|
||||
config ARM_GLOBAL_TIMER
|
||||
bool "Support for the ARM global timer" if COMPILE_TEST
|
||||
select TIMER_OF if OF
|
||||
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
|
||||
index 9a7d4dc00b6e..a8b20b65bd4b 100644
|
||||
--- a/drivers/clocksource/arm_arch_timer.c
|
||||
+++ b/drivers/clocksource/arm_arch_timer.c
|
||||
@@ -326,6 +326,48 @@ static u64 notrace arm64_1188873_read_cntvct_el0(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
|
||||
+/*
|
||||
+ * The low bits of the counter registers are indeterminate while bit 10 or
|
||||
+ * greater is rolling over. Since the counter value can jump both backward
|
||||
+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
|
||||
+ * with all ones or all zeros in the low bits. Bound the loop by the maximum
|
||||
+ * number of CPU cycles in 3 consecutive 24 MHz counter periods.
|
||||
+ */
|
||||
+#define __sun50i_a64_read_reg(reg) ({ \
|
||||
+ u64 _val; \
|
||||
+ int _retries = 150; \
|
||||
+ \
|
||||
+ do { \
|
||||
+ _val = read_sysreg(reg); \
|
||||
+ _retries--; \
|
||||
+ } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
|
||||
+ \
|
||||
+ WARN_ON_ONCE(!_retries); \
|
||||
+ _val; \
|
||||
+})
|
||||
+
|
||||
+static u64 notrace sun50i_a64_read_cntpct_el0(void)
|
||||
+{
|
||||
+ return __sun50i_a64_read_reg(cntpct_el0);
|
||||
+}
|
||||
+
|
||||
+static u64 notrace sun50i_a64_read_cntvct_el0(void)
|
||||
+{
|
||||
+ return __sun50i_a64_read_reg(cntvct_el0);
|
||||
+}
|
||||
+
|
||||
+static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
|
||||
+{
|
||||
+ return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
|
||||
+}
|
||||
+
|
||||
+static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
|
||||
+{
|
||||
+ return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
|
||||
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
|
||||
@@ -423,6 +465,19 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
|
||||
.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
|
||||
},
|
||||
#endif
|
||||
+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
|
||||
+ {
|
||||
+ .match_type = ate_match_dt,
|
||||
+ .id = "allwinner,erratum-unknown1",
|
||||
+ .desc = "Allwinner erratum UNKNOWN1",
|
||||
+ .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
|
||||
+ .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
|
||||
+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
|
||||
+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
|
||||
+ .set_next_event_phys = erratum_set_next_event_tval_phys,
|
||||
+ .set_next_event_virt = erratum_set_next_event_tval_virt,
|
||||
+ },
|
||||
+#endif
|
||||
};
|
||||
|
||||
typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
|
||||
|
||||
From patchwork Sun Jan 13 02:17:19 2019
|
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X-Patchwork-Id: 10761195
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Sat, 12 Jan 2019 21:17:22 -0500 (EST)
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
To: Catalin Marinas <catalin.marinas@arm.com>,
|
||||
Will Deacon <will.deacon@arm.com>,
|
||||
Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
|
||||
Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
|
||||
Daniel Lezcano <daniel.lezcano@linaro.org>,
|
||||
Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
|
||||
Subject: [PATCH v3 2/2] arm64: dts: allwinner: a64: Enable A64 timer
|
||||
workaround
|
||||
Date: Sat, 12 Jan 2019 20:17:19 -0600
|
||||
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|
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|
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|
||||
|
||||
As instability in the architectural timer has been observed on multiple
|
||||
devices using this SoC, inluding the Pine64 and the Orange Pi Win,
|
||||
enable the workaround in the SoC's device tree.
|
||||
|
||||
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
index f3a66f888205..13eac92a8c55 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -175,6 +175,7 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
+ allwinner,erratum-unknown1;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14
|
||||
|
|
@ -54,7 +54,7 @@ Summary: The Linux kernel
|
|||
%if 0%{?released_kernel}
|
||||
|
||||
# Do we have a -stable update to apply?
|
||||
%define stable_update 3
|
||||
%define stable_update 4
|
||||
# Set rpm version accordingly
|
||||
%if 0%{?stable_update}
|
||||
%define stablerev %{stable_update}
|
||||
|
|
@ -594,10 +594,6 @@ Patch340: arm64-tegra-jetson-tx1-fixes.patch
|
|||
# https://patchwork.kernel.org/patch/10858639/
|
||||
Patch341: arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch
|
||||
|
||||
# Fix for AllWinner A64 Timer Errata, still not final
|
||||
# https://www.spinics.net/lists/arm-kernel/msg699622.html
|
||||
Patch350: Allwinner-A64-timer-workaround.patch
|
||||
|
||||
# 400 - IBM (ppc/s390x) patches
|
||||
|
||||
# 500 - Temp fixes/CVEs etc
|
||||
|
|
@ -1899,6 +1895,9 @@ fi
|
|||
#
|
||||
#
|
||||
%changelog
|
||||
* Mon Mar 25 2019 Laura Abbott <labbott@redhat.com> - 5.0.4-300
|
||||
- Linux v5.0.4
|
||||
|
||||
* Sat Mar 23 2019 Peter Robinson <pbrobinson@fedoraproject.org>
|
||||
- Fixes for Tegra Jetson TX series
|
||||
- Initial support for NVIDIA Jetson Nano
|
||||
|
|
|
|||
2
sources
2
sources
|
|
@ -1,2 +1,2 @@
|
|||
SHA512 (linux-5.0.tar.xz) = 3fbab70c7b03b1a10e9fa14d1e2e1f550faba4f5792b7699ca006951da74ab86e7d7f19c6a67849ab99343186e7d6f2752cd910d76222213b93c1eab90abf1b0
|
||||
SHA512 (patch-5.0.3.xz) = f14f1f456acacf9272cd07f1ed9da02ddeef98687b18cb9d62968689c055405b839c1b043e92ece6639afc035c67abe1187ee74b0271860b40824ad1bd130a48
|
||||
SHA512 (patch-5.0.4.xz) = 570d4a9142f67cda7de1e60d25afe85aabc64057008c5442c47e0b1b109a34d366cadc963be3896d4b50c1abdba8fb7b0ad42a8a811615f4953f7271b4422404
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue