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Justin M. Forbes 2019-07-09 13:27:52 -05:00
commit 5c2ab4e801
335 changed files with 6839 additions and 3227 deletions
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ARM-cpufreq-support-for-Raspberry-Pi.patch Normal file
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@ -0,0 +1,706 @@
From ba60a01e02086b0a242cf5ea3c59419108ada40b Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Date: Tue, 11 Jun 2019 19:58:34 +0200
Subject: [PATCH 1/5] clk: bcm2835: remove pllb
Raspberry Pi's firmware controls this pll, we should use the firmware
interface to access it.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
---
drivers/clk/bcm/clk-bcm2835.c | 28 ++++------------------------
1 file changed, 4 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 770bb01f523e..867ae3c20041 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1651,30 +1651,10 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.fixed_divider = 1,
.flags = CLK_SET_RATE_PARENT),
- /* PLLB is used for the ARM's clock. */
- [BCM2835_PLLB] = REGISTER_PLL(
- .name = "pllb",
- .cm_ctrl_reg = CM_PLLB,
- .a2w_ctrl_reg = A2W_PLLB_CTRL,
- .frac_reg = A2W_PLLB_FRAC,
- .ana_reg_base = A2W_PLLB_ANA0,
- .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
- .lock_mask = CM_LOCK_FLOCKB,
-
- .ana = &bcm2835_ana_default,
-
- .min_rate = 600000000u,
- .max_rate = 3000000000u,
- .max_fb_rate = BCM2835_MAX_FB_RATE),
- [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
- .name = "pllb_arm",
- .source_pll = "pllb",
- .cm_reg = CM_PLLB,
- .a2w_reg = A2W_PLLB_ARM,
- .load_mask = CM_PLLB_LOADARM,
- .hold_mask = CM_PLLB_HOLDARM,
- .fixed_divider = 1,
- .flags = CLK_SET_RATE_PARENT),
+ /*
+ * PLLB is used for the ARM's clock. Controlled by firmware, see
+ * clk-raspberrypi.c.
+ */
/*
* PLLC is the core PLL, used to drive the core VPU clock.
--
2.21.0
From 64482a97a0a2f14ebdbfe80a8eb0e063d293807b Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Wed, 12 Jun 2019 17:23:12 +0100
Subject: [PATCH 2/5] clk: bcm283x: add driver interfacing with Raspberry Pi's
firmware
Raspberry Pi's firmware offers an interface though which update it's
clock's frequencies. This is specially useful in order to change the CPU
clock (pllb_arm) which is 'owned' by the firmware and we're unable to
scale using the register interface provided by clk-bcm2835.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
drivers/clk/bcm/Kconfig | 7 +
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-raspberrypi.c | 300 ++++++++++++++++++++++++++++++
3 files changed, 308 insertions(+)
create mode 100644 drivers/clk/bcm/clk-raspberrypi.c
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 29ee7b776cd4..a4a2775d65e1 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -64,3 +64,10 @@ config CLK_BCM_SR
default ARCH_BCM_IPROC
help
Enable common clock framework support for the Broadcom Stingray SoC
+
+config CLK_RASPBERRYPI
+ tristate "Raspberry Pi firmware based clock support"
+ depends on RASPBERRYPI_FIRMWARE || (COMPILE_TEST && !RASPBERRYPI_FIRMWARE)
+ help
+ Enable common clock framework support for Raspberry Pi's firmware
+ dependent clocks
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 002661d39128..eb7159099d82 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835-aux.o
+obj-$(CONFIG_CLK_RASPBERRYPI) += clk-raspberrypi.o
obj-$(CONFIG_ARCH_BCM_53573) += clk-bcm53573-ilp.o
obj-$(CONFIG_CLK_BCM_CYGNUS) += clk-cygnus.o
obj-$(CONFIG_CLK_BCM_HR2) += clk-hr2.o
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
new file mode 100644
index 000000000000..467933767106
--- /dev/null
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Raspberry Pi driver for firmware controlled clocks
+ *
+ * Even though clk-bcm2835 provides an interface to the hardware registers for
+ * the system clocks we've had to factor out 'pllb' as the firmware 'owns' it.
+ * We're not allowed to change it directly as we might race with the
+ * over-temperature and under-voltage protections provided by the firmware.
+ *
+ * Copyright (C) 2019 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <soc/bcm2835/raspberrypi-firmware.h>
+
+#define RPI_FIRMWARE_ARM_CLK_ID 0x000000003
+
+#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
+#define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1)
+
+/*
+ * Even though the firmware interface alters 'pllb' the frequencies are
+ * provided as per 'pllb_arm'. We need to scale before passing them trough.
+ */
+#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE 2
+
+#define A2W_PLL_FRAC_BITS 20
+
+struct raspberrypi_clk {
+ struct device *dev;
+ struct rpi_firmware *firmware;
+
+ unsigned long min_rate;
+ unsigned long max_rate;
+
+ struct clk_hw pllb;
+ struct clk_hw *pllb_arm;
+ struct clk_lookup *pllb_arm_lookup;
+};
+
+/*
+ * Structure of the message passed to Raspberry Pi's firmware in order to
+ * change clock rates. The 'disable_turbo' option is only available to the ARM
+ * clock (pllb) which we enable by default as turbo mode will alter multiple
+ * clocks at once.
+ *
+ * Even though we're able to access the clock registers directly we're bound to
+ * use the firmware interface as the firmware ultimately takes care of
+ * mitigating overheating/undervoltage situations and we would be changing
+ * frequencies behind his back.
+ *
+ * For more information on the firmware interface check:
+ * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
+ */
+struct raspberrypi_firmware_prop {
+ __le32 id;
+ __le32 val;
+ __le32 disable_turbo;
+} __packed;
+
+static int raspberrypi_clock_property(struct rpi_firmware *firmware, u32 tag,
+ u32 clk, u32 *val)
+{
+ struct raspberrypi_firmware_prop msg = {
+ .id = clk,
+ .val = *val,
+ .disable_turbo = 1,
+ };
+ int ret;
+
+ ret = rpi_firmware_property(firmware, tag, &msg, sizeof(msg));
+ if (ret)
+ return ret;
+
+ *val = msg.val;
+
+ return 0;
+}
+
+static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
+{
+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
+ pllb);
+ u32 val = 0;
+ int ret;
+
+ ret = raspberrypi_clock_property(rpi->firmware,
+ RPI_FIRMWARE_GET_CLOCK_STATE,
+ RPI_FIRMWARE_ARM_CLK_ID, &val);
+ if (ret)
+ return 0;
+
+ return !!(val & RPI_FIRMWARE_STATE_ENABLE_BIT);
+}
+
+
+static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
+ pllb);
+ u32 val = 0;
+ int ret;
+
+ ret = raspberrypi_clock_property(rpi->firmware,
+ RPI_FIRMWARE_GET_CLOCK_RATE,
+ RPI_FIRMWARE_ARM_CLK_ID,
+ &val);
+ if (ret)
+ return ret;
+
+ return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+}
+
+static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
+ pllb);
+ u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+ int ret;
+
+ ret = raspberrypi_clock_property(rpi->firmware,
+ RPI_FIRMWARE_SET_CLOCK_RATE,
+ RPI_FIRMWARE_ARM_CLK_ID,
+ &new_rate);
+ if (ret)
+ dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
+ clk_hw_get_name(hw), ret);
+
+ return ret;
+}
+
+/*
+ * Sadly there is no firmware rate rounding interface. We borrowed it from
+ * clk-bcm2835.
+ */
+static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
+ pllb);
+ u64 div, final_rate;
+ u32 ndiv, fdiv;
+
+ /* We can't use req->rate directly as it would overflow */
+ final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
+
+ div = (u64)final_rate << A2W_PLL_FRAC_BITS;
+ do_div(div, req->best_parent_rate);
+
+ ndiv = div >> A2W_PLL_FRAC_BITS;
+ fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
+
+ final_rate = ((u64)req->best_parent_rate *
+ ((ndiv << A2W_PLL_FRAC_BITS) + fdiv));
+
+ req->rate = final_rate >> A2W_PLL_FRAC_BITS;
+
+ return 0;
+}
+
+static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
+ .is_prepared = raspberrypi_fw_pll_is_on,
+ .recalc_rate = raspberrypi_fw_pll_get_rate,
+ .set_rate = raspberrypi_fw_pll_set_rate,
+ .determine_rate = raspberrypi_pll_determine_rate,
+};
+
+static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
+{
+ u32 min_rate = 0, max_rate = 0;
+ struct clk_init_data init;
+ int ret;
+
+ memset(&init, 0, sizeof(init));
+
+ /* All of the PLLs derive from the external oscillator. */
+ init.parent_names = (const char *[]){ "osc" };
+ init.num_parents = 1;
+ init.name = "pllb";
+ init.ops = &raspberrypi_firmware_pll_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
+
+ /* Get min & max rates set by the firmware */
+ ret = raspberrypi_clock_property(rpi->firmware,
+ RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
+ RPI_FIRMWARE_ARM_CLK_ID,
+ &min_rate);
+ if (ret) {
+ dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
+ init.name, ret);
+ return ret;
+ }
+
+ ret = raspberrypi_clock_property(rpi->firmware,
+ RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
+ RPI_FIRMWARE_ARM_CLK_ID,
+ &max_rate);
+ if (ret) {
+ dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
+ init.name, ret);
+ return ret;
+ }
+
+ if (!min_rate || !max_rate) {
+ dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n",
+ min_rate, max_rate);
+ return -EINVAL;
+ }
+
+ dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
+ min_rate, max_rate);
+
+ rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+ rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+
+ rpi->pllb.init = &init;
+
+ return devm_clk_hw_register(rpi->dev, &rpi->pllb);
+}
+
+static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
+{
+ rpi->pllb_arm = clk_hw_register_fixed_factor(rpi->dev,
+ "pllb_arm", "pllb",
+ CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ 1, 2);
+ if (IS_ERR(rpi->pllb_arm)) {
+ dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
+ return PTR_ERR(rpi->pllb_arm);
+ }
+
+ rpi->pllb_arm_lookup = clkdev_hw_create(rpi->pllb_arm, NULL, "cpu0");
+ if (!rpi->pllb_arm_lookup) {
+ dev_err(rpi->dev, "Failed to initialize pllb_arm_lookup\n");
+ clk_hw_unregister_fixed_factor(rpi->pllb_arm);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int raspberrypi_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *firmware_node;
+ struct device *dev = &pdev->dev;
+ struct rpi_firmware *firmware;
+ struct raspberrypi_clk *rpi;
+ int ret;
+
+ firmware_node = of_find_compatible_node(NULL, NULL,
+ "raspberrypi,bcm2835-firmware");
+ if (!firmware_node) {
+ dev_err(dev, "Missing firmware node\n");
+ return -ENOENT;
+ }
+
+ firmware = rpi_firmware_get(firmware_node);
+ of_node_put(firmware_node);
+ if (!firmware)
+ return -EPROBE_DEFER;
+
+ rpi = devm_kzalloc(dev, sizeof(*rpi), GFP_KERNEL);
+ if (!rpi)
+ return -ENOMEM;
+
+ rpi->dev = dev;
+ rpi->firmware = firmware;
+
+ ret = raspberrypi_register_pllb(rpi);
+ if (ret) {
+ dev_err(dev, "Failed to initialize pllb, %d\n", ret);
+ return ret;
+ }
+
+ ret = raspberrypi_register_pllb_arm(rpi);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct platform_driver raspberrypi_clk_driver = {
+ .driver = {
+ .name = "raspberrypi-clk",
+ },
+ .probe = raspberrypi_clk_probe,
+};
+module_platform_driver(raspberrypi_clk_driver);
+
+MODULE_AUTHOR("Nicolas Saenz Julienne <nsaenzjulienne@suse.de>");
+MODULE_DESCRIPTION("Raspberry Pi firmware clock driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:raspberrypi-clk");
--
2.21.0
From e750e62addb9ee00f47ab4a73c0645d44172ab12 Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Date: Tue, 11 Jun 2019 19:58:38 +0200
Subject: [PATCH 3/5] firmware: raspberrypi: register clk device
Since clk-raspberrypi is tied to the VC4 firmware instead of particular
hardware it's registration should be performed by the firmware driver.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
---
drivers/firmware/raspberrypi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c
index 61be15d9df7d..da26a584dca0 100644
--- a/drivers/firmware/raspberrypi.c
+++ b/drivers/firmware/raspberrypi.c
@@ -20,6 +20,7 @@
#define MBOX_CHAN_PROPERTY 8
static struct platform_device *rpi_hwmon;
+static struct platform_device *rpi_clk;
struct rpi_firmware {
struct mbox_client cl;
@@ -207,6 +208,12 @@ rpi_register_hwmon_driver(struct device *dev, struct rpi_firmware *fw)
-1, NULL, 0);
}
+static void rpi_register_clk_driver(struct device *dev)
+{
+ rpi_clk = platform_device_register_data(dev, "raspberrypi-clk",
+ -1, NULL, 0);
+}
+
static int rpi_firmware_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -234,6 +241,7 @@ static int rpi_firmware_probe(struct platform_device *pdev)
rpi_firmware_print_firmware_revision(fw);
rpi_register_hwmon_driver(dev, fw);
+ rpi_register_clk_driver(dev);
return 0;
}
@@ -254,6 +262,8 @@ static int rpi_firmware_remove(struct platform_device *pdev)
platform_device_unregister(rpi_hwmon);
rpi_hwmon = NULL;
+ platform_device_unregister(rpi_clk);
+ rpi_clk = NULL;
mbox_free_channel(fw->chan);
return 0;
--
2.21.0
From a94ed1abc52b51c55454b3f1a7181af9d91d9d73 Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Date: Tue, 11 Jun 2019 19:58:40 +0200
Subject: [PATCH 4/5] cpufreq: add driver for Raspbery Pi
Raspberry Pi's firmware offers and interface though which update it's
performance requirements. It allows us to request for specific runtime
frequencies, which the firmware might or might not respect, depending on
the firmware configuration and thermals.
As the maximum and minimum frequencies are configurable in the firmware
there is no way to know in advance their values. So the Raspberry Pi
cpufreq driver queries them, builds an opp frequency table to then
launch cpufreq-dt.
Also, as the firmware interface might be configured as a module, making
the cpu clock unavailable during init, this implements a full fledged
driver, as opposed to most drivers registering cpufreq-dt, which only
make use of an init routine.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/cpufreq/Kconfig.arm | 8 +++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/raspberrypi-cpufreq.c | 97 +++++++++++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 drivers/cpufreq/raspberrypi-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index f8129edc145e..5e9204d443ff 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -133,6 +133,14 @@ config ARM_QCOM_CPUFREQ_HW
The driver implements the cpufreq interface for this HW engine.
Say Y if you want to support CPUFreq HW.
+config ARM_RASPBERRYPI_CPUFREQ
+ tristate "Raspberry Pi cpufreq support"
+ depends on CLK_RASPBERRYPI || COMPILE_TEST
+ help
+ This adds the CPUFreq driver for Raspberry Pi
+
+ If in doubt, say N.
+
config ARM_S3C_CPUFREQ
bool
help
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 689b26c6f949..121c1acb66c0 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o
obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
+obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/raspberrypi-cpufreq.c b/drivers/cpufreq/raspberrypi-cpufreq.c
new file mode 100644
index 000000000000..2bc7d9734272
--- /dev/null
+++ b/drivers/cpufreq/raspberrypi-cpufreq.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Raspberry Pi cpufreq driver
+ *
+ * Copyright (C) 2019, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+
+#define RASPBERRYPI_FREQ_INTERVAL 100000000
+
+static struct platform_device *cpufreq_dt;
+
+static int raspberrypi_cpufreq_probe(struct platform_device *pdev)
+{
+ struct device *cpu_dev;
+ unsigned long min, max;
+ unsigned long rate;
+ struct clk *clk;
+ int ret;
+
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev) {
+ pr_err("Cannot get CPU for cpufreq driver\n");
+ return -ENODEV;
+ }
+
+ clk = clk_get(cpu_dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(cpu_dev, "Cannot get clock for CPU0\n");
+ return PTR_ERR(clk);
+ }
+
+ /*
+ * The max and min frequencies are configurable in the Raspberry Pi
+ * firmware, so we query them at runtime.
+ */
+ min = roundup(clk_round_rate(clk, 0), RASPBERRYPI_FREQ_INTERVAL);
+ max = roundup(clk_round_rate(clk, ULONG_MAX), RASPBERRYPI_FREQ_INTERVAL);
+ clk_put(clk);
+
+ for (rate = min; rate <= max; rate += RASPBERRYPI_FREQ_INTERVAL) {
+ ret = dev_pm_opp_add(cpu_dev, rate, 0);
+ if (ret)
+ goto remove_opp;
+ }
+
+ cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
+ ret = PTR_ERR_OR_ZERO(cpufreq_dt);
+ if (ret) {
+ dev_err(cpu_dev, "Failed to create platform device, %d\n", ret);
+ goto remove_opp;
+ }
+
+ return 0;
+
+remove_opp:
+ dev_pm_opp_remove_all_dynamic(cpu_dev);
+
+ return ret;
+}
+
+static int raspberrypi_cpufreq_remove(struct platform_device *pdev)
+{
+ struct device *cpu_dev;
+
+ cpu_dev = get_cpu_device(0);
+ if (cpu_dev)
+ dev_pm_opp_remove_all_dynamic(cpu_dev);
+
+ platform_device_unregister(cpufreq_dt);
+
+ return 0;
+}
+
+/*
+ * Since the driver depends on clk-raspberrypi, which may return EPROBE_DEFER,
+ * all the activity is performed in the probe, which may be defered as well.
+ */
+static struct platform_driver raspberrypi_cpufreq_driver = {
+ .driver = {
+ .name = "raspberrypi-cpufreq",
+ },
+ .probe = raspberrypi_cpufreq_probe,
+ .remove = raspberrypi_cpufreq_remove,
+};
+module_platform_driver(raspberrypi_cpufreq_driver);
+
+MODULE_AUTHOR("Nicolas Saenz Julienne <nsaenzjulienne@suse.de");
+MODULE_DESCRIPTION("Raspberry Pi cpufreq driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:raspberrypi-cpufreq");
--
2.21.0
From af32d83d10976ff357c56adba79fa3cb06e1c32d Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Date: Tue, 11 Jun 2019 19:58:42 +0200
Subject: [PATCH 5/5] clk: raspberrypi: register platform device for
raspberrypi-cpufreq
As 'clk-raspberrypi' depends on RPi's firmware interface, which might be
configured as a module, the cpu clock might not be available for the
cpufreq driver during it's init process. So we register the
'raspberrypi-cpufreq' platform device after the probe sequence succeeds.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
---
drivers/clk/bcm/clk-raspberrypi.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index 467933767106..7f9b001f8d70 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -34,6 +34,7 @@
struct raspberrypi_clk {
struct device *dev;
struct rpi_firmware *firmware;
+ struct platform_device *cpufreq;
unsigned long min_rate;
unsigned long max_rate;
@@ -272,6 +273,7 @@ static int raspberrypi_clk_probe(struct platform_device *pdev)
rpi->dev = dev;
rpi->firmware = firmware;
+ platform_set_drvdata(pdev, rpi);
ret = raspberrypi_register_pllb(rpi);
if (ret) {
@@ -283,6 +285,18 @@ static int raspberrypi_clk_probe(struct platform_device *pdev)
if (ret)
return ret;
+ rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq",
+ -1, NULL, 0);
+
+ return 0;
+}
+
+static int raspberrypi_clk_remove(struct platform_device *pdev)
+{
+ struct raspberrypi_clk *rpi = platform_get_drvdata(pdev);
+
+ platform_device_unregister(rpi->cpufreq);
+
return 0;
}
@@ -291,6 +305,7 @@ static struct platform_driver raspberrypi_clk_driver = {
.name = "raspberrypi-clk",
},
.probe = raspberrypi_clk_probe,
+ .remove = raspberrypi_clk_remove,
};
module_platform_driver(raspberrypi_clk_driver);
--
2.21.0

8
Kbuild-Add-an-option-to-enable-GCC-VTA.patch
View file

@ -49,11 +49,11 @@ index 9ef547fc7ffe..5777d902f8f3 100644
--- a/Makefile
+++ b/Makefile
@@ -735,7 +735,11 @@ KBUILD_CFLAGS += -fomit-frame-pointer
endif
KBUILD_CFLAGS += -ftrivial-auto-var-init=pattern
endif
+ifdef CONFIG_DEBUG_INFO_VTA
+DEBUG_CFLAGS += $(call cc-option, -fvar-tracking-assignments)
+DEBUG_CFLAGS += $(call cc-option, -fvar-tracking-assignments)
+else
DEBUG_CFLAGS := $(call cc-option, -fno-var-tracking-assignments)
+endif
@ -87,8 +87,8 @@ index 0d9e81779e37..424206212931 100644
+ environment to automatically compile everything both ways,
+ generating an error if anything differs.
config GDB_SCRIPTS
bool "Provide GDB scripts for kernel debugging"
config DEBUG_INFO_BTF
bool "Generate BTF typeinfo"
--
2.20.1

41
arm64-acpi-ignore-5.1-fadts-reported-as-5.0.patch Normal file
View file

@ -0,0 +1,41 @@
From a7edc17544709d20f800dc0898096365a3d68613 Mon Sep 17 00:00:00 2001
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Sun, 2 Jun 2019 16:36:15 +0200
Subject: [PATCH] acpi/arm64: ignore 5.1 FADTs that are reported as 5.0
Some Qualcomm Snapdragon based laptops built to run Microsoft Windows
are clearly ACPI 5.1 based, given that that is the first ACPI revision
that supports ARM, and introduced the FADT 'arm_boot_flags' field,
which has a non-zero field on those systems.
So in these cases, infer from the ARM boot flags that the FADT must be
5.1 or later, and treat it as 5.1.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/kernel/acpi.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 803f0494dd3e3..7722e85fb69c3 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -155,10 +155,14 @@ static int __init acpi_fadt_sanity_check(void)
*/
if (table->revision < 5 ||
(table->revision == 5 && fadt->minor_revision < 1)) {
- pr_err("Unsupported FADT revision %d.%d, should be 5.1+\n",
+ pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 5.1+\n",
table->revision, fadt->minor_revision);
- ret = -EINVAL;
- goto out;
+
+ if (!fadt->arm_boot_flags) {
+ ret = -EINVAL;
+ goto out;
+ }
+ pr_err("FADT has ARM boot flags set, assuming 5.1\n");
}
if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) {

30
arm64-acpi-make-ac-and-battery-drivers-available-on-non-x86.patch Normal file
View file

@ -0,0 +1,30 @@
From 7b87bc98ab598ae40ef1818fb0c420d61dd87ed1 Mon Sep 17 00:00:00 2001
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Mon, 3 Jun 2019 08:37:11 +0200
Subject: [PATCH] acpi: make AC and battery drivers available on !X86
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
drivers/acpi/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index e016f7a6ed136..3c8011e7b0d7c 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -155,7 +155,6 @@ config ACPI_EC_DEBUGFS
config ACPI_AC
tristate "AC Adapter"
- depends on X86
select POWER_SUPPLY
default y
help
@@ -168,7 +167,6 @@ config ACPI_AC
config ACPI_BATTERY
tristate "Battery"
- depends on X86
select POWER_SUPPLY
default y
help

145
arm64-dts-rockchip-Update-DWC3-modules-on-RK3399-SoCs.patch Normal file
View file

@ -0,0 +1,145 @@
From patchwork Thu Jun 13 16:27:45 2019
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From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: devicetree@vger.kernel.org
Subject: [PATCH] arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs
Date: Thu, 13 Jun 2019 18:27:45 +0200
Message-Id: <20190613162745.12195-1-enric.balletbo@collabora.com>
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As per binding documentation [1], the DWC3 core should have the "ref",
"bus_early" and "suspend" clocks. As explained in the binding, those
clocks are required for new platforms but not for existing platforms
before commit fe8abf332b8f ("usb: dwc3: support clocks and resets for
DWC3 core").
However, as those clocks are really treated as required, this ends with
having some annoying messages when the "rockchip,rk3399-dwc3" is used:
[ 1.724107] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2
[ 1.731893] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2
[ 2.495937] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2
[ 2.647239] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2
In order to remove those annoying messages, update the DWC3 hardware
module node and add all the required clocks. With this change, both, the
glue node and the DWC3 core node, have the clocks defined, but that's
not really a problem and there isn't a side effect on do this. So, we
can get rid of the annoying get clk error messages.
[1] Documentation/devicetree/bindings/usb/dwc3.txt
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 196ac9b78076..a15348d185ce 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -414,6 +414,9 @@
compatible = "snps,dwc3";
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
+ <&cru SCLK_USB3OTG0_SUSPEND>;
+ clock-names = "ref", "bus_early", "suspend";
dr_mode = "otg";
phys = <&u2phy0_otg>, <&tcphy0_usb3>;
phy-names = "usb2-phy", "usb3-phy";
@@ -447,6 +450,9 @@
compatible = "snps,dwc3";
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
+ <&cru SCLK_USB3OTG1_SUSPEND>;
+ clock-names = "ref", "bus_early", "suspend";
dr_mode = "otg";
phys = <&u2phy1_otg>, <&tcphy1_usb3>;
phy-names = "usb2-phy", "usb3-phy";

1002
arm64-qcom-DWC3-USB-Add-support-for-ACPI-based-AArch64-Laptops.patch Normal file
View file

File diff suppressed because it is too large Load diff

293
arm64-qcom-pinctrl-support-for-ACPI.patch Normal file
View file

@ -0,0 +1,293 @@
From 0ab5b9df0c9f07ae747ddc678d4e423c42f69624 Mon Sep 17 00:00:00 2001
From: Lee Jones <lee.jones@linaro.org>
Date: Mon, 10 Jun 2019 09:42:06 +0100
Subject: [PATCH 1/8] i2c: i2c-qcom-geni: Provide support for ACPI
Add a match table to allow automatic probing of ACPI device
QCOM0220. Ignore clock attainment errors. Set default clock
frequency value.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
drivers/i2c/busses/i2c-qcom-geni.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index db075bc0d952..9e3b8a98688d 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
@@ -483,6 +484,14 @@ static const struct i2c_algorithm geni_i2c_algo = {
.functionality = geni_i2c_func,
};
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id geni_i2c_acpi_match[] = {
+ { "QCOM0220"},
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
+#endif
+
static int geni_i2c_probe(struct platform_device *pdev)
{
struct geni_i2c_dev *gi2c;
@@ -502,7 +511,7 @@ static int geni_i2c_probe(struct platform_device *pdev)
return PTR_ERR(gi2c->se.base);
gi2c->se.clk = devm_clk_get(&pdev->dev, "se");
- if (IS_ERR(gi2c->se.clk)) {
+ if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(&pdev->dev)) {
ret = PTR_ERR(gi2c->se.clk);
dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
return ret;
@@ -516,6 +525,9 @@ static int geni_i2c_probe(struct platform_device *pdev)
gi2c->clk_freq_out = KHZ(100);
}
+ if (has_acpi_companion(&pdev->dev))
+ ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(&pdev->dev));
+
gi2c->irq = platform_get_irq(pdev, 0);
if (gi2c->irq < 0) {
dev_err(&pdev->dev, "IRQ error for i2c-geni\n");
@@ -660,6 +672,7 @@ static struct platform_driver geni_i2c_driver = {
.name = "geni_i2c",
.pm = &geni_i2c_pm_ops,
.of_match_table = geni_i2c_dt_match,
+ .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
},
};
--
2.21.0
From 5a0639fed6e05977d85c4824354e73d0a2fa92ef Mon Sep 17 00:00:00 2001
From: Lee Jones <lee.jones@linaro.org>
Date: Mon, 10 Jun 2019 09:42:07 +0100
Subject: [PATCH 2/8] i2c: i2c-qcom-geni: Signify successful driver probe
The Qualcomm Geni I2C driver currently probes silently which can be
confusing when debugging potential issues. Add a low level (INFO)
print when each I2C controller is successfully initially set-up.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
drivers/i2c/busses/i2c-qcom-geni.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 9e3b8a98688d..a89bfce5388e 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -596,6 +596,8 @@ static int geni_i2c_probe(struct platform_device *pdev)
return ret;
}
+ dev_dbg(&pdev->dev, "Geni-I2C adaptor successfully added\n");
+
return 0;
}
--
2.21.0
From 6f202eb6dbccf3172616a620faf934bf6195a0f9 Mon Sep 17 00:00:00 2001
From: Lee Jones <lee.jones@linaro.org>
Date: Mon, 10 Jun 2019 09:42:08 +0100
Subject: [PATCH 3/8] pinctrl: msm: Add ability for drivers to supply a
reserved GPIO list
When booting MSM based platforms with Device Tree or some ACPI
implementations, it is possible to provide a list of reserved pins
via the 'gpio-reserved-ranges' and 'gpios' properties respectively.
However some ACPI tables are not populated with this information,
thus it has to come from a knowledgable device driver instead.
Here we provide the MSM common driver with additional support to
parse this informtion and correctly populate the widely used
'valid_mask'.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 18 ++++++++++++++++++
drivers/pinctrl/qcom/pinctrl-msm.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 6e319bcc2326..80682b017a47 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -599,8 +599,23 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *chip)
int ret;
unsigned int len, i;
unsigned int max_gpios = pctrl->soc->ngpios;
+ const int *reserved = pctrl->soc->reserved_gpios;
u16 *tmp;
+ /* Driver provided reserved list overrides DT and ACPI */
+ if (reserved) {
+ bitmap_fill(chip->valid_mask, max_gpios);
+ for (i = 0; reserved[i] >= 0; i++) {
+ if (i >= max_gpios || reserved[i] >= max_gpios) {
+ dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
+ return -EINVAL;
+ }
+ clear_bit(reserved[i], chip->valid_mask);
+ }
+
+ return 0;
+ }
+
/* The number of GPIOs in the ACPI tables */
len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL,
0);
@@ -956,6 +971,9 @@ static void msm_gpio_irq_handler(struct irq_desc *desc)
static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
{
+ if (pctrl->soc->reserved_gpios)
+ return true;
+
return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index b724581c605c..48569cda8471 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -113,6 +113,7 @@ struct msm_pinctrl_soc_data {
bool pull_no_keeper;
const char *const *tiles;
unsigned int ntiles;
+ const int *reserved_gpios;
};
extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
--
2.21.0
From 568ff4c9723d761164416fdf876232f5b14cf3ad Mon Sep 17 00:00:00 2001
From: Lee Jones <lee.jones@linaro.org>
Date: Mon, 10 Jun 2019 09:42:09 +0100
Subject: [PATCH 4/8] pinctrl: qcom: sdm845: Provide ACPI support
This patch provides basic support for booting with ACPI instead
of the currently supported Device Tree. When doing so there are a
couple of differences which we need to taken into consideration.
Firstly, the SDM850 ACPI tables omit information pertaining to the
4 reserved GPIOs on the platform. If Linux attempts to touch/
initialise any of these lines, the firmware will restart the
platform.
Secondly, when booting with ACPI, it is expected that the firmware
will set-up things like; Regulators, Clocks, Pin Functions, etc in
their ideal configuration. Thus, the possible Pin Functions
available to this platform are not advertised when providing the
higher GPIOD/Pinctrl APIs with pin information.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
drivers/pinctrl/qcom/Kconfig | 2 +-
drivers/pinctrl/qcom/pinctrl-sdm845.c | 36 ++++++++++++++++++++++++++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 890d0a3a790b..27ab585a639c 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -169,7 +169,7 @@ config PINCTRL_SDM660
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
- depends on GPIOLIB && OF
+ depends on GPIOLIB && (OF || ACPI)
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index c97f20fca5fd..98a438dba711 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -3,6 +3,7 @@
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*/
+#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@@ -1277,6 +1278,10 @@ static const struct msm_pingroup sdm845_groups[] = {
UFS_RESET(ufs_reset, 0x99f000),
};
+static const int sdm845_acpi_reserved_gpios[] = {
+ 0, 1, 2, 3, 81, 82, 83, 84, -1
+};
+
static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
.pins = sdm845_pins,
.npins = ARRAY_SIZE(sdm845_pins),
@@ -1287,11 +1292,39 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
.ngpios = 150,
};
+static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {
+ .pins = sdm845_pins,
+ .npins = ARRAY_SIZE(sdm845_pins),
+ .groups = sdm845_groups,
+ .ngroups = ARRAY_SIZE(sdm845_groups),
+ .reserved_gpios = sdm845_acpi_reserved_gpios,
+ .ngpios = 150,
+};
+
static int sdm845_pinctrl_probe(struct platform_device *pdev)
{
- return msm_pinctrl_probe(pdev, &sdm845_pinctrl);
+ int ret;
+
+ if (pdev->dev.of_node) {
+ ret = msm_pinctrl_probe(pdev, &sdm845_pinctrl);
+ } else if (has_acpi_companion(&pdev->dev)) {
+ ret = msm_pinctrl_probe(pdev, &sdm845_acpi_pinctrl);
+ } else {
+ dev_err(&pdev->dev, "DT and ACPI disabled\n");
+ return -EINVAL;
+ }
+
+ return ret;
}
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id sdm845_pinctrl_acpi_match[] = {
+ { "QCOM0217"},
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, sdm845_pinctrl_acpi_match);
+#endif
+
static const struct of_device_id sdm845_pinctrl_of_match[] = {
{ .compatible = "qcom,sdm845-pinctrl", },
{ },
@@ -1302,6 +1335,7 @@ static struct platform_driver sdm845_pinctrl_driver = {
.name = "sdm845-pinctrl",
.pm = &msm_pinctrl_dev_pm_ops,
.of_match_table = sdm845_pinctrl_of_match,
+ .acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match),
},
.probe = sdm845_pinctrl_probe,
.remove = msm_pinctrl_remove,
--
2.21.0

35
arm64-rock960-enable-tsadc.patch
View file

@ -1,35 +0,0 @@
From 02260a619efe574d0f6c2a4420b8b76c6802294e Mon Sep 17 00:00:00 2001
From: Ezequiel Garcia <ezequiel@collabora.com>
Date: Fri, 15 Feb 2019 12:25:39 -0300
Subject: arm64: dts: rockchip: Enable tsadc device on rock960
Enable the thermal sensor. This device also provides
temperature shutdown protection. The shutdown value is
set at 110C, as tested by the vendor.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
index e40e66e33a5e..2927db4dda9d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
@@ -527,6 +527,13 @@
status = "okay";
};
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ rockchip,hw-tshut-temp = <110000>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
--
cgit 1.2-0.3.lf.el7

2072
arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch
View file

File diff suppressed because it is too large Load diff

83
arm64-ufs-qcom-Add-support-for-platforms-booting-ACPI.patch Normal file
View file

@ -0,0 +1,83 @@
From 9ceb22fbffbad710db2c91ed32e4e73503f13301 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Tue, 25 Jun 2019 19:12:10 +0100
Subject: [PATCH] scsi: ufs-qcom: Add support for platforms booting ACPI
New Qualcomm AArch64 based laptops are now available which use UFS
as their primary data storage medium. These devices are supplied
with ACPI support out of the box. This patch ensures the Qualcomm
UFS driver will be bound when the "QCOM24A5" H/W device is
advertised as present.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
drivers/scsi/ufs/ufs-qcom.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index b4d1b5c22987..ee4b1da1e223 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -3,6 +3,7 @@
* Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
*/
+#include <linux/acpi.h>
#include <linux/time.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@@ -161,6 +162,9 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
int err = 0;
struct device *dev = host->hba->dev;
+ if (has_acpi_companion(dev))
+ return 0;
+
err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
&host->rx_l0_sync_clk, false);
if (err)
@@ -1127,9 +1131,13 @@ static int ufs_qcom_init(struct ufs_hba *hba)
__func__, err);
goto out_variant_clear;
} else if (IS_ERR(host->generic_phy)) {
- err = PTR_ERR(host->generic_phy);
- dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
- goto out_variant_clear;
+ if (has_acpi_companion(dev)) {
+ host->generic_phy = NULL;
+ } else {
+ err = PTR_ERR(host->generic_phy);
+ dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
+ goto out_variant_clear;
+ }
}
err = ufs_qcom_bus_register(host);
@@ -1599,6 +1607,14 @@ static const struct of_device_id ufs_qcom_of_match[] = {
};
MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id ufs_qcom_acpi_match[] = {
+ { "QCOM24A5" },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
+#endif
+
static const struct dev_pm_ops ufs_qcom_pm_ops = {
.suspend = ufshcd_pltfrm_suspend,
.resume = ufshcd_pltfrm_resume,
@@ -1615,6 +1631,7 @@ static struct platform_driver ufs_qcom_pltform = {
.name = "ufshcd-qcom",
.pm = &ufs_qcom_pm_ops,
.of_match_table = of_match_ptr(ufs_qcom_of_match),
+ .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
},
};
module_platform_driver(ufs_qcom_pltform);
--
2.21.0

185
bcm2835-camera-Restore-return-behavior-of-ctrl_set_bitrate.patch Normal file
View file

@ -0,0 +1,185 @@
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From: Stefan Wahren <wahrenst@gmx.net>
To: Eric Anholt <eric@anholt.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Madhumitha Prabakaran <madhumithabiw@gmail.com>
Subject: [PATCH V2] staging: bcm2835-camera: Restore return behavior of
ctrl_set_bitrate()
Date: Wed, 26 Jun 2019 17:48:11 +0200
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Cc: devel@driverdev.osuosl.org, Stefan Wahren <wahrenst@gmx.net>,
Dave Stevenson <dave.stevenson@raspberrypi.org>,
Dan Carpenter <dan.carpenter@oracle.com>,
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The commit 52c4dfcead49 ("Staging: vc04_services: Cleanup in
ctrl_set_bitrate()") changed the return behavior of ctrl_set_bitrate().
We cannot do this because of a bug in the firmware, which breaks probing
of bcm2835-camera:
bcm2835-v4l2: mmal_init: failed to set all camera controls: -3
Cleanup: Destroy video encoder
Cleanup: Destroy image encoder
Cleanup: Destroy video render
Cleanup: Destroy camera
bcm2835-v4l2: bcm2835_mmal_probe: mmal init failed: -3
bcm2835-camera: probe of bcm2835-camera failed with error -3
So restore the old behavior, add an explaining comment and a debug message
to verify that the bug has been fixed in firmware.
Fixes: 52c4dfcead49 ("Staging: vc04_services: Cleanup in ctrl_set_bitrate()")
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Acked-by: Dan Carpenter <dan.carpenter@oracle.com>
---
.../staging/vc04_services/bcm2835-camera/controls.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
Changes in V2:
- add an explaining comment as suggest by Dan and Dave
- add a debug message to verify the firmware behavior
--
2.7.4
diff --git a/drivers/staging/vc04_services/bcm2835-camera/controls.c b/drivers/staging/vc04_services/bcm2835-camera/controls.c
index d60e378..c251164 100644
--- a/drivers/staging/vc04_services/bcm2835-camera/controls.c
+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c
@@ -604,15 +604,28 @@ static int ctrl_set_bitrate(struct bm2835_mmal_dev *dev,
struct v4l2_ctrl *ctrl,
const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
{
+ int ret;
struct vchiq_mmal_port *encoder_out;
dev->capture.encode_bitrate = ctrl->val;
encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
- return vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
- mmal_ctrl->mmal_id, &ctrl->val,
- sizeof(ctrl->val));
+ ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
+ mmal_ctrl->mmal_id, &ctrl->val,
+ sizeof(ctrl->val));
+
+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
+ "%s: After: mmal_ctrl:%p ctrl id:0x%x ctrl val:%d ret %d(%d)\n",
+ __func__, mmal_ctrl, ctrl->id, ctrl->val, ret,
+ (ret == 0 ? 0 : -EINVAL));
+
+ /*
+ * Older firmware versions (pre July 2019) have a bug in handling
+ * MMAL_PARAMETER_VIDEO_BIT_RATE that result in the call
+ * returning -MMAL_MSG_STATUS_EINVAL. So ignore errors from this call.
+ */
+ return 0;
}
static int ctrl_set_bitrate_mode(struct bm2835_mmal_dev *dev,

399
bcm2835-cpufreq-add-CPU-frequency-control-driver.patch
View file

@ -1,399 +0,0 @@
From fbdb31e061b67941342fc5afa714488f75174632 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Thu, 31 May 2018 19:08:12 +0100
Subject: [PATCH 1/3] bcm2835: cpufreq: add CPU frequency control driver
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 7 ++
arch/arm/boot/dts/bcm2837.dtsi | 33 +++++++
drivers/clk/bcm/Kconfig | 8 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-raspberrypi.c | 138 +++++++++++++++++++++++++++++
5 files changed, 187 insertions(+)
create mode 100644 drivers/clk/bcm/clk-raspberrypi.c
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 29f970f864dc..6d0f43957af4 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -35,6 +35,13 @@
reg = <0x7e00b840 0x3c>;
interrupts = <0 2>;
};
+
+ arm_clk: arm_clk {
+ compatible = "raspberrypi,bcm2835-cpu";
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #clock-cells = <0>;
+ clock-output-names = "arm";
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index beb6c502dadc..9cfc553a3633 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -44,6 +44,9 @@
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
+ clocks = <&arm_clk>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
@@ -52,6 +55,9 @@
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
+ clocks = <&arm_clk>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
@@ -60,6 +66,9 @@
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
+ clocks = <&arm_clk>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
@@ -68,6 +77,30 @@
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
+ clocks = <&arm_clk>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ clock-latency-ns = <355000>;
+ opp-suspend;
+ };
+
+ opp@900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ clock-latency-ns = <355000>;
+ };
+
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ clock-latency-ns = <355000>;
};
};
};
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 4c4bd85f707c..e40bd19da22b 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -63,3 +63,11 @@ config CLK_BCM_SR
default ARCH_BCM_IPROC
help
Enable common clock framework support for the Broadcom Stingray SoC
+
+config CLK_RASPBERRYPI_CPU
+ bool "Raspberry Pi CPU clock driver"
+ depends on ARCH_BCM2835 || (COMPILE_TEST && OF)
+ depends on RASPBERRYPI_FIRMWARE=y
+ help
+ This enables support for the RPi CPU clock which can be adjusted
+ via the RPi firmware.
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 002661d39128..a028b0a90b6e 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-a
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835-aux.o
obj-$(CONFIG_ARCH_BCM_53573) += clk-bcm53573-ilp.o
+obj-$(CONFIG_CLK_RASPBERRYPI_CPU) += clk-raspberrypi.o
obj-$(CONFIG_CLK_BCM_CYGNUS) += clk-cygnus.o
obj-$(CONFIG_CLK_BCM_HR2) += clk-hr2.o
obj-$(CONFIG_CLK_BCM_NSP) += clk-nsp.o
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
new file mode 100644
index 000000000000..046efc822a59
--- /dev/null
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Raspberry Pi CPU clock driver
+ *
+ * Copyright (C) 2018 Stefan Wahren <stefan.wahren@i2se.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <soc/bcm2835/raspberrypi-firmware.h>
+
+#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */
+
+struct rpi_cpu_clkgen {
+ struct clk_hw hw;
+ struct rpi_firmware *fw;
+};
+
+/* tag part of the message */
+struct prop {
+ u32 id; /* the ID of the clock/voltage to get or set */
+ u32 val; /* the value (e.g. rate (in Hz)) to set */
+} __packed;
+
+static int rpi_cpu_clock_property(struct rpi_firmware *fw, u32 tag, u32 *val)
+{
+ int ret;
+ struct prop msg = {
+ .id = VCMSG_ID_ARM_CLOCK,
+ .val = *val,
+ };
+
+ ret = rpi_firmware_property(fw, tag, &msg, sizeof(msg));
+ if (ret)
+ return ret;
+
+ *val = msg.val;
+
+ return 0;
+}
+
+static unsigned long rpi_cpu_get_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct rpi_cpu_clkgen *cpu = container_of(hw, struct rpi_cpu_clkgen, hw);
+ u32 rate = 0;
+
+ rpi_cpu_clock_property(cpu->fw, RPI_FIRMWARE_GET_CLOCK_RATE, &rate);
+
+ return rate;
+}
+
+static long rpi_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return rate;
+}
+
+static int rpi_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct rpi_cpu_clkgen *cpu = container_of(hw, struct rpi_cpu_clkgen, hw);
+ u32 new_rate = rate;
+
+ return rpi_cpu_clock_property(cpu->fw, RPI_FIRMWARE_SET_CLOCK_RATE,
+ &new_rate);
+}
+
+static const struct clk_ops rpi_cpu_ops = {
+ .recalc_rate = rpi_cpu_get_rate,
+ .round_rate = rpi_cpu_round_rate,
+ .set_rate = rpi_cpu_set_rate,
+};
+
+static int rpi_cpu_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *fw_node;
+ struct rpi_cpu_clkgen *cpu;
+ struct clk_init_data *init;
+ int ret;
+
+ cpu = devm_kzalloc(dev, sizeof(*cpu), GFP_KERNEL);
+ if (!cpu)
+ return -ENOMEM;
+
+ init = devm_kzalloc(dev, sizeof(*init), GFP_KERNEL);
+ if (!init)
+ return -ENOMEM;
+
+ fw_node = of_find_compatible_node(NULL, NULL,
+ "raspberrypi,bcm2835-firmware");
+ if (!fw_node) {
+ dev_err(dev, "Missing firmware node\n");
+ return -ENOENT;
+ }
+
+ cpu->fw = rpi_firmware_get(fw_node);
+ of_node_put(fw_node);
+ if (!cpu->fw)
+ return -EPROBE_DEFER;
+
+ init->name = dev->of_node->name;
+ init->ops = &rpi_cpu_ops;
+
+ cpu->hw.init = init;
+ ret = devm_clk_hw_register(dev, &cpu->hw);
+ if (ret)
+ return ret;
+
+ return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
+ &cpu->hw);
+}
+
+static const struct of_device_id rpi_cpu_of_match[] = {
+ { .compatible = "raspberrypi,bcm2835-cpu", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rpi_cpu_of_match);
+
+static struct platform_driver rpi_cpu_driver = {
+ .driver = {
+ .name = "raspberrypi-cpu",
+ .of_match_table = rpi_cpu_of_match,
+ },
+ .probe = rpi_cpu_probe,
+};
+builtin_platform_driver(rpi_cpu_driver);
+
+MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
+MODULE_DESCRIPTION("Raspberry Pi CPU clock driver");
+MODULE_LICENSE("GPL v2");
--
2.20.1
From 0681db63db37cf9015ef9b667c237c3974de04e6 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Mon, 4 Jun 2018 09:14:10 +0100
Subject: [PATCH 2/3] add 1.4 ghz OPP for the 3B+
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
index 42bb09044cc7..3333c080696c 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
@@ -106,3 +106,10 @@
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
+
+&cpu0_opp_table {
+ opp@1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ clock-latency-ns = <355000>;
+ };
+};
--
2.20.1
From 65f821f03ac635f28c8c79c5e436b398194521f2 Mon Sep 17 00:00:00 2001
From: Stefan Wahren <stefan.wahren@i2se.com>
Date: Wed, 26 Sep 2018 21:13:22 +0200
Subject: [PATCH 3/3] ARM: bcm2837: Use CPU0 as cooling device
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/boot/dts/bcm2837.dtsi | 25 +++++++++++++++++++++++++
arch/arm/boot/dts/bcm283x.dtsi | 2 +-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 9cfc553a3633..1590d94b618e 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -1,4 +1,5 @@
#include "bcm283x.dtsi"
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "brcm,bcm2837";
@@ -47,6 +48,7 @@
clocks = <&arm_clk>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -58,6 +60,7 @@
clocks = <&arm_clk>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
@@ -69,6 +72,7 @@
clocks = <&arm_clk>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
@@ -80,6 +84,7 @@
clocks = <&arm_clk>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
};
@@ -117,6 +122,26 @@
&cpu_thermal {
coefficients = <(-538) 412000>;
+
+ trips {
+ cpu_alert0: cpu-alert0 {
+ temperature = <70000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_crit>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
/* enable thermal sensor with the correct compatible property set */
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 31b29646b14c..2def0684d198 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -38,7 +38,7 @@
thermal-sensors = <&thermal>;
trips {
- cpu-crit {
+ cpu_crit: cpu-crit {
temperature = <80000>;
hysteresis = <0>;
type = "critical";
--
2.20.1

1133
bcm2835-vchiq-use-interruptible-waits.patch Normal file
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File diff suppressed because it is too large Load diff

1
configs/fedora/debug/CONFIG_DEBUG_MISC Normal file
View file

@ -0,0 +1 @@
CONFIG_DEBUG_MISC=y

1
configs/fedora/debug/CONFIG_DEBUG_PI_LIST
View file

@ -1 +0,0 @@
CONFIG_DEBUG_PI_LIST=y

1
configs/fedora/debug/CONFIG_LOCK_EVENT_COUNTS Normal file
View file

@ -0,0 +1 @@
CONFIG_LOCK_EVENT_COUNTS=y

1
configs/fedora/generic/CONFIG_ACPI_HMAT Normal file
View file

@ -0,0 +1 @@
CONFIG_ACPI_HMAT=y

0
configs/fedora/generic/x86/x86_64/CONFIG_AQTION → configs/fedora/generic/CONFIG_AQTION
View file

1
configs/fedora/generic/CONFIG_AX88796B_PHY Normal file
View file

@ -0,0 +1 @@
CONFIG_AX88796B_PHY=m

1
configs/fedora/generic/CONFIG_BACKLIGHT_LCD_SUPPORT
View file

@ -1 +0,0 @@
CONFIG_BACKLIGHT_LCD_SUPPORT=y

1
configs/fedora/generic/CONFIG_BATMAN_ADV_SYSFS Normal file
View file

@ -0,0 +1 @@
CONFIG_BATMAN_ADV_SYSFS=y

1
configs/fedora/generic/CONFIG_BT_MTKSDIO Normal file
View file

@ -0,0 +1 @@
CONFIG_BT_MTKSDIO=m

1
configs/fedora/generic/CONFIG_CHARGER_LT3651 Normal file
View file

@ -0,0 +1 @@
CONFIG_CHARGER_LT3651=m

1
configs/fedora/generic/CONFIG_CHARGER_LTC3651
View file

@ -1 +0,0 @@
# CONFIG_CHARGER_LTC3651 is not set

1
configs/fedora/generic/CONFIG_CHARGER_MAX77650 Normal file
View file

@ -0,0 +1 @@
CONFIG_CHARGER_MAX77650=m

1
configs/fedora/generic/CONFIG_CHARGER_UCS1002 Normal file
View file

@ -0,0 +1 @@
CONFIG_CHARGER_UCS1002=m

1
configs/fedora/generic/CONFIG_CHASH_SELFTEST
View file

@ -1 +0,0 @@
# CONFIG_CHASH_SELFTEST is not set

1
configs/fedora/generic/CONFIG_CHASH_STATS
View file

@ -1 +0,0 @@
# CONFIG_CHASH_STATS is not set

1
configs/fedora/generic/CONFIG_CLK_SIFIVE Normal file
View file

@ -0,0 +1 @@
# CONFIG_CLK_SIFIVE is not set

1
configs/fedora/generic/CONFIG_CLK_SUNXI Normal file
View file

@ -0,0 +1 @@
# CONFIG_CLK_SUNXI is not set

1
configs/fedora/generic/CONFIG_CLK_SUNXI_CLOCKS Normal file
View file

@ -0,0 +1 @@
# CONFIG_CLK_SUNXI_CLOCKS is not set

1
configs/fedora/generic/CONFIG_CLK_SUNXI_PRCM_SUN6I Normal file
View file

@ -0,0 +1 @@
# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set

1
configs/fedora/generic/CONFIG_CLK_SUNXI_PRCM_SUN8I Normal file
View file

@ -0,0 +1 @@
# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set

1
configs/fedora/generic/CONFIG_CLK_SUNXI_PRCM_SUN9I Normal file
View file

@ -0,0 +1 @@
# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set

2
configs/fedora/generic/CONFIG_CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES
View file

@ -1 +1 @@
# CONFIG_CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
CONFIG_CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y

1
configs/fedora/generic/CONFIG_COUNTER Normal file
View file

@ -0,0 +1 @@
# CONFIG_COUNTER is not set

1
configs/fedora/generic/CONFIG_CROS_EC_RPMSG Normal file
View file

@ -0,0 +1 @@
CONFIG_CROS_EC_RPMSG=m

1
configs/fedora/generic/CONFIG_CROS_USBPD_LOGGER Normal file
View file

@ -0,0 +1 @@
CONFIG_CROS_USBPD_LOGGER=m

1
configs/fedora/generic/CONFIG_CRYPTO_ECRDSA Normal file
View file

@ -0,0 +1 @@
CONFIG_CRYPTO_ECRDSA=m

1
configs/fedora/generic/CONFIG_DEBUG_INFO_BTF Normal file
View file

@ -0,0 +1 @@
# CONFIG_DEBUG_INFO_BTF is not set

1
configs/fedora/generic/CONFIG_DEBUG_MISC Normal file
View file

@ -0,0 +1 @@
# CONFIG_DEBUG_MISC is not set

1
configs/fedora/generic/CONFIG_DEBUG_PI_LIST
View file

@ -1 +0,0 @@
# CONFIG_DEBUG_PI_LIST is not set

1
configs/fedora/generic/CONFIG_DEBUG_PLIST Normal file
View file

@ -0,0 +1 @@
# CONFIG_DEBUG_PLIST is not set

1
configs/fedora/generic/CONFIG_DM_DUST Normal file
View file

@ -0,0 +1 @@
CONFIG_DM_DUST=m

2
configs/fedora/generic/CONFIG_DM_WRITECACHE
View file

@ -1 +1 @@
# CONFIG_DM_WRITECACHE is not set
CONFIG_DM_WRITECACHE=m

1
configs/fedora/generic/CONFIG_DRM_MGA Normal file
View file

@ -0,0 +1 @@
# CONFIG_DRM_MGA is not set

1
configs/fedora/generic/CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D Normal file
View file

@ -0,0 +1 @@
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m

1
configs/fedora/generic/CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 Normal file
View file

@ -0,0 +1 @@
CONFIG_DRM_PANEL_ROCKTECH_JH057N00900=m

1
configs/fedora/generic/CONFIG_DRM_PANEL_RONBO_RB070D30 Normal file
View file

@ -0,0 +1 @@
CONFIG_DRM_PANEL_RONBO_RB070D30=m

1
configs/fedora/generic/CONFIG_DRM_R128 Normal file
View file

@ -0,0 +1 @@
# CONFIG_DRM_R128 is not set

1
configs/fedora/generic/CONFIG_DRM_SAVAGE Normal file
View file

@ -0,0 +1 @@
# CONFIG_DRM_SAVAGE is not set

1
configs/fedora/generic/CONFIG_DRM_TDFX Normal file
View file

@ -0,0 +1 @@
# CONFIG_DRM_TDFX=n is not set

1
configs/fedora/generic/CONFIG_DRM_VIA Normal file
View file

@ -0,0 +1 @@
# CONFIG_DRM_VIA is not set

1
configs/fedora/generic/CONFIG_FIELDBUS_DEV Normal file
View file

@ -0,0 +1 @@
# CONFIG_FIELDBUS_DEV is not set

1
configs/fedora/generic/CONFIG_FXAS21002C Normal file
View file

@ -0,0 +1 @@
CONFIG_FXAS21002C=m

1
configs/fedora/generic/CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF Normal file
View file

@ -0,0 +1 @@
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set

1
configs/fedora/generic/CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL Normal file
View file

@ -0,0 +1 @@
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set

1
configs/fedora/generic/CONFIG_GCC_PLUGIN_STRUCTLEAK_USER Normal file
View file

@ -0,0 +1 @@
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set

1
configs/fedora/generic/CONFIG_GCC_PLUGIN_STRUCTLEAK_VERBOSE Normal file
View file

@ -0,0 +1 @@
# CONFIG_GCC_PLUGIN_STRUCTLEAK_VERBOSE is not set

1
configs/fedora/generic/CONFIG_GPIO_MAX77650 Normal file
View file

@ -0,0 +1 @@
CONFIG_GPIO_MAX77650=m

1
configs/fedora/generic/CONFIG_HID_MACALLY Normal file
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@ -0,0 +1 @@
CONFIG_HID_MACALLY=m

1
configs/fedora/generic/CONFIG_HID_U2FZERO Normal file
View file

@ -0,0 +1 @@
CONFIG_HID_U2FZERO=m

1
configs/fedora/generic/CONFIG_I2C_AMD_MP2 Normal file
View file

@ -0,0 +1 @@
CONFIG_I2C_AMD_MP2=m

1
configs/fedora/generic/CONFIG_IKHEADERS Normal file
View file

@ -0,0 +1 @@
CONFIG_IKHEADERS=m

1
configs/fedora/generic/CONFIG_INET6_XFRM_MODE_BEET
View file

@ -1 +0,0 @@
CONFIG_INET6_XFRM_MODE_BEET=m

1
configs/fedora/generic/CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION
View file

@ -1 +0,0 @@
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m

1
configs/fedora/generic/CONFIG_INET6_XFRM_MODE_TRANSPORT
View file

@ -1 +0,0 @@
CONFIG_INET6_XFRM_MODE_TRANSPORT=m

1
configs/fedora/generic/CONFIG_INET6_XFRM_MODE_TUNNEL
View file

@ -1 +0,0 @@
CONFIG_INET6_XFRM_MODE_TUNNEL=m

1
configs/fedora/generic/CONFIG_INET_XFRM_MODE_BEET
View file

@ -1 +0,0 @@
CONFIG_INET_XFRM_MODE_BEET=m

1
configs/fedora/generic/CONFIG_INET_XFRM_MODE_TRANSPORT
View file

@ -1 +0,0 @@
CONFIG_INET_XFRM_MODE_TRANSPORT=m

1
configs/fedora/generic/CONFIG_INET_XFRM_MODE_TUNNEL
View file

@ -1 +0,0 @@
CONFIG_INET_XFRM_MODE_TUNNEL=m

1
configs/fedora/generic/CONFIG_INFINIBAND_EFA Normal file
View file

@ -0,0 +1 @@
CONFIG_INFINIBAND_EFA=m

1
configs/fedora/generic/CONFIG_INIT_STACK_NONE Normal file
View file

@ -0,0 +1 @@
CONFIG_INIT_STACK_NONE=y

1
configs/fedora/generic/CONFIG_INPUT_GPIO_VIBRA Normal file
View file

@ -0,0 +1 @@
CONFIG_INPUT_GPIO_VIBRA=m

1
configs/fedora/generic/CONFIG_INPUT_MAX77650_ONKEY Normal file
View file

@ -0,0 +1 @@
CONFIG_INPUT_MAX77650_ONKEY=m

1
configs/fedora/generic/CONFIG_IXP4XX_NPE Normal file
View file

@ -0,0 +1 @@
# CONFIG_IXP4XX_NPE is not set

1
configs/fedora/generic/CONFIG_IXP4XX_QMGR Normal file
View file

@ -0,0 +1 @@
# CONFIG_IXP4XX_QMGR is not set

1
configs/fedora/generic/CONFIG_KEYBOARD_QT1050 Normal file
View file

@ -0,0 +1 @@
CONFIG_KEYBOARD_QT1050=m

1
configs/fedora/generic/CONFIG_KPC2000 Normal file
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@ -0,0 +1 @@
# CONFIG_KPC2000 is not set

1
configs/fedora/generic/CONFIG_LEDS_LM3532 Normal file
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@ -0,0 +1 @@
CONFIG_LEDS_LM3532=m

1
configs/fedora/generic/CONFIG_LEDS_MAX77650 Normal file
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@ -0,0 +1 @@
CONFIG_LEDS_MAX77650=m

1
configs/fedora/generic/CONFIG_LOCK_EVENT_COUNTS Normal file
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@ -0,0 +1 @@
# CONFIG_LOCK_EVENT_COUNTS is not set

1
configs/fedora/generic/CONFIG_MAX31856 Normal file
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@ -0,0 +1 @@
CONFIG_MAX31856=m

1
configs/fedora/generic/CONFIG_MB1232 Normal file
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@ -0,0 +1 @@
CONFIG_MB1232=m

2
configs/fedora/generic/CONFIG_MEDIA_CONTROLLER_DVB
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@ -1 +1 @@
# CONFIG_MEDIA_CONTROLLER_DVB is not set
CONFIG_MEDIA_CONTROLLER_DVB=y

1
configs/fedora/generic/CONFIG_MFD_MAX77650 Normal file
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@ -0,0 +1 @@
CONFIG_MFD_MAX77650=m

1
configs/fedora/generic/CONFIG_MFD_STMFX Normal file
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@ -0,0 +1 @@
# CONFIG_MFD_STMFX is not set

1
configs/fedora/generic/CONFIG_MT7615E Normal file
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@ -0,0 +1 @@
CONFIG_MT7615E=m

1
configs/fedora/generic/CONFIG_MTD_NAND
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@ -1 +0,0 @@
# CONFIG_MTD_NAND is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_BRCMNAND Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_BRCMNAND is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_CAFE Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_CAFE is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_CS553X Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_CS553X is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_ECC_BCH
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@ -1 +0,0 @@
# CONFIG_MTD_NAND_ECC_BCH is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_ECC_SW_BCH Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_ECC_SW_BCH is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_FSL_IFC Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_FSL_IFC is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_GPIO Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_GPIO is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_HISI504 Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_HISI504 is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_MXC Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_MXC is not set

1
configs/fedora/generic/CONFIG_MTD_NAND_NANDSIM Normal file
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@ -0,0 +1 @@
# CONFIG_MTD_NAND_NANDSIM is not set

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