Linux v4.19-11706-g11743c56785c
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parent
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commit
968d59bf94
33 changed files with 135 additions and 8150 deletions
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From patchwork Wed Sep 26 06:24:57 2018
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X-Patchwork-Id: 10615319
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2018 07:26:26 +0100
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From: Akash Gajjar <Akash_Gajjar@mentor.com>
|
||||
To: <heiko@sntech.de>
|
||||
Subject: [PATCH v3] arm64: dts: rockchip: add initial dts support for
|
||||
Rockpro64
|
||||
Date: Wed, 26 Sep 2018 11:54:57 +0530
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Cc: Mark Rutland <mark.rutland@arm.com>,
|
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Shohei Maruyama <cheat.sc.linux@outlook.com>, Arnd Bergmann <arnd@arndb.de>,
|
||||
devicetree@vger.kernel.org, Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
|
||||
Shawn Lin <shawn.lin@rock-chips.com>, linux-kernel@vger.kernel.org,
|
||||
Masahiro Yamada <yamada.masahiro@socionext.com>,
|
||||
linux-rockchip@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
|
||||
Klaus Goger <klaus.goger@theobroma-systems.com>,
|
||||
Philippe Ombredanne <pombredanne@nexb.com>,
|
||||
Enric Balletbo i Serra <enric.balletbo@collabora.com>,
|
||||
Pragnesh_patel@mentor.com, Deepak_das@mentor.com,
|
||||
Levin Du <djw@t-chip.com.cn>,
|
||||
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|
||||
Rockpro64 is a rockchip RK3399 based board from pine64.org.
|
||||
This patch adds basic device node support for Rockpro64 board and make it able
|
||||
to bring up.
|
||||
|
||||
Peripheral Works
|
||||
- Sdcard
|
||||
- USB 2.0, 3.0
|
||||
- Leds
|
||||
- Ethernet
|
||||
- Debug console
|
||||
|
||||
Not working:
|
||||
- USB Type-C
|
||||
|
||||
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
|
||||
Acked-by: Deepak Das <Deepak_Das@mentor.com>
|
||||
---
|
||||
changes for v2
|
||||
- Added support for usb 2.0, 3.0
|
||||
- Added fusb302 node and its regulator support
|
||||
- Cleanup pinctrl node
|
||||
- Remove backlight, pcie, sound codec node inherited from firefly-rk3399 dts
|
||||
changes for v3
|
||||
- Added copyright properly
|
||||
- Typo correction in commit message
|
||||
|
||||
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 692 +++++++++++++++++++++
|
||||
3 files changed, 697 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
|
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|
||||
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
|
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index acfd3c7..ac95183 100644
|
||||
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
|
||||
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
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||||
@@ -160,6 +160,10 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "pine64,rock64", "rockchip,rk3328";
|
||||
|
||||
+- Pine64 RockPro64 board:
|
||||
+ Required root node properties:
|
||||
+ - compatible = "pine64,rockpro64", "rockchip,rk3399";
|
||||
+
|
||||
- Rockchip PX3 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
index b0092d9..03d523a 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -15,5 +15,6 @@
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
|
||||
new file mode 100644
|
||||
index 0000000..1d35f54
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
|
||||
@@ -0,0 +1,692 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/input/linux-event-codes.h>
|
||||
+#include <dt-bindings/pwm/pwm.h>
|
||||
+#include "rk3399.dtsi"
|
||||
+#include "rk3399-opp.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Pine64 RockPro64";
|
||||
+ compatible = "pine64,rockpro64", "rockchip,rk3399";
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ clkin_gmac: external-gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clkin_gmac";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ dc_12v: dc-12v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "dc_12v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ autorepeat;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwrbtn>;
|
||||
+
|
||||
+ power {
|
||||
+ debounce-interval = <100>;
|
||||
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
+ label = "GPIO Key Power";
|
||||
+ linux,code = <KEY_POWER>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
|
||||
+
|
||||
+ work-led {
|
||||
+ label = "work";
|
||||
+ default-state = "on";
|
||||
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ diy-led {
|
||||
+ label = "diy";
|
||||
+ default-state = "off";
|
||||
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk808 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+
|
||||
+ /*
|
||||
+ * On the module itself this is one of these (depending
|
||||
+ * on the actual card populated):
|
||||
+ * - SDIO_RESET_L_WL_REG_ON
|
||||
+ * - PDN (power down when low)
|
||||
+ */
|
||||
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ /* switched by pmic_sleep */
|
||||
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc1v8_s3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_pwr_en>;
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
|
||||
+ vcc5v0_host: vcc5v0-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_host_en>;
|
||||
+ regulator-name = "vcc5v0_host";
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_typec: vcc5v0-typec-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_typec_en>;
|
||||
+ regulator-name = "vcc5v0_typec";
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_log: vdd-log {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm2 0 25000 1>;
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1400000>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
+ assigned-clock-parents = <&clkin_gmac>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-supply = <&vcc_lan>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rgmii_pins>;
|
||||
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ snps,reset-delays-us = <0 10000 50000>;
|
||||
+ tx_delay = <0x28>;
|
||||
+ rx_delay = <0x11>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ clock-frequency = <400000>;
|
||||
+ i2c-scl-rising-time-ns = <168>;
|
||||
+ i2c-scl-falling-time-ns = <4>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk808: pmic@1b {
|
||||
+ compatible = "rockchip,rk808";
|
||||
+ reg = <0x1b>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk808-clkout2";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc_sys>;
|
||||
+ vcc2-supply = <&vcc_sys>;
|
||||
+ vcc3-supply = <&vcc_sys>;
|
||||
+ vcc4-supply = <&vcc_sys>;
|
||||
+ vcc6-supply = <&vcc_sys>;
|
||||
+ vcc7-supply = <&vcc_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc_sys>;
|
||||
+ vcc10-supply = <&vcc_sys>;
|
||||
+ vcc11-supply = <&vcc_sys>;
|
||||
+ vcc12-supply = <&vcc3v3_sys>;
|
||||
+ vddio-supply = <&vcc1v8_pmu>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_center: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_center";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_l: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_cpu_l";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_dvp: LDO_REG1 {
|
||||
+ regulator-name = "vcc1v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc2v8_dvp: LDO_REG2 {
|
||||
+ regulator-name = "vcc2v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <2800000>;
|
||||
+ regulator-max-microvolt = <2800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vcc1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sdio: LDO_REG4 {
|
||||
+ regulator-name = "vcc_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca3v0_codec: LDO_REG5 {
|
||||
+ regulator-name = "vcca3v0_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v5: LDO_REG6 {
|
||||
+ regulator-name = "vcc_1v5";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1500000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_codec: LDO_REG7 {
|
||||
+ regulator-name = "vcca1v8_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v0: LDO_REG8 {
|
||||
+ regulator-name = "vcc_3v0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc3v3_s3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s0: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_s0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_b: regulator@40 {
|
||||
+ compatible = "silergy,syr827";
|
||||
+ reg = <0x40>;
|
||||
+ fcs,suspend-voltage-selector = <0>;
|
||||
+ regulator-name = "vdd_cpu_b";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: regulator@41 {
|
||||
+ compatible = "silergy,syr828";
|
||||
+ reg = <0x41>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ i2c-scl-rising-time-ns = <300>;
|
||||
+ i2c-scl-falling-time-ns = <15>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c3 {
|
||||
+ i2c-scl-rising-time-ns = <450>;
|
||||
+ i2c-scl-falling-time-ns = <15>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ i2c-scl-rising-time-ns = <600>;
|
||||
+ i2c-scl-falling-time-ns = <20>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ fusb0: typec-portc@22 {
|
||||
+ compatible = "fcs,fusb302";
|
||||
+ reg = <0x22>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&fusb0_int>;
|
||||
+ vbus-supply = <&vcc5v0_typec>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0 {
|
||||
+ rockchip,playback-channels = <8>;
|
||||
+ rockchip,capture-channels = <8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s1 {
|
||||
+ rockchip,playback-channels = <2>;
|
||||
+ rockchip,capture-channels = <2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bt656-supply = <&vcc1v8_dvp>;
|
||||
+ audio-supply = <&vcca1v8_codec>;
|
||||
+ sdmmc-supply = <&vcc_sdio>;
|
||||
+ gpio1830-supply = <&vcc_3v0>;
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmu1830-supply = <&vcc_3v0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ buttons {
|
||||
+ pwrbtn: pwrbtn {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fusb302x {
|
||||
+ fusb0_int: fusb0-int {
|
||||
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ work_led_gpio: work_led-gpio {
|
||||
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ diy_led_gpio: diy_led-gpio {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ lcd-panel {
|
||||
+ lcd_panel_reset: lcd-panel-reset {
|
||||
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie_pwr_en: pcie-pwr-en {
|
||||
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ vsel1_gpio: vsel1-gpio {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ vsel2_gpio: vsel2-gpio {
|
||||
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb-typec {
|
||||
+ vcc5v0_typec_en: vcc5v0_typec_en {
|
||||
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2 {
|
||||
+ vcc5v0_host_en: vcc5v0-host-en {
|
||||
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca1v8_s3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
|
||||
+ disable-wp;
|
||||
+ max-frequency = <150000000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ mmc-hs400-1_8v;
|
||||
+ mmc-hs400-enhanced-strobe;
|
||||
+ non-removable;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ /* tshut mode 0:CRU 1:GPIO */
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ /* tshut polarity 0:LOW 1:HIGH */
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ u2phy0_otg: otg-port {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ u2phy0_host: host-port {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ u2phy1_otg: otg-port {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ u2phy1_host: host-port {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "otg";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_1 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vopb {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopb_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
1
configs/fedora/generic/CONFIG_ADXL372_I2C
Normal file
1
configs/fedora/generic/CONFIG_ADXL372_I2C
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_ADXL372_I2C=m
|
||||
1
configs/fedora/generic/CONFIG_ADXL372_SPI
Normal file
1
configs/fedora/generic/CONFIG_ADXL372_SPI
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_ADXL372_SPI=m
|
||||
1
configs/fedora/generic/CONFIG_LTC1660
Normal file
1
configs/fedora/generic/CONFIG_LTC1660
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_LTC1660=m
|
||||
1
configs/fedora/generic/CONFIG_MCP3911
Normal file
1
configs/fedora/generic/CONFIG_MCP3911
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_MCP3911=m
|
||||
1
configs/fedora/generic/CONFIG_VL53L0X_I2C
Normal file
1
configs/fedora/generic/CONFIG_VL53L0X_I2C
Normal file
|
|
@ -0,0 +1 @@
|
|||
# CONFIG_VL53L0X_I2C is not set
|
||||
1
configs/fedora/generic/arm/CONFIG_MESON_CANVAS
Normal file
1
configs/fedora/generic/arm/CONFIG_MESON_CANVAS
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_MESON_CANVAS=m
|
||||
1
configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_ADSP
Normal file
1
configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_ADSP
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_QCOM_Q6V5_ADSP=m
|
||||
1
configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_MSS
Normal file
1
configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_MSS
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_QCOM_Q6V5_MSS=m
|
||||
1
configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_PAS
Normal file
1
configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_PAS
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_QCOM_Q6V5_PAS=m
|
||||
1
configs/fedora/generic/arm/CONFIG_QCOM_SPMI_ADC5
Normal file
1
configs/fedora/generic/arm/CONFIG_QCOM_SPMI_ADC5
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_QCOM_SPMI_ADC5=m
|
||||
1
configs/fedora/generic/arm/CONFIG_RESET_QCOM_PDC
Normal file
1
configs/fedora/generic/arm/CONFIG_RESET_QCOM_PDC
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_RESET_QCOM_PDC=m
|
||||
1
configs/fedora/generic/arm/CONFIG_VIDEO_IMX_PXP
Normal file
1
configs/fedora/generic/arm/CONFIG_VIDEO_IMX_PXP
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_VIDEO_IMX_PXP=m
|
||||
1
configs/fedora/generic/arm/armv7/CONFIG_IMX_SCU
Normal file
1
configs/fedora/generic/arm/armv7/CONFIG_IMX_SCU
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_IMX_SCU=y
|
||||
2
gitrev
2
gitrev
|
|
@ -1 +1 @@
|
|||
673c790e72822ee433931ea701e4fceef75a0eac
|
||||
11743c56785c751c087eecdb98713eef796609e0
|
||||
|
|
|
|||
|
|
@ -147,6 +147,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -3118,6 +3120,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3192,6 +3195,7 @@ CONFIG_MAXSMP=y
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -3264,6 +3268,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
|
|||
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
|
||||
# CONFIG_MEMTEST is not set
|
||||
# CONFIG_MEN_A21_WDT is not set
|
||||
CONFIG_MESON_CANVAS=m
|
||||
CONFIG_MESON_EFUSE=m
|
||||
CONFIG_MESON_GXBB_WATCHDOG=m
|
||||
CONFIG_MESON_GXL_PHY=m
|
||||
|
|
@ -4689,6 +4694,9 @@ CONFIG_QCOM_L2_PMU=y
|
|||
CONFIG_QCOM_L3_PMU=y
|
||||
# CONFIG_QCOM_LLCC is not set
|
||||
CONFIG_QCOM_PDC=y
|
||||
CONFIG_QCOM_Q6V5_ADSP=m
|
||||
CONFIG_QCOM_Q6V5_MSS=m
|
||||
CONFIG_QCOM_Q6V5_PAS=m
|
||||
CONFIG_QCOM_Q6V5_PIL=m
|
||||
# CONFIG_QCOM_Q6V5_WCSS is not set
|
||||
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
|
||||
|
|
@ -4700,6 +4708,7 @@ CONFIG_QCOM_SMD_RPM=m
|
|||
CONFIG_QCOM_SMEM=m
|
||||
CONFIG_QCOM_SMP2P=m
|
||||
CONFIG_QCOM_SMSM=m
|
||||
CONFIG_QCOM_SPMI_ADC5=m
|
||||
CONFIG_QCOM_SPMI_IADC=m
|
||||
CONFIG_QCOM_SPMI_TEMP_ALARM=m
|
||||
CONFIG_QCOM_SPMI_VADC=m
|
||||
|
|
@ -4885,6 +4894,7 @@ CONFIG_RESET_HISI=y
|
|||
# CONFIG_RESET_HSDK_V1 is not set
|
||||
# CONFIG_RESET_MESON_AUDIO_ARB is not set
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
CONFIG_RESET_QCOM_PDC=m
|
||||
CONFIG_RESET_SIMPLE=y
|
||||
# CONFIG_RESET_TI_SCI is not set
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
|
@ -6952,6 +6962,7 @@ CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
|
|||
CONFIG_VIDEO_HDPVR=m
|
||||
CONFIG_VIDEO_HEXIUM_GEMINI=m
|
||||
CONFIG_VIDEO_HEXIUM_ORION=m
|
||||
CONFIG_VIDEO_IMX_PXP=m
|
||||
# CONFIG_VIDEO_IVTV_ALSA is not set
|
||||
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
|
||||
CONFIG_VIDEO_IVTV=m
|
||||
|
|
@ -7023,6 +7034,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -147,6 +147,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -3098,6 +3100,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3171,6 +3174,7 @@ CONFIG_MAX_RAW_DEVS=8192
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -3243,6 +3247,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
|
|||
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
|
||||
# CONFIG_MEMTEST is not set
|
||||
# CONFIG_MEN_A21_WDT is not set
|
||||
CONFIG_MESON_CANVAS=m
|
||||
CONFIG_MESON_EFUSE=m
|
||||
CONFIG_MESON_GXBB_WATCHDOG=m
|
||||
CONFIG_MESON_GXL_PHY=m
|
||||
|
|
@ -4666,6 +4671,9 @@ CONFIG_QCOM_L2_PMU=y
|
|||
CONFIG_QCOM_L3_PMU=y
|
||||
# CONFIG_QCOM_LLCC is not set
|
||||
CONFIG_QCOM_PDC=y
|
||||
CONFIG_QCOM_Q6V5_ADSP=m
|
||||
CONFIG_QCOM_Q6V5_MSS=m
|
||||
CONFIG_QCOM_Q6V5_PAS=m
|
||||
CONFIG_QCOM_Q6V5_PIL=m
|
||||
# CONFIG_QCOM_Q6V5_WCSS is not set
|
||||
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
|
||||
|
|
@ -4677,6 +4685,7 @@ CONFIG_QCOM_SMD_RPM=m
|
|||
CONFIG_QCOM_SMEM=m
|
||||
CONFIG_QCOM_SMP2P=m
|
||||
CONFIG_QCOM_SMSM=m
|
||||
CONFIG_QCOM_SPMI_ADC5=m
|
||||
CONFIG_QCOM_SPMI_IADC=m
|
||||
CONFIG_QCOM_SPMI_TEMP_ALARM=m
|
||||
CONFIG_QCOM_SPMI_VADC=m
|
||||
|
|
@ -4862,6 +4871,7 @@ CONFIG_RESET_HISI=y
|
|||
# CONFIG_RESET_HSDK_V1 is not set
|
||||
# CONFIG_RESET_MESON_AUDIO_ARB is not set
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
CONFIG_RESET_QCOM_PDC=m
|
||||
CONFIG_RESET_SIMPLE=y
|
||||
# CONFIG_RESET_TI_SCI is not set
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
|
@ -6928,6 +6938,7 @@ CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
|
|||
CONFIG_VIDEO_HDPVR=m
|
||||
CONFIG_VIDEO_HEXIUM_GEMINI=m
|
||||
CONFIG_VIDEO_HEXIUM_ORION=m
|
||||
CONFIG_VIDEO_IMX_PXP=m
|
||||
# CONFIG_VIDEO_IVTV_ALSA is not set
|
||||
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
|
||||
CONFIG_VIDEO_IVTV=m
|
||||
|
|
@ -6999,6 +7010,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_AFE4403 is not set
|
||||
|
|
@ -2541,6 +2543,7 @@ CONFIG_IMX_GPCV2=y
|
|||
CONFIG_IMX_IPUV3_CORE=m
|
||||
CONFIG_IMX_MBOX=m
|
||||
CONFIG_IMX_REMOTEPROC=m
|
||||
CONFIG_IMX_SCU=y
|
||||
CONFIG_IMX_SDMA=m
|
||||
CONFIG_IMX_THERMAL=m
|
||||
CONFIG_IMX_WEIM=y
|
||||
|
|
@ -3263,6 +3266,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=32768
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3356,6 +3360,7 @@ CONFIG_MAXSMP=y
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -3428,6 +3433,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
|
|||
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
|
||||
# CONFIG_MEMTEST is not set
|
||||
# CONFIG_MEN_A21_WDT is not set
|
||||
CONFIG_MESON_CANVAS=m
|
||||
CONFIG_MESON_EFUSE=m
|
||||
# CONFIG_MESON_GXBB_WATCHDOG is not set
|
||||
# CONFIG_MESON_GXL_PHY is not set
|
||||
|
|
@ -4959,6 +4965,9 @@ CONFIG_QCOM_IOMMU=y
|
|||
CONFIG_QCOM_PDC=y
|
||||
CONFIG_QCOM_PM8XXX_XOADC=m
|
||||
CONFIG_QCOM_PM=y
|
||||
CONFIG_QCOM_Q6V5_ADSP=m
|
||||
CONFIG_QCOM_Q6V5_MSS=m
|
||||
CONFIG_QCOM_Q6V5_PAS=m
|
||||
CONFIG_QCOM_Q6V5_PIL=m
|
||||
# CONFIG_QCOM_Q6V5_WCSS is not set
|
||||
CONFIG_QCOM_QFPROM=m
|
||||
|
|
@ -4969,6 +4978,7 @@ CONFIG_QCOM_SMD_RPM=m
|
|||
CONFIG_QCOM_SMEM=m
|
||||
CONFIG_QCOM_SMP2P=m
|
||||
CONFIG_QCOM_SMSM=m
|
||||
CONFIG_QCOM_SPMI_ADC5=m
|
||||
CONFIG_QCOM_SPMI_IADC=m
|
||||
CONFIG_QCOM_SPMI_TEMP_ALARM=m
|
||||
CONFIG_QCOM_SPMI_VADC=m
|
||||
|
|
@ -5174,6 +5184,7 @@ CONFIG_RESET_GPIO=y
|
|||
# CONFIG_RESET_HSDK_V1 is not set
|
||||
# CONFIG_RESET_MESON_AUDIO_ARB is not set
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
CONFIG_RESET_QCOM_PDC=m
|
||||
CONFIG_RESET_SIMPLE=y
|
||||
# CONFIG_RESET_TI_SCI is not set
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
|
@ -7426,6 +7437,7 @@ CONFIG_VIDEO_HDPVR=m
|
|||
CONFIG_VIDEO_HEXIUM_GEMINI=m
|
||||
CONFIG_VIDEO_HEXIUM_ORION=m
|
||||
# CONFIG_VIDEO_IMX_MEDIA is not set
|
||||
CONFIG_VIDEO_IMX_PXP=m
|
||||
CONFIG_VIDEO_IMX_VDOA=m
|
||||
# CONFIG_VIDEO_IVTV_ALSA is not set
|
||||
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
|
||||
|
|
@ -7519,6 +7531,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_AFE4403 is not set
|
||||
|
|
@ -2420,6 +2422,7 @@ CONFIG_IMA=y
|
|||
# CONFIG_IMG_ASCII_LCD is not set
|
||||
# CONFIG_IMX_IPUV3_CORE is not set
|
||||
CONFIG_IMX_MBOX=m
|
||||
CONFIG_IMX_SCU=y
|
||||
# CONFIG_INA2XX_ADC is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
|
|
@ -3123,6 +3126,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=32768
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3210,6 +3214,7 @@ CONFIG_MAXSMP=y
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -3280,6 +3285,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
|
|||
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
|
||||
# CONFIG_MEMTEST is not set
|
||||
# CONFIG_MEN_A21_WDT is not set
|
||||
CONFIG_MESON_CANVAS=m
|
||||
CONFIG_MESON_EFUSE=m
|
||||
# CONFIG_MESON_GXBB_WATCHDOG is not set
|
||||
# CONFIG_MESON_GXL_PHY is not set
|
||||
|
|
@ -4698,10 +4704,14 @@ CONFIG_QCOM_CLK_APCS_MSM8916=m
|
|||
# CONFIG_QCOM_LLCC is not set
|
||||
CONFIG_QCOM_PDC=y
|
||||
CONFIG_QCOM_PM8XXX_XOADC=m
|
||||
CONFIG_QCOM_Q6V5_ADSP=m
|
||||
CONFIG_QCOM_Q6V5_MSS=m
|
||||
CONFIG_QCOM_Q6V5_PAS=m
|
||||
# CONFIG_QCOM_Q6V5_WCSS is not set
|
||||
CONFIG_QCOM_RMTFS_MEM=m
|
||||
# CONFIG_QCOM_RPMH is not set
|
||||
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
|
||||
CONFIG_QCOM_SPMI_ADC5=m
|
||||
CONFIG_QCOM_SYSMON=m
|
||||
CONFIG_QEDE=m
|
||||
CONFIG_QEDF=m
|
||||
|
|
@ -4883,6 +4893,7 @@ CONFIG_RESET_GPIO=y
|
|||
# CONFIG_RESET_HSDK_V1 is not set
|
||||
# CONFIG_RESET_MESON_AUDIO_ARB is not set
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
CONFIG_RESET_QCOM_PDC=m
|
||||
CONFIG_RESET_SIMPLE=y
|
||||
# CONFIG_RESET_TI_SCI is not set
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
|
@ -6990,6 +7001,7 @@ CONFIG_VIDEO_HDPVR=m
|
|||
CONFIG_VIDEO_HEXIUM_GEMINI=m
|
||||
CONFIG_VIDEO_HEXIUM_ORION=m
|
||||
# CONFIG_VIDEO_IMX_MEDIA is not set
|
||||
CONFIG_VIDEO_IMX_PXP=m
|
||||
# CONFIG_VIDEO_IVTV_ALSA is not set
|
||||
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
|
||||
CONFIG_VIDEO_IVTV=m
|
||||
|
|
@ -7069,6 +7081,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_AFE4403 is not set
|
||||
|
|
@ -2402,6 +2404,7 @@ CONFIG_IMA=y
|
|||
# CONFIG_IMG_ASCII_LCD is not set
|
||||
# CONFIG_IMX_IPUV3_CORE is not set
|
||||
CONFIG_IMX_MBOX=m
|
||||
CONFIG_IMX_SCU=y
|
||||
# CONFIG_INA2XX_ADC is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
|
|
@ -3103,6 +3106,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=32768
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3189,6 +3193,7 @@ CONFIG_MAX_RAW_DEVS=8192
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -3259,6 +3264,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
|
|||
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
|
||||
# CONFIG_MEMTEST is not set
|
||||
# CONFIG_MEN_A21_WDT is not set
|
||||
CONFIG_MESON_CANVAS=m
|
||||
CONFIG_MESON_EFUSE=m
|
||||
# CONFIG_MESON_GXBB_WATCHDOG is not set
|
||||
# CONFIG_MESON_GXL_PHY is not set
|
||||
|
|
@ -4675,10 +4681,14 @@ CONFIG_QCOM_CLK_APCS_MSM8916=m
|
|||
# CONFIG_QCOM_LLCC is not set
|
||||
CONFIG_QCOM_PDC=y
|
||||
CONFIG_QCOM_PM8XXX_XOADC=m
|
||||
CONFIG_QCOM_Q6V5_ADSP=m
|
||||
CONFIG_QCOM_Q6V5_MSS=m
|
||||
CONFIG_QCOM_Q6V5_PAS=m
|
||||
# CONFIG_QCOM_Q6V5_WCSS is not set
|
||||
CONFIG_QCOM_RMTFS_MEM=m
|
||||
# CONFIG_QCOM_RPMH is not set
|
||||
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
|
||||
CONFIG_QCOM_SPMI_ADC5=m
|
||||
CONFIG_QCOM_SYSMON=m
|
||||
CONFIG_QEDE=m
|
||||
CONFIG_QEDF=m
|
||||
|
|
@ -4860,6 +4870,7 @@ CONFIG_RESET_GPIO=y
|
|||
# CONFIG_RESET_HSDK_V1 is not set
|
||||
# CONFIG_RESET_MESON_AUDIO_ARB is not set
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
CONFIG_RESET_QCOM_PDC=m
|
||||
CONFIG_RESET_SIMPLE=y
|
||||
# CONFIG_RESET_TI_SCI is not set
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
|
@ -6966,6 +6977,7 @@ CONFIG_VIDEO_HDPVR=m
|
|||
CONFIG_VIDEO_HEXIUM_GEMINI=m
|
||||
CONFIG_VIDEO_HEXIUM_ORION=m
|
||||
# CONFIG_VIDEO_IMX_MEDIA is not set
|
||||
CONFIG_VIDEO_IMX_PXP=m
|
||||
# CONFIG_VIDEO_IVTV_ALSA is not set
|
||||
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
|
||||
CONFIG_VIDEO_IVTV=m
|
||||
|
|
@ -7045,6 +7057,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_AFE4403 is not set
|
||||
|
|
@ -2523,6 +2525,7 @@ CONFIG_IMX_GPCV2=y
|
|||
CONFIG_IMX_IPUV3_CORE=m
|
||||
CONFIG_IMX_MBOX=m
|
||||
CONFIG_IMX_REMOTEPROC=m
|
||||
CONFIG_IMX_SCU=y
|
||||
CONFIG_IMX_SDMA=m
|
||||
CONFIG_IMX_THERMAL=m
|
||||
CONFIG_IMX_WEIM=y
|
||||
|
|
@ -3243,6 +3246,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=32768
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3335,6 +3339,7 @@ CONFIG_MAX_RAW_DEVS=8192
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -3407,6 +3412,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
|
|||
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
|
||||
# CONFIG_MEMTEST is not set
|
||||
# CONFIG_MEN_A21_WDT is not set
|
||||
CONFIG_MESON_CANVAS=m
|
||||
CONFIG_MESON_EFUSE=m
|
||||
# CONFIG_MESON_GXBB_WATCHDOG is not set
|
||||
# CONFIG_MESON_GXL_PHY is not set
|
||||
|
|
@ -4936,6 +4942,9 @@ CONFIG_QCOM_IOMMU=y
|
|||
CONFIG_QCOM_PDC=y
|
||||
CONFIG_QCOM_PM8XXX_XOADC=m
|
||||
CONFIG_QCOM_PM=y
|
||||
CONFIG_QCOM_Q6V5_ADSP=m
|
||||
CONFIG_QCOM_Q6V5_MSS=m
|
||||
CONFIG_QCOM_Q6V5_PAS=m
|
||||
CONFIG_QCOM_Q6V5_PIL=m
|
||||
# CONFIG_QCOM_Q6V5_WCSS is not set
|
||||
CONFIG_QCOM_QFPROM=m
|
||||
|
|
@ -4946,6 +4955,7 @@ CONFIG_QCOM_SMD_RPM=m
|
|||
CONFIG_QCOM_SMEM=m
|
||||
CONFIG_QCOM_SMP2P=m
|
||||
CONFIG_QCOM_SMSM=m
|
||||
CONFIG_QCOM_SPMI_ADC5=m
|
||||
CONFIG_QCOM_SPMI_IADC=m
|
||||
CONFIG_QCOM_SPMI_TEMP_ALARM=m
|
||||
CONFIG_QCOM_SPMI_VADC=m
|
||||
|
|
@ -5151,6 +5161,7 @@ CONFIG_RESET_GPIO=y
|
|||
# CONFIG_RESET_HSDK_V1 is not set
|
||||
# CONFIG_RESET_MESON_AUDIO_ARB is not set
|
||||
# CONFIG_RESET_QCOM_AOSS is not set
|
||||
CONFIG_RESET_QCOM_PDC=m
|
||||
CONFIG_RESET_SIMPLE=y
|
||||
# CONFIG_RESET_TI_SCI is not set
|
||||
# CONFIG_RESET_TI_SYSCON is not set
|
||||
|
|
@ -7402,6 +7413,7 @@ CONFIG_VIDEO_HDPVR=m
|
|||
CONFIG_VIDEO_HEXIUM_GEMINI=m
|
||||
CONFIG_VIDEO_HEXIUM_ORION=m
|
||||
# CONFIG_VIDEO_IMX_MEDIA is not set
|
||||
CONFIG_VIDEO_IMX_PXP=m
|
||||
CONFIG_VIDEO_IMX_VDOA=m
|
||||
# CONFIG_VIDEO_IVTV_ALSA is not set
|
||||
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
|
||||
|
|
@ -7495,6 +7507,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -158,6 +158,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -2995,6 +2997,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3074,6 +3077,7 @@ CONFIG_MAXSMP=y
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6593,6 +6597,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -158,6 +158,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -2972,6 +2974,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3051,6 +3054,7 @@ CONFIG_MAX_RAW_DEVS=8192
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6568,6 +6572,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -2774,6 +2776,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -2848,6 +2851,7 @@ CONFIG_MAXSMP=y
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6261,6 +6265,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -2751,6 +2753,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -2824,6 +2827,7 @@ CONFIG_MAX_RAW_DEVS=8192
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6234,6 +6238,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -2719,6 +2721,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -2793,6 +2796,7 @@ CONFIG_MAXSMP=y
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6152,6 +6156,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -2696,6 +2698,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -2769,6 +2772,7 @@ CONFIG_MAX_RAW_DEVS=8192
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6125,6 +6129,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -161,6 +161,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -3053,6 +3055,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3126,6 +3129,7 @@ CONFIG_MAXSMP=y
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6644,6 +6648,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
|
|
@ -161,6 +161,8 @@ CONFIG_ADAPTEC_STARFIRE=m
|
|||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL372_I2C=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
# CONFIG_ADXRS450 is not set
|
||||
# CONFIG_AFE4403 is not set
|
||||
# CONFIG_AFE4404 is not set
|
||||
|
|
@ -3030,6 +3032,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
|
|||
CONFIG_LPFC_NVME_TARGET=y
|
||||
CONFIG_LSI_ET1011C_PHY=m
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=65536
|
||||
CONFIG_LTC1660=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
# CONFIG_LTC2497 is not set
|
||||
|
|
@ -3103,6 +3106,7 @@ CONFIG_MAX_RAW_DEVS=8192
|
|||
# CONFIG_MCORE2 is not set
|
||||
# CONFIG_MCP320X is not set
|
||||
# CONFIG_MCP3422 is not set
|
||||
CONFIG_MCP3911=m
|
||||
CONFIG_MCP4018=m
|
||||
# CONFIG_MCP4131 is not set
|
||||
# CONFIG_MCP4531 is not set
|
||||
|
|
@ -6619,6 +6623,7 @@ CONFIG_VIRTIO_VSOCKETS=m
|
|||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_VL53L0X_I2C is not set
|
||||
CONFIG_VL6180=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
|
|
|
|||
11
kernel.spec
11
kernel.spec
|
|
@ -69,7 +69,7 @@ Summary: The Linux kernel
|
|||
# The rc snapshot level
|
||||
%global rcrev 0
|
||||
# The git snapshot level
|
||||
%define gitrev 5
|
||||
%define gitrev 6
|
||||
# Set rpm version accordingly
|
||||
%define rpmversion 4.%{upstream_sublevel}.0
|
||||
%endif
|
||||
|
|
@ -581,12 +581,6 @@ Patch305: qcom-msm89xx-fixes.patch
|
|||
# https://patchwork.kernel.org/project/linux-mmc/list/?submitter=71861
|
||||
Patch306: arm-sdhci-esdhc-imx-fixes.patch
|
||||
|
||||
# https://www.spinics.net/lists/arm-kernel/msg670137.html
|
||||
Patch307: arm64-ZynqMP-firmware-clock-drivers-core.patch
|
||||
|
||||
Patch308: arm64-96boards-Rock960-CE-board-support.patch
|
||||
Patch309: arm64-rockchip-add-initial-Rockpro64.patch
|
||||
|
||||
Patch330: bcm2835-cpufreq-add-CPU-frequency-control-driver.patch
|
||||
|
||||
Patch331: bcm283x-drm-vc4-set-is_yuv-to-false-when-num_planes-1.patch
|
||||
|
|
@ -1882,6 +1876,9 @@ fi
|
|||
#
|
||||
#
|
||||
%changelog
|
||||
* Tue Oct 30 2018 Justin M. Forbes <jforbes@fedoraproject.org> - 4.20.0-0.rc0.git6.1
|
||||
- Linux v4.19-11706-g11743c56785c
|
||||
|
||||
* Mon Oct 29 2018 Justin M. Forbes <jforbes@fedoraproject.org> - 4.20.0-0.rc0.git5.1
|
||||
- Linux v4.19-9448-g673c790e7282
|
||||
|
||||
|
|
|
|||
2
sources
2
sources
|
|
@ -1,2 +1,2 @@
|
|||
SHA512 (linux-4.19.tar.xz) = ab67cc746b375a8b135e8b23e35e1d6787930d19b3c26b2679787d62951cbdbc3bb66f8ededeb9b890e5008b2459397f9018f1a6772fdef67780b06a4cb9f6f4
|
||||
SHA512 (patch-4.19-git5.xz) = cdac8f1b9408ea7a7094ce1def5f4b8f8fd54781b7b02badcd2ae5d10dd0cd67388b9b392b38f58fd87ab4f68d828153d68631f23326e958fe978414963b7948
|
||||
SHA512 (patch-4.19-git6.xz) = 1936630e0205da2c4823be3401e645b743027d2e05ab310c6a89293187b3ad3dfb891ffb2365e594317368844a63b58383d86ddd3ca2bc45a6fc7b06b32091f3
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue