From ee95a2a44dd91a56038caafe37efaa53a427530e Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Wed, 1 May 2013 08:45:58 -0400 Subject: [PATCH] Add some powerpc fixes for POWER8 --- kernel.spec | 13 ++++++- powerpc-Add-isync-to-copy_and_flush.patch | 39 +++++++++++++++++++ ...RQs-with-MMU-on-exceptions-when-HV=0.patch | 39 +++++++++++++++++++ ...ondary-CPUs-hanging-on-boot-for-HV=0.patch | 33 ++++++++++++++++ 4 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 powerpc-Add-isync-to-copy_and_flush.patch create mode 100644 powerpc-Fix-hardware-IRQs-with-MMU-on-exceptions-when-HV=0.patch create mode 100644 powerpc-power8-Fix-secondary-CPUs-hanging-on-boot-for-HV=0.patch diff --git a/kernel.spec b/kernel.spec index 0f730ce52..da0914afb 100644 --- a/kernel.spec +++ b/kernel.spec @@ -62,7 +62,7 @@ Summary: The Linux kernel # For non-released -rc kernels, this will be appended after the rcX and # gitX tags, so a 3 here would become part of release "0.rcX.gitX.3" # -%global baserelease 301 +%global baserelease 302 %global fedora_build %{baserelease} # base_sublevel is the kernel version we're starting with and patching @@ -754,6 +754,10 @@ Patch25011: iwlwifi-fix-freeing-uninitialized-pointer.patch Patch25014: blkcg-fix-scheduling-while-atomic-in-blk_queue_bypass_start.patch +Patch25015: powerpc-Add-isync-to-copy_and_flush.patch +Patch25016: powerpc-power8-Fix-secondary-CPUs-hanging-on-boot-for-HV=0.patch +Patch25017: powerpc-Fix-hardware-IRQs-with-MMU-on-exceptions-when-HV=0.patch + # END OF PATCH DEFINITIONS %endif @@ -1457,6 +1461,10 @@ ApplyPatch iwlwifi-fix-freeing-uninitialized-pointer.patch ApplyPatch blkcg-fix-scheduling-while-atomic-in-blk_queue_bypass_start.patch +ApplyPatch powerpc-Add-isync-to-copy_and_flush.patch +ApplyPatch powerpc-power8-Fix-secondary-CPUs-hanging-on-boot-for-HV=0.patch +ApplyPatch powerpc-Fix-hardware-IRQs-with-MMU-on-exceptions-when-HV=0.patch + # END OF PATCH APPLICATIONS %endif @@ -2289,6 +2297,9 @@ fi # and build. %changelog +* Wed May 01 2013 Josh Boyer +- Add some powerpc fixes for POWER8 + * Tue Apr 30 2013 Peter Robinson - Enable CONFIG_SERIAL_8250_DW on ARM diff --git a/powerpc-Add-isync-to-copy_and_flush.patch b/powerpc-Add-isync-to-copy_and_flush.patch new file mode 100644 index 000000000..f9f3fa874 --- /dev/null +++ b/powerpc-Add-isync-to-copy_and_flush.patch @@ -0,0 +1,39 @@ +From 29ce3c5073057991217916abc25628e906911757 Mon Sep 17 00:00:00 2001 +From: Michael Neuling +Date: Wed, 24 Apr 2013 00:30:09 +0000 +Subject: powerpc: Add isync to copy_and_flush + +In __after_prom_start we copy the kernel down to zero in two calls to +copy_and_flush. After the first call (copy from 0 to copy_to_here:) +we jump to the newly copied code soon after. + +Unfortunately there's no isync between the copy of this code and the +jump to it. Hence it's possible that stale instructions could still be +in the icache or pipeline before we branch to it. + +We've seen this on real machines and it's results in no console output +after: + calling quiesce... + returning from prom_init + +The below adds an isync to ensure that the copy and flushing has +completed before any branching to the new instructions occurs. + +Signed-off-by: Michael Neuling +CC: +Signed-off-by: Benjamin Herrenschmidt +--- +diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S +index 0886ae6..b61363d 100644 +--- a/arch/powerpc/kernel/head_64.S ++++ b/arch/powerpc/kernel/head_64.S +@@ -509,6 +509,7 @@ _GLOBAL(copy_and_flush) + sync + addi r5,r5,8 + addi r6,r6,8 ++ isync + blr + + .align 8 +-- +cgit v0.9.1 diff --git a/powerpc-Fix-hardware-IRQs-with-MMU-on-exceptions-when-HV=0.patch b/powerpc-Fix-hardware-IRQs-with-MMU-on-exceptions-when-HV=0.patch new file mode 100644 index 000000000..c1a2a4687 --- /dev/null +++ b/powerpc-Fix-hardware-IRQs-with-MMU-on-exceptions-when-HV=0.patch @@ -0,0 +1,39 @@ +From 3e96ca7f007ddb06b82a74a68585d1dbafa85ff1 Mon Sep 17 00:00:00 2001 +From: Michael Neuling +Date: Thu, 25 Apr 2013 15:30:57 +0000 +Subject: powerpc: Fix hardware IRQs with MMU on exceptions when HV=0 + +POWER8 allows us to take interrupts with the MMU on. This gives us a +second set of vectors offset at 0x4000. + +Unfortunately when coping these vectors we missed checking for MSR HV +for hardware interrupts (0x500). This results in us trying to use +HSRR0/1 when HV=0, rather than SRR0/1 on HW IRQs + +The below fixes this to check CPU_FTR_HVMODE when patching the code at +0x4500. + +Also we remove the check for CPU_FTR_ARCH_206 since relocation on IRQs +are only available in arch 2.07 and beyond. + +Thanks to benh for helping find this. + +Signed-off-by: Michael Neuling +CC: +Signed-off-by: Benjamin Herrenschmidt +--- +diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S +index e789ee7..82ceab4 100644 +--- a/arch/powerpc/kernel/exceptions-64s.S ++++ b/arch/powerpc/kernel/exceptions-64s.S +@@ -797,7 +797,7 @@ hardware_interrupt_relon_hv: + _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV) + FTR_SECTION_ELSE + _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR) +- ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_206) ++ ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) + STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment) + STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check) + STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable) +-- +cgit v0.9.1 diff --git a/powerpc-power8-Fix-secondary-CPUs-hanging-on-boot-for-HV=0.patch b/powerpc-power8-Fix-secondary-CPUs-hanging-on-boot-for-HV=0.patch new file mode 100644 index 000000000..b3754af95 --- /dev/null +++ b/powerpc-power8-Fix-secondary-CPUs-hanging-on-boot-for-HV=0.patch @@ -0,0 +1,33 @@ +From 8c2a381734fc9718f127f4aba958e8a7958d4028 Mon Sep 17 00:00:00 2001 +From: Michael Neuling +Date: Wed, 24 Apr 2013 21:00:37 +0000 +Subject: powerpc/power8: Fix secondary CPUs hanging on boot for HV=0 + +In __restore_cpu_power8 we determine if we are HV and if not, we return +before setting HV only resources. + +Unfortunately we forgot to restore the link register from r11 before +returning. + +This will happen on boot and with secondary CPUs not coming online. + +This adds the missing link register restore. + +Signed-off-by: Michael Neuling +CC: +Signed-off-by: Benjamin Herrenschmidt +--- +diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S +index 2e6ad11..4daa5b7 100644 +--- a/arch/powerpc/kernel/cpu_setup_power.S ++++ b/arch/powerpc/kernel/cpu_setup_power.S +@@ -67,6 +67,7 @@ _GLOBAL(__restore_cpu_power8) + bl __init_FSCR + mfmsr r3 + rldicl. r0,r3,4,63 ++ mtlr r11 + beqlr + li r0,0 + mtspr SPRN_LPID,r0 +-- +cgit v0.9.1