65 lines
2.8 KiB
Diff
65 lines
2.8 KiB
Diff
From patchwork Thu Mar 26 12:20:01 2020
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: drm/vc4: Fix HDMI mode validation
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From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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X-Patchwork-Id: 358980
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Message-Id: <20200326122001.22215-1-nsaenzjulienne@suse.de>
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To: Eric Anholt <eric@anholt.net>,
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Daniel Vetter <daniel.vetter@ffwll.ch>
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Cc: Stefan Wahren <stefan.wahren@i2se.com>, f.fainelli@gmail.com,
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Dave Stevenson <dave.stevenson@raspberrypi.com>,
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David Airlie <airlied@linux.ie>, linux-kernel@vger.kernel.org,
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dri-devel@lists.freedesktop.org, maxime@cerno.tech,
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Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
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linux-rpi-kernel@lists.infradead.org
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Date: Thu, 26 Mar 2020 13:20:01 +0100
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Current mode validation impedes setting up some video modes which should
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be supported otherwise. Namely 1920x1200@60Hz.
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Fix this by lowering the minimum HDMI state machine clock to pixel clock
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ratio allowed.
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Fixes: 32e823c63e90 ("drm/vc4: Reject HDMI modes with too high of clocks")
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Reported-by: Stefan Wahren <stefan.wahren@i2se.com>
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Suggested-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Reviewed-by: Maxime Ripard <mripard@kernel.org>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 20 ++++++++++++++++----
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1 file changed, 16 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
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index cea18dc15f77..340719238753 100644
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -681,11 +681,23 @@ static enum drm_mode_status
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vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
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const struct drm_display_mode *mode)
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{
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- /* HSM clock must be 108% of the pixel clock. Additionally,
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- * the AXI clock needs to be at least 25% of pixel clock, but
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- * HSM ends up being the limiting factor.
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+ /*
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+ * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
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+ * be faster than pixel clock, infinitesimally faster, tested in
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+ * simulation. Otherwise, exact value is unimportant for HDMI
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+ * operation." This conflicts with bcm2835's vc4 documentation, which
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+ * states HSM's clock has to be at least 108% of the pixel clock.
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+ *
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+ * Real life tests reveal that vc4's firmware statement holds up, and
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+ * users are able to use pixel clocks closer to HSM's, namely for
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+ * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
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+ * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
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+ * 162MHz.
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+ *
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+ * Additionally, the AXI clock needs to be at least 25% of
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+ * pixel clock, but HSM ends up being the limiting factor.
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*/
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- if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
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+ if (mode->clock > HSM_CLOCK_FREQ / (1000 * 101 / 100))
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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