From 73ba30c91eaac63037bd557e3c07c9251de8839d Mon Sep 17 00:00:00 2001 From: Fedora Release Engineering Date: Fri, 17 Jan 2025 15:50:47 +0000 Subject: [PATCH 1/4] Rebuilt for https://fedoraproject.org/wiki/Fedora_42_Mass_Rebuild --- llvm12.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm12.spec b/llvm12.spec index eea7d81..95e36a1 100644 --- a/llvm12.spec +++ b/llvm12.spec @@ -48,7 +48,7 @@ Name: %{pkg_name} Version: %{maj_ver}.%{min_ver}.%{patch_ver}%{?rc_ver:~rc%{rc_ver}} -Release: 12%{?dist} +Release: 13%{?dist} Summary: The Low Level Virtual Machine License: NCSA @@ -517,6 +517,9 @@ fi %endif %changelog +* Fri Jan 17 2025 Fedora Release Engineering - 12.0.1-13 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_42_Mass_Rebuild + * Thu Jul 18 2024 Fedora Release Engineering - 12.0.1-12 - Rebuilt for https://fedoraproject.org/wiki/Fedora_41_Mass_Rebuild From d82dc37af715d0d4112abd604168ddfee7218470 Mon Sep 17 00:00:00 2001 From: Jens Petersen Date: Mon, 28 Apr 2025 13:01:14 +0800 Subject: [PATCH 2/4] patch for sphinx ReleaseNotes wrapping errors RHEL 10 has sphinx-7.2.6 /builddir/build/BUILD/llvm-12.0.1.src/docs/ReleaseNotes.rst:146: ERROR: Unexpected indentation. /builddir/build/BUILD/llvm-12.0.1.src/docs/ReleaseNotes.rst:147: WARNING: Block quote ends without a blank line; unexpected unindent. /builddir/build/BUILD/llvm-12.0.1.src/docs/ReleaseNotes.rst:153: ERROR: Unexpected indentation. : --- llvm12-ReleaseNotes-sphinx-7.2.6-wrap.patch | 229 ++++++++++++++++++++ llvm12.spec | 2 + 2 files changed, 231 insertions(+) create mode 100644 llvm12-ReleaseNotes-sphinx-7.2.6-wrap.patch diff --git a/llvm12-ReleaseNotes-sphinx-7.2.6-wrap.patch b/llvm12-ReleaseNotes-sphinx-7.2.6-wrap.patch new file mode 100644 index 0000000..52c7333 --- /dev/null +++ b/llvm12-ReleaseNotes-sphinx-7.2.6-wrap.patch @@ -0,0 +1,229 @@ +--- llvm-12.0.1.src/docs/ReleaseNotes.rst~ 2021-06-29 00:23:38.000000000 +0800 ++++ llvm-12.0.1.src/docs/ReleaseNotes.rst 2025-04-26 17:03:03.640319913 +0800 +@@ -40,8 +40,7 @@ + functionality, or simply have a lot to talk about), see the `NOTE` below + for adding a new subsection. + +-* The ConstantPropagation pass was removed. Users should use the InstSimplify +- pass instead. ++* The ConstantPropagation pass was removed. Users should use the InstSimplify pass instead. + + + .. NOTE +@@ -60,60 +59,37 @@ + + * ... + +-* Added the ``byref`` attribute to better represent argument passing +- for the `amdgpu_kernel` calling convention. ++* Added the ``byref`` attribute to better represent argument passing for the `amdgpu_kernel` calling convention. + +-* Added type parameter to the ``sret`` attribute to continue work on +- removing pointer element types. ++* Added type parameter to the ``sret`` attribute to continue work on removing pointer element types. + +-* The ``llvm.experimental.vector.reduce`` family of intrinsics have been renamed +- to drop the "experimental" from the name, reflecting their now fully supported +- status in the IR. ++* The ``llvm.experimental.vector.reduce`` family of intrinsics have been renamed to drop the "experimental" from the name, reflecting their now fully supported status in the IR. + + + Changes to building LLVM + ------------------------ + +-* The internal ``llvm-build`` Python script and the associated ``LLVMBuild.txt`` +- files used to describe the LLVM component structure have been removed and +- replaced by a pure ``CMake`` approach, where each component stores extra +- properties in the created targets. These properties are processed once all +- components are defined to resolve library dependencies and produce the header +- expected by llvm-config. ++* The internal ``llvm-build`` Python script and the associated ``LLVMBuild.txt`` files used to describe the LLVM component structure have been removed and replaced by a pure ``CMake`` approach, where each component stores extra properties in the created targets. These properties are processed once all components are defined to resolve library dependencies and produce the header expected by llvm-config. + + Changes to TableGen + ------------------- + +-* The new "TableGen Programmer's Reference" replaces the "TableGen Language +- Introduction" and "TableGen Language Reference" documents. ++* The new "TableGen Programmer's Reference" replaces the "TableGen Language Introduction" and "TableGen Language Reference" documents. + +-* The syntax for specifying an integer range in a range list has changed. +- The old syntax used a hyphen in the range (e.g., ``{0-9}``). The new syntax +- uses the "`...`" range punctuation (e.g., ``{0...9}``). The hyphen syntax +- is deprecated. ++* The syntax for specifying an integer range in a range list has changed. The old syntax used a hyphen in the range (e.g., ``{0-9}``). The new syntax uses the "`...`" range punctuation (e.g., ``{0...9}``). The hyphen syntax is deprecated. + + Changes to the AArch64 Backend + -------------------------- + + During this release ... + +-* Lots of improvements to generation of Windows unwind data; the unwind +- data is optimized and written in packed form where possible, reducing +- the size of unwind data (pdata and xdata sections) by around 60% +- compared with LLVM 11. The generation of prologs/epilogs is tweaked +- when targeting Windows, to increase the chances of being able to use +- the packed unwind info format. +- +-* Support for creating Windows unwind data using ``.seh_*`` assembler +- directives. +- +-* Produce proper assembly output for the Windows target, including +- ``:lo12:`` relocation specifiers, to allow the assembly output +- to actually be assembled. +- +-* Changed the assembly comment string for MSVC targets to ``//`` (consistent +- with the MinGW and ELF targets), freeing up ``;`` to be used as +- statement separator. ++* Lots of improvements to generation of Windows unwind data; the unwind data is optimized and written in packed form where possible, reducing the size of unwind data (pdata and xdata sections) by around 60% compared with LLVM 11. The generation of prologs/epilogs is tweaked when targeting Windows, to increase the chances of being able to use the packed unwind info format. ++ ++* Support for creating Windows unwind data using ``.seh_*`` assembler directives. ++ ++* Produce proper assembly output for the Windows target, including ``:lo12:`` relocation specifiers, to allow the assembly output to actually be assembled. ++ ++* Changed the assembly comment string for MSVC targets to ``//`` (consistent with the MinGW and ELF targets), freeing up ``;`` to be used as statement separator. + + Changes to the ARM Backend + -------------------------- +@@ -131,51 +107,39 @@ + + Optimization: + +-* Made improvements to loop unroll-and-jam including fix to respect user +- provided #pragma unroll-and-jam for loops on targets other than ARM. +-* Improved PartialInliner allowing it to handle code regions in a switch +- statements. +-* Improved PGO support on AIX by building and linking with compiler-rt profile +- library. ++* Made improvements to loop unroll-and-jam including fix to respect user provided #pragma unroll-and-jam for loops on targets other than ARM. ++* Improved PartialInliner allowing it to handle code regions in a switch statements. ++* Improved PGO support on AIX by building and linking with compiler-rt profile library. + * Add support for Epilogue Vectorization and enabled it by default. + + CodeGen: + + * POWER10 support +- * Implementation of PC Relative addressing in LLD including the associated +- linker optimizations. +- * Add support for the new matrix multiplication (MMA) instructions to Clang +- and LLVM. ++ * Implementation of PC Relative addressing in LLD including the associated linker optimizations. ++ * Add support for the new matrix multiplication (MMA) instructions to Clang and LLVM. + * Implementation of Power10 builtins. + + * Scheduling enhancements +- * Add a new algorithm to cluster more loads/stores if the DAG is not too +- complicated. ++ * Add a new algorithm to cluster more loads/stores if the DAG is not too complicated. + * Enable the PowerPC scheduling heuristic for Power10. + + * Target dependent passes tuning +- * Enhance LoopStrengthReduce/PPCLoopInstrFormPrep pass for PowerPC, +- especially for P10 intrinsics. ++ * Enhance LoopStrengthReduce/PPCLoopInstrFormPrep pass for PowerPC, especially for P10 intrinsics. + * Enhance machine combiner pass to reduce register pressure for PowerPC. +- * Improve MachineSink to do more sinking based on register pressure and alias +- analysis. ++ * Improve MachineSink to do more sinking based on register pressure and alias analysis. + + * General improvements + * Complete the constrained floating point operations support. + * Improve the llvm-exegesis support. +- * Improve the stack clash protection to probe the gap between stackptr and +- realigned stackptr. ++ * Improve the stack clash protection to probe the gap between stackptr and realigned stackptr. + * Improve the IEEE long double support for Power8. + * Enable MemorySSA for LoopSink. +- * Enhance LLVM debugging functionality via options such as -print-changed and +- -print-before-changed. ++ * Enhance LLVM debugging functionality via options such as -print-changed and -print-before-changed. + * Add builtins for Power9 (i.e. darn, xvtdiv, xvtsqrt etc). + * Add options to disable all or part of LoopIdiomRecognizePass. +- * Add support for printing the DDG in DOT form allowing for visual inspection +- of the Data Dependence Graph. ++ * Add support for printing the DDG in DOT form allowing for visual inspection of the Data Dependence Graph. + * Remove the QPX support. +- * Significant number of bug fixes including all the fixes necessary to +- achieve a clean test run for Julia. ++ * Significant number of bug fixes including all the fixes necessary to achieve a clean test run for Julia. + + AIX Support: + +@@ -186,14 +150,11 @@ + * General Improvements + * Enable the AIX extended AltiVec ABI under option -mabi=vec-extabi. + * Add partial C99 complex type support. +- * Implemente traceback table for functions (encodes vector information, +- emits exception handling). +- * Implemente code generation for C++ dynamic initialization and finalization. +- of non-local variables for use with the -bcdtors option of the AIX linker. ++ * Implemente traceback table for functions (encodes vector information, emits exception handling). ++ * Implemente code generation for C++ dynamic initialization and finalization of non-local variables for use with the -bcdtors option of the AIX linker. + * Add new option -mignore-xcoff-visibility. + * Enable explicit sections on AIX. +- * Enable -f[no-]data-sections on AIX and set -fdata-sections to be the default +- on AIX. ++ * Enable -f[no-]data-sections on AIX and set -fdata-sections to be the default on AIX. + * Enable -f[no-]function-sections. + * Add support for relocation generation using the large code model. + * Add pragma align natural and sorted out pragma pack stack effect. +@@ -204,19 +165,10 @@ + + During this release ... + +-* The 'mpx' feature was removed from the backend. It had been removed from clang +- frontend in 10.0. Mention of the 'mpx' feature in an IR file will print a +- message to stderr, but IR should still compile. +-* Support for ``-march=alderlake``, ``-march=sapphirerapids``, +- ``-march=znver3`` and ``-march=x86-64-v[234]`` has been added. +-* The assembler now has support for {disp32} and {disp8} pseudo prefixes for +- controlling displacement size for memory operands and jump displacements. The +- assembler also supports the .d32 and .d8 mnemonic suffixes to do the same. +-* A new function attribute "tune-cpu" has been added to support -mtune like gcc. +- This allows microarchitectural optimizations to be applied independent from +- the "target-cpu" attribute or TargetMachine CPU which will be used to select +- Instruction Set. If the attribute is not present, the tune CPU will follow +- the target CPU. ++* The 'mpx' feature was removed from the backend. It had been removed from clang frontend in 10.0. Mention of the 'mpx' feature in an IR file will print a message to stderr, but IR should still compile. ++* Support for ``-march=alderlake``, ``-march=sapphirerapids``, ``-march=znver3`` and ``-march=x86-64-v[234]`` has been added. ++* The assembler now has support for {disp32} and {disp8} pseudo prefixes for controlling displacement size for memory operands and jump displacements. The assembler also supports the .d32 and .d8 mnemonic suffixes to do the same. ++* A new function attribute "tune-cpu" has been added to support -mtune like gcc. This allows microarchitectural optimizations to be applied independent from the "target-cpu" attribute or TargetMachine CPU which will be used to select Instruction Set. If the attribute is not present, the tune CPU will follow the target CPU. + * Support for ``HRESET`` instructions has been added. + * Support for ``UINTR`` instructions has been added. + * Support for ``AVXVNNI`` instructions has been added. +@@ -226,8 +178,7 @@ + + During this release ... + +-* The new ``byref`` attribute is now the preferred method for +- representing aggregate kernel arguments. ++* The new ``byref`` attribute is now the preferred method for representing aggregate kernel arguments. + + Changes to the AVR Target + ----------------------------- +@@ -260,22 +211,14 @@ + + During this release ... + +-* The DIModule metadata is extended with a field to indicate if it is a +- module declaration. This extension enables the emission of debug info +- for a Fortran 'use ' statement. For more information +- on what the debug info entries should look like and how the debugger +- can use them, please see test/DebugInfo/X86/dimodule-external-fortran.ll. ++* The DIModule metadata is extended with a field to indicate if it is a module declaration. This extension enables the emission of debug info for a Fortran 'use ' statement. For more information on what the debug info entries should look like and how the debugger can use them, please see test/DebugInfo/X86/dimodule-external-fortran.ll. + + Changes to the LLVM tools + --------------------------------- + +-* llvm-readobj and llvm-readelf behavior has changed to report an error when +- executed with no input files instead of reading an input from stdin. +- Reading from stdin can still be achieved by specifying `-` as an input file. +- +-* llvm-mca supports serialization of the timeline and summary views. +- The `--json` command line option prints a JSON representation of +- these views to stdout. ++* llvm-readobj and llvm-readelf behavior has changed to report an error when executed with no input files instead of reading an input from stdin. Reading from stdin can still be achieved by specifying `-` as an input file. ++ ++* llvm-mca supports serialization of the timeline and summary views. The `--json` command line option prints a JSON representation of these views to stdout. + + Changes to LLDB + --------------------------------- diff --git a/llvm12.spec b/llvm12.spec index 95e36a1..853726a 100644 --- a/llvm12.spec +++ b/llvm12.spec @@ -68,6 +68,7 @@ Patch2: typename.patch Patch3: test-go-py-pipes.patch Patch101: 0001-Deactivate-markdown-doc.patch +Patch102: llvm12-ReleaseNotes-sphinx-7.2.6-wrap.patch BuildRequires: gcc BuildRequires: gcc-c++ @@ -187,6 +188,7 @@ LLVM's modified googletest sources. %if %{defined el9} %patch -P101 -p2 -b .orig %endif +%patch -P102 -p1 -b .orig %py3_shebang_fix \ test/BugPoint/compile-custom.ll.py \ From 0a0f11217c9546c46c8eb4474e6c81e86dea675a Mon Sep 17 00:00:00 2001 From: Jens Petersen Date: Mon, 28 Apr 2025 13:04:18 +0800 Subject: [PATCH 3/4] rhel10 also needs python3-recommonmark --- llvm12.spec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm12.spec b/llvm12.spec index 853726a..525e7aa 100644 --- a/llvm12.spec +++ b/llvm12.spec @@ -79,7 +79,7 @@ BuildRequires: libffi-devel BuildRequires: ncurses-devel BuildRequires: python3-psutil BuildRequires: python3-sphinx -%if %{defined fedora} +%if %{defined fedora} || 0%{?rhel} >= 10 BuildRequires: python3-recommonmark %endif BuildRequires: multilib-rpm-config From ada66de9c4a5722d9629d2913bca039550022bc9 Mon Sep 17 00:00:00 2001 From: Fedora Release Engineering Date: Thu, 24 Jul 2025 20:47:30 +0000 Subject: [PATCH 4/4] Rebuilt for https://fedoraproject.org/wiki/Fedora_43_Mass_Rebuild --- llvm12.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm12.spec b/llvm12.spec index 525e7aa..80161e2 100644 --- a/llvm12.spec +++ b/llvm12.spec @@ -48,7 +48,7 @@ Name: %{pkg_name} Version: %{maj_ver}.%{min_ver}.%{patch_ver}%{?rc_ver:~rc%{rc_ver}} -Release: 13%{?dist} +Release: 14%{?dist} Summary: The Low Level Virtual Machine License: NCSA @@ -519,6 +519,9 @@ fi %endif %changelog +* Thu Jul 24 2025 Fedora Release Engineering - 12.0.1-14 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_43_Mass_Rebuild + * Fri Jan 17 2025 Fedora Release Engineering - 12.0.1-13 - Rebuilt for https://fedoraproject.org/wiki/Fedora_42_Mass_Rebuild