520 lines
23 KiB
Diff
520 lines
23 KiB
Diff
riscv64 support patch taken from Opensuse:
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https://build.opensuse.org/package/show/openSUSE:Factory:RISCV/libqt5-qtwebengine?rev=110
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Index: qtwebengine-everywhere-src-5.15.19/configure.pri
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/configure.pri
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+++ qtwebengine-everywhere-src-5.15.19/configure.pri
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@@ -157,6 +157,7 @@ defineTest(qtConfTest_detectArch) {
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contains(QT_ARCH, "arm")|contains(QT_ARCH, "arm64"): return(true)
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contains(QT_ARCH, "mips"): return(true)
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contains(QT_ARCH, "mips64"): return(true)
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+ contains(QT_ARCH, "riscv64"): return(true)
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qtLog("Architecture not supported.")
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return(false)
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}
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Index: qtwebengine-everywhere-src-5.15.19/mkspecs/features/functions.prf
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/mkspecs/features/functions.prf
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+++ qtwebengine-everywhere-src-5.15.19/mkspecs/features/functions.prf
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@@ -112,6 +112,7 @@ defineReplace(gnArch) {
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contains(qtArch, "mips"): return(mipsel)
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contains(qtArch, "mips64"): return(mips64el)
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contains(qtArch, "mips64el"): return(mips64el)
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+ contains(qtArch, "riscv64"): return(riscv64)
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return(unknown)
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}
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/base/process/launch_posix.cc
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/base/process/launch_posix.cc
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/base/process/launch_posix.cc
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@@ -704,7 +704,7 @@ NOINLINE pid_t CloneAndLongjmpInChild(un
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alignas(16) char stack_buf[PTHREAD_STACK_MIN];
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#if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \
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defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_S390_FAMILY) || \
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- defined(ARCH_CPU_PPC64_FAMILY)
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+ defined(ARCH_CPU_PPC64_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY)
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// The stack grows downward.
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void* stack = stack_buf + sizeof(stack_buf);
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#else
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/build/build_config.h
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/build/build_config.h
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/build/build_config.h
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@@ -193,6 +193,11 @@
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#define ARCH_CPU_32_BITS 1
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#define ARCH_CPU_BIG_ENDIAN 1
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#endif
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+#elif defined(__riscv) && __riscv_xlen == 64
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+#define ARCH_CPU_RISCV_FAMILY 1
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+#define ARCH_CPU_RISCV64 1
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+#define ARCH_CPU_64_BITS 1
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+#define ARCH_CPU_LITTLE_ENDIAN 1
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#else
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#error Please add support for your architecture in build/build_config.h
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#endif
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn
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@@ -290,3 +290,20 @@ gcc_toolchain("mips64") {
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is_clang = false
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}
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}
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+
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+gcc_toolchain("riscv64") {
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+ cc = "gcc"
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+ cxx = "g++"
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+
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+ readelf = "readelf"
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+ nm = "nm"
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+ ar = "ar"
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+ ld = cxx
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+
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+ toolchain_args = {
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+ current_cpu = "riscv64"
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+ current_os = "linux"
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+ is_clang = false
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+ }
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+}
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+
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/skia/BUILD.gn
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/skia/BUILD.gn
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/skia/BUILD.gn
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@@ -821,6 +821,8 @@ skia_source_set("skia_opts") {
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sources = skia_opts.none_sources
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} else if (current_cpu == "s390x") {
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sources = skia_opts.none_sources
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+ } else if (current_cpu == "riscv64") {
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+ sources = skia_opts.none_sources
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} else {
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assert(false, "Need to port cpu specific stuff from skia_library_opts.gyp")
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}
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/angle/gni/angle.gni
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/angle/gni/angle.gni
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/angle/gni/angle.gni
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@@ -54,7 +54,7 @@ angle_data_dir = "angledata"
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declare_args() {
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if (current_cpu == "arm64" || current_cpu == "x64" ||
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current_cpu == "mips64el" || current_cpu == "s390x" ||
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- current_cpu == "ppc64") {
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+ current_cpu == "ppc64" || current_cpu == "riscv64") {
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angle_64bit_current_cpu = true
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} else if (current_cpu == "arm" || current_cpu == "x86" ||
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current_cpu == "mipsel" || current_cpu == "s390" ||
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h
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@@ -9,6 +9,7 @@
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#ifndef ANGLE_PLATFORMMETHODS_H
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#define ANGLE_PLATFORMMETHODS_H
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+#include <stddef.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <array>
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn
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@@ -38,6 +38,8 @@ if (current_cpu == "x86" || current_cpu
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sources = [ "SaveRegisters_mips64.S" ]
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} else if (current_cpu == "ppc64") {
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sources = [ "SaveRegisters_ppc64.S" ]
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+ } else if (current_cpu == "riscv64") {
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+ sources = [ "SaveRegisters_riscv64.S" ]
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}
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if (current_cpu == "arm") {
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/SaveRegisters_riscv64.S
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===================================================================
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--- /dev/null
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/SaveRegisters_riscv64.S
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@@ -0,0 +1,45 @@
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+/*
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+ * typedef void (*PushAllRegistersCallback)(ThreadState*, intptr_t*);
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+ * extern "C" void PushAllRegisters(ThreadState*, PushAllRegistersCallback)
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+ */
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+
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+.type PushAllRegisters, %function
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+.global PushAllRegisters
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+.hidden PushAllRegisters
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+PushAllRegisters:
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+ /* Push all callee-saves registers to get them
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+ * on the stack for conservative stack scanning.
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+ * Reserve space for callee-saved registers and return address.
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+ */
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+ addi sp,sp,-112
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+ /* Save the callee-saved registers and the return address. */
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+ sd ra,0(sp)
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+ sd s0,8(sp)
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+ sd s1,16(sp)
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+ sd s2,24(sp)
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+ sd s3,32(sp)
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+ sd s4,40(sp)
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+ sd s5,48(sp)
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+ sd s6,56(sp)
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+ sd s7,64(sp)
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+ sd s8,72(sp)
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+ sd s9,80(sp)
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+ sd s10,88(sp)
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+ sd s11,96(sp)
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+ /* Note: the callee-saved floating point registers do not need to be
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+ * copied to the stack, because fp registers never hold heap pointers
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+ * and so do not need to be kept visible to the garbage collector.
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+ * Pass the first argument untouched in a0 and the
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+ * stack pointer to the callback.
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+ */
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+ mv ra,a1
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+ mv a1,sp
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+ jalr ra
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+ /* Restore return address, adjust stack and return.
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+ * Note: the copied registers do not need to be reloaded here,
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+ * because they were preserved by the called routine.
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+ */
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+ ld ra,0(sp)
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+ addi sp,sp,112
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+ ret
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+.size PushAllRegisters, . - PushAllRegisters
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h
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@@ -105,6 +105,8 @@ extern "C" {
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#elif defined(__mips__) && defined(__LP64__)
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#define OPENSSL_64_BIT
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#define OPENSSL_MIPS64
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+#elif defined(__riscv) && __SIZEOF_POINTER__ == 8
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+#define OPENSSL_64_BIT
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#elif defined(__pnacl__)
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#define OPENSSL_32_BIT
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#define OPENSSL_PNACL
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/dav1d/config/linux/riscv64/config.h
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===================================================================
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--- /dev/null
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/dav1d/config/linux/riscv64/config.h
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@@ -0,0 +1,38 @@
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+/*
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+ * Autogenerated by the Meson build system.
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+ * Do not edit, your changes will be lost.
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+ */
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+
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+#pragma once
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+
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+#define ARCH_AARCH64 0
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+
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+#define ARCH_ARM 0
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+
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+#define ARCH_PPC64LE 0
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+
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+#define ARCH_X86 0
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+
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+#define ARCH_X86_32 0
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+
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+#define ARCH_X86_64 0
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+
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+#define CONFIG_16BPC 1
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+
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+#define CONFIG_8BPC 1
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+
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+// #define CONFIG_LOG 1 -- Logging is controlled by Chromium
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+
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+#define ENDIANNESS_BIG 0
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+
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+#define HAVE_ASM 0
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+
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+#define HAVE_AS_FUNC 0
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+
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+#define HAVE_CLOCK_GETTIME 1
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+
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+#define HAVE_GETAUXVAL 1
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+
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+#define HAVE_POSIX_MEMALIGN 1
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+
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+#define HAVE_UNISTD_H 1
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Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h
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===================================================================
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--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h
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+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h
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@@ -88,7 +88,7 @@
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*/
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#if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) || \
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defined(__mips__) || defined(__PPC__) || defined(__ARM_EABI__) || \
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- defined(__aarch64__) || defined(__s390__)) \
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+ defined(__aarch64__) || defined(__s390__) || defined(__riscv)) \
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&& (defined(__linux) || defined(__ANDROID__))
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#ifndef SYS_CPLUSPLUS
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@@ -301,7 +301,7 @@ struct kernel_old_sigaction {
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} __attribute__((packed,aligned(4)));
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#elif (defined(__mips__) && _MIPS_SIM == _MIPS_SIM_ABI32)
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#define kernel_old_sigaction kernel_sigaction
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-#elif defined(__aarch64__)
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+#elif defined(__aarch64__) || defined(__riscv)
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// No kernel_old_sigaction defined for arm64.
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#endif
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@@ -341,7 +341,9 @@ struct kernel_sigaction {
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void (*sa_sigaction_)(int, siginfo_t *, void *);
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};
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unsigned long sa_flags;
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+#ifndef __riscv
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void (*sa_restorer)(void);
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+#endif
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struct kernel_sigset_t sa_mask;
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#endif
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};
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@@ -519,7 +521,7 @@ struct kernel_stat {
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int st_blocks;
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int st_pad4[14];
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};
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-#elif defined(__aarch64__)
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+#elif defined(__aarch64__) || defined(__riscv)
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struct kernel_stat {
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unsigned long st_dev;
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unsigned long st_ino;
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@@ -1065,7 +1067,7 @@ struct kernel_statfs {
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#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
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#endif
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/* End of ARM 3/EABI definitions */
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-#elif defined(__aarch64__)
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+#elif defined(__aarch64__) || defined(__riscv)
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#ifndef __NR_setxattr
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#define __NR_setxattr 5
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#endif
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@@ -1880,7 +1882,7 @@ struct kernel_statfs {
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#undef LSS_RETURN
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#if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) \
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- || defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__))
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+ || defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__) || defined(__riscv))
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/* Failing system calls return a negative result in the range of
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* -1..-4095. These are "errno" values with the sign inverted.
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*/
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@@ -3373,6 +3375,122 @@ struct kernel_statfs {
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}
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LSS_RETURN(int, __ret);
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}
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+ #elif defined(__riscv)
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+ #undef LSS_REG
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+ #define LSS_REG(r,a) register int64_t __r##r __asm__("a"#r) = (int64_t)a
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+ #undef LSS_BODY
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+ #define LSS_BODY(type,name,args...) \
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+ register int64_t __res_a0 __asm__("a0"); \
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+ register int64_t __a7 __asm__("a7") = __NR_##name; \
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+ int64_t __res; \
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+ __asm__ __volatile__ ("scall\n" \
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+ : "=r"(__res_a0) \
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+ : "r"(__a7) , ## args \
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+ : "memory"); \
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+ __res = __res_a0; \
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+ LSS_RETURN(type, __res)
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+ #undef _syscall0
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+ #define _syscall0(type, name) \
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+ type LSS_NAME(name)(void) { \
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+ LSS_BODY(type, name); \
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+ }
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+ #undef _syscall1
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+ #define _syscall1(type, name, type1, arg1) \
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+ type LSS_NAME(name)(type1 arg1) { \
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+ LSS_REG(0, arg1); LSS_BODY(type, name, "r"(__r0)); \
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+ }
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+ #undef _syscall2
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+ #define _syscall2(type, name, type1, arg1, type2, arg2) \
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+ type LSS_NAME(name)(type1 arg1, type2 arg2) { \
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+ LSS_REG(0, arg1); LSS_REG(1, arg2); \
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+ LSS_BODY(type, name, "r"(__r0), "r"(__r1)); \
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+ }
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+ #undef _syscall3
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+ #define _syscall3(type, name, type1, arg1, type2, arg2, type3, arg3) \
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+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3) { \
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+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
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+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2)); \
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+ }
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+ #undef _syscall4
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+ #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
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+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
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+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
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+ LSS_REG(3, arg4); \
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+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3)); \
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+ }
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+ #undef _syscall5
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+ #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
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+ type5,arg5) \
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+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \
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+ type5 arg5) { \
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+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
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+ LSS_REG(3, arg4); LSS_REG(4, arg5); \
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+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \
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+ "r"(__r4)); \
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+ }
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+ #undef _syscall6
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+ #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
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+ type5,arg5,type6,arg6) \
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+ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \
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+ type5 arg5, type6 arg6) { \
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+ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
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+ LSS_REG(3, arg4); LSS_REG(4, arg5); LSS_REG(5, arg6); \
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+ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \
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+ "r"(__r4), "r"(__r5)); \
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+ }
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+
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+ LSS_INLINE int LSS_NAME(clone)(int (*fn)(void *), void *child_stack,
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+ int flags, void *arg, int *parent_tidptr,
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+ void *newtls, int *child_tidptr) {
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+ int64_t __res;
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+ {
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+ register int64_t __res_a0 __asm__("a0");
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+ register uint64_t __flags __asm__("a0") = flags;
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+ register void *__stack __asm__("a1") = child_stack;
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+ register void *__ptid __asm__("a2") = parent_tidptr;
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|
+ register void *__tls __asm__("a3") = newtls;
|
|
+ register int *__ctid __asm__("a4") = child_tidptr;
|
|
+ __asm__ __volatile__(/* Push "arg" and "fn" onto the stack that will be
|
|
+ * used by the child.
|
|
+ */
|
|
+ "addi %2,%2,-16\n"
|
|
+ "sd %1, 0(%2)\n"
|
|
+ "sd %4, 8(%2)\n"
|
|
+
|
|
+ /* %a0 = syscall(%a0 = flags,
|
|
+ * %a1 = child_stack,
|
|
+ * %a2 = parent_tidptr,
|
|
+ * %a3 = newtls,
|
|
+ * %a4 = child_tidptr)
|
|
+ */
|
|
+ "li a7, %8\n"
|
|
+ "scall\n"
|
|
+
|
|
+ /* if (%a0 != 0)
|
|
+ * return %a0;
|
|
+ */
|
|
+ "bnez %0, 1f\n"
|
|
+
|
|
+ /* In the child, now. Call "fn(arg)".
|
|
+ */
|
|
+ "ld a1, 0(sp)\n"
|
|
+ "ld a0, 8(sp)\n"
|
|
+ "jalr a1\n"
|
|
+
|
|
+ /* Call _exit(%a0).
|
|
+ */
|
|
+ "li a7, %9\n"
|
|
+ "scall\n"
|
|
+ "1:\n"
|
|
+ : "=r" (__res_a0)
|
|
+ : "r"(fn), "r"(__stack), "r"(__flags), "r"(arg),
|
|
+ "r"(__ptid), "r"(__tls), "r"(__ctid),
|
|
+ "i"(__NR_clone), "i"(__NR_exit)
|
|
+ : "cc", "memory");
|
|
+ __res = __res_a0;
|
|
+ }
|
|
+ LSS_RETURN(int, __res);
|
|
+ }
|
|
#endif
|
|
#define __NR__exit __NR_exit
|
|
#define __NR__gettid __NR_gettid
|
|
@@ -4181,7 +4299,7 @@ struct kernel_statfs {
|
|
LSS_SC_BODY(4, int, 8, d, type, protocol, sv);
|
|
}
|
|
#endif
|
|
- #if defined(__ARM_EABI__) || defined (__aarch64__)
|
|
+ #if defined(__ARM_EABI__) || defined (__aarch64__) || defined(__riscv)
|
|
LSS_INLINE _syscall3(ssize_t, recvmsg, int, s, struct kernel_msghdr*, msg,
|
|
int, flags)
|
|
LSS_INLINE _syscall3(ssize_t, sendmsg, int, s, const struct kernel_msghdr*,
|
|
@@ -4503,7 +4621,7 @@ struct kernel_statfs {
|
|
// TODO: define this in an arch-independant way instead of inlining the clone
|
|
// syscall body.
|
|
|
|
-# if defined(__aarch64__)
|
|
+# if defined(__aarch64__) || defined(__riscv)
|
|
LSS_INLINE pid_t LSS_NAME(fork)(void) {
|
|
// No fork syscall on aarch64 - implement by means of the clone syscall.
|
|
// Note that this does not reset glibc's cached view of the PID/TID, so
|
|
Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn
|
|
===================================================================
|
|
--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn
|
|
+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn
|
|
@@ -149,6 +149,7 @@ swiftshader_llvm_source_set("swiftshader
|
|
deps += [ ":swiftshader_llvm_ppc" ]
|
|
} else if (current_cpu == "x86" || current_cpu == "x64") {
|
|
deps += [ ":swiftshader_llvm_x86" ]
|
|
+ } else if (current_cpu == "riscv64") {
|
|
} else {
|
|
assert(false, "Unsupported current_cpu")
|
|
}
|
|
Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc
|
|
===================================================================
|
|
--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc
|
|
+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc
|
|
@@ -30,7 +30,7 @@ bool VectorDifference(const uint8_t* ima
|
|
static bool (*diff_proc)(const uint8_t*, const uint8_t*) = nullptr;
|
|
|
|
if (!diff_proc) {
|
|
-#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY)
|
|
+#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY) || defined(WEBRTC_ARCH_RISCV_FAMILY)
|
|
// For ARM and MIPS processors, always use C version.
|
|
// TODO(hclam): Implement a NEON version.
|
|
diff_proc = &VectorDifference_C;
|
|
Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h
|
|
===================================================================
|
|
--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h
|
|
+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h
|
|
@@ -50,6 +50,10 @@
|
|
#elif defined(__EMSCRIPTEN__)
|
|
#define WEBRTC_ARCH_32_BITS
|
|
#define WEBRTC_ARCH_LITTLE_ENDIAN
|
|
+#elif defined(__riscv) && __riscv_xlen == 64
|
|
+#define WEBRTC_ARCH_RISCV_FAMILY
|
|
+#define WEBRTC_ARCH_64_BITS
|
|
+#define WEBRTC_ARCH_LITTLE_ENDIAN
|
|
#else
|
|
#error Please add support for your architecture in rtc_base/system/arch.h
|
|
#endif
|
|
Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/gn/tools/gn/args.cc
|
|
===================================================================
|
|
--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/gn/tools/gn/args.cc
|
|
+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/gn/tools/gn/args.cc
|
|
@@ -329,6 +329,7 @@ void Args::SetSystemVarsLocked(Scope* de
|
|
static const char kMips64[] = "mips64el";
|
|
static const char kS390X[] = "s390x";
|
|
static const char kPPC64[] = "ppc64";
|
|
+ static const char kRiscv64[] = "riscv64";
|
|
const char* arch = nullptr;
|
|
|
|
// Set the host CPU architecture based on the underlying OS, not
|
|
@@ -353,6 +354,8 @@ void Args::SetSystemVarsLocked(Scope* de
|
|
// This allows us to use the same toolchain as ppc64 BE
|
|
// and specific flags are included using the host_byteorder logic.
|
|
arch = kPPC64;
|
|
+ else if (os_arch == "riscv64")
|
|
+ arch = kRiscv64;
|
|
else
|
|
CHECK(false) << "OS architecture not handled. (" << os_arch << ")";
|
|
|
|
Index: qtwebengine-everywhere-src-5.15.19/src/3rdparty/gn/util/build_config.h
|
|
===================================================================
|
|
--- qtwebengine-everywhere-src-5.15.19.orig/src/3rdparty/gn/util/build_config.h
|
|
+++ qtwebengine-everywhere-src-5.15.19/src/3rdparty/gn/util/build_config.h
|
|
@@ -172,6 +172,16 @@
|
|
#define ARCH_CPU_32_BITS 1
|
|
#define ARCH_CPU_BIG_ENDIAN 1
|
|
#endif
|
|
+#elif defined(__riscv)
|
|
+#define ARCH_CPU_RISCV_FAMILY 1
|
|
+#if __riscv_xlen == 64
|
|
+#define ARCH_CPU_RISCV64 1
|
|
+#define ARCH_CPU_64_BITS 1
|
|
+#else
|
|
+#define ARCH_CPU_RISCV32 1
|
|
+#define ARCH_CPU_32_BITS 1
|
|
+#endif
|
|
+#define ARCH_CPU_LITTLE_ENDIAN 1
|
|
#else
|
|
#error Please add support for your architecture in build_config.h
|
|
#endif
|