diff --git a/0001-Rebase-to-upstream-6.15.5-rockchip-DTs.patch b/0001-Rebase-to-upstream-6.15.5-rockchip-DTs.patch new file mode 100644 index 0000000..ecb69d5 --- /dev/null +++ b/0001-Rebase-to-upstream-6.15.5-rockchip-DTs.patch @@ -0,0 +1,3467 @@ +From c0f3a6ff6c7a7cfe857b4cda1b6f3615e25842d8 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 20 Jun 2025 13:29:43 +0100 +Subject: [PATCH] Rebase to upstream 6.15.5 rockchip DTs + +Signed-off-by: Peter Robinson +--- + .../arm64/rockchip/px30-engicam-common.dtsi | 3 +- + .../arm64/rockchip/px30-engicam-ctouch2.dtsi | 2 +- + .../px30-engicam-px30-core-edimm2.2.dts | 2 +- + .../arm64/rockchip/px30-ringneck-haikou.dts | 2 + + .../src/arm64/rockchip/px30-ringneck.dtsi | 4 - + .../src/arm64/rockchip/rk3308-roc-cc.dts | 2 +- + .../src/arm64/rockchip/rk3318-a95x-z2.dts | 4 +- + .../src/arm64/rockchip/rk3328-rock-pi-e.dts | 8 + + .../src/arm64/rockchip/rk3399-nanopi4.dtsi | 2 +- + .../src/arm64/rockchip/rk3399-puma-haikou.dts | 34 ++- + .../src/arm64/rockchip/rk3399-puma.dtsi | 58 +++-- + .../src/arm64/rockchip/rk3399-roc-pc-plus.dts | 2 +- + .../src/arm64/rockchip/rk3399-rock-pi-4.dtsi | 2 +- + dts/upstream/src/arm64/rockchip/rk3528.dtsi | 3 +- + .../rockchip/rk3566-bigtreetech-cb2.dtsi | 2 +- + .../src/arm64/rockchip/rk3566-pinenote.dtsi | 2 + + .../src/arm64/rockchip/rk3566-quartz64-a.dts | 8 +- + .../src/arm64/rockchip/rk3566-quartz64-b.dts | 8 +- + .../src/arm64/rockchip/rk3566-rock-3c.dts | 1 + + .../src/arm64/rockchip/rk3568-nanopi-r5s.dtsi | 5 +- + .../src/arm64/rockchip/rk3568-qnap-ts433.dts | 2 + + .../src/arm64/rockchip/rk3568-rock-3a.dts | 14 -- + .../src/arm64/rockchip/rk356x-base.dtsi | 44 ++-- + .../arm64/rockchip/rk3576-armsom-sige5.dts | 52 +++- + .../src/arm64/rockchip/rk3576-evb1-v10.dts | 47 ++++ + dts/upstream/src/arm64/rockchip/rk3576.dtsi | 192 ++++++++++++++- + .../src/arm64/rockchip/rk3588-armsom-lm7.dtsi | 4 + + .../arm64/rockchip/rk3588-armsom-sige7.dts | 75 ++++++ + .../src/arm64/rockchip/rk3588-base.dtsi | 117 +++++++-- + .../arm64/rockchip/rk3588-coolpi-cm5-evb.dts | 2 +- + .../rockchip/rk3588-coolpi-cm5-genbook.dts | 2 +- + .../src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 4 + + .../rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 + + .../rockchip/rk3588-edgeble-neu6a-io.dtsi | 47 ++++ + .../src/arm64/rockchip/rk3588-evb1-v10.dts | 50 +++- + .../src/arm64/rockchip/rk3588-extra.dtsi | 186 +++++++++++++++ + .../src/arm64/rockchip/rk3588-fet3588-c.dtsi | 4 + + .../rockchip/rk3588-firefly-core-3588j.dtsi | 4 + + .../rockchip/rk3588-firefly-itx-3588j.dts | 2 +- + .../rk3588-friendlyelec-cm3588-nas.dts | 2 +- + .../rockchip/rk3588-friendlyelec-cm3588.dtsi | 8 + + .../src/arm64/rockchip/rk3588-h96-max-v58.dts | 30 ++- + .../src/arm64/rockchip/rk3588-jaguar.dts | 224 +++++++++++++++++- + .../src/arm64/rockchip/rk3588-nanopc-t6.dtsi | 6 +- + .../src/arm64/rockchip/rk3588-ok3588-c.dts | 4 + + .../rockchip/rk3588-orangepi-5-compact.dtsi | 11 +- + .../arm64/rockchip/rk3588-orangepi-5-max.dts | 67 +++++- + .../arm64/rockchip/rk3588-orangepi-5-plus.dts | 56 ++++- + .../src/arm64/rockchip/rk3588-orangepi-5.dtsi | 6 +- + .../src/arm64/rockchip/rk3588-quartzpro64.dts | 6 +- + .../src/arm64/rockchip/rk3588-rock-5-itx.dts | 53 +++++ + .../src/arm64/rockchip/rk3588-rock-5b.dts | 83 ++++++- + .../arm64/rockchip/rk3588-tiger-haikou.dts | 4 +- + .../src/arm64/rockchip/rk3588-tiger.dtsi | 5 +- + .../src/arm64/rockchip/rk3588-toybrick-x0.dts | 4 + + .../src/arm64/rockchip/rk3588-turing-rk1.dtsi | 6 + + dts/upstream/src/arm64/rockchip/rk3588j.dtsi | 53 ++--- + .../src/arm64/rockchip/rk3588s-coolpi-4b.dts | 31 ++- + .../src/arm64/rockchip/rk3588s-evb1-v10.dts | 6 +- + .../arm64/rockchip/rk3588s-gameforce-ace.dts | 6 +- + .../rockchip/rk3588s-indiedroid-nova.dts | 8 +- + .../arm64/rockchip/rk3588s-khadas-edge2.dts | 4 + + .../src/arm64/rockchip/rk3588s-nanopi-r6.dtsi | 6 +- + .../src/arm64/rockchip/rk3588s-odroid-m2.dts | 6 +- + .../arm64/rockchip/rk3588s-orangepi-5.dtsi | 16 +- + .../src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +- + .../src/arm64/rockchip/rk3588s-rock-5c.dts | 42 +++- + 67 files changed, 1569 insertions(+), 196 deletions(-) + +diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi +index 1edfd643b25..a334ef0629d 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi ++++ b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi +@@ -31,7 +31,7 @@ + }; + + vcc3v3_btreg: vcc3v3-btreg { +- compatible = "regulator-gpio"; ++ compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; +@@ -39,7 +39,6 @@ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +- states = <3300000 0x0>; + }; + + vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod { +diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi b/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi +index 80db778c968..b60e68faa83 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi ++++ b/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi +@@ -26,5 +26,5 @@ + }; + + &vcc3v3_btreg { +- enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + }; +diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts b/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts +index 165d09ccb94..5886b802c52 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts ++++ b/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts +@@ -39,5 +39,5 @@ + }; + + &vcc3v3_btreg { +- enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts +index 1a59e8b1dc4..91cf4cd3fae 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts ++++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts +@@ -154,6 +154,8 @@ + }; + + &i2c3 { ++ status = "okay"; ++ + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; +diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi +index e80412abec0..142244d5270 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi ++++ b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi +@@ -325,10 +325,6 @@ + }; + }; + +-&i2c3 { +- status = "okay"; +-}; +- + &i2s0_8ch { + rockchip,trcm-sync-tx-only; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts b/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts +index 629121de5a1..5e718194899 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts +@@ -147,7 +147,7 @@ + + &pwm5 { + status = "okay"; +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin_pull_down>; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts +index a94114fb7cc..96c27fc5005 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts +@@ -274,13 +274,13 @@ + + &pwm0 { + pinctrl-0 = <&pwm0_pin_pull_up>; +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + status = "okay"; + }; + + &pwm1 { + pinctrl-0 = <&pwm1_pin_pull_up>; +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts +index 6310b58de77..a4bdd87d072 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts +@@ -428,10 +428,18 @@ + status = "okay"; + }; + ++&u2phy_otg { ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; + ++&usb20_otg { ++ status = "okay"; ++}; ++ + &usbdrd3 { + dr_mode = "host"; + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi +index b169be06d4d..c8eb5481f43 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi +@@ -603,7 +603,7 @@ + }; + + &pwm2 { +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts +index 947bbd62a6b..70979079923 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts +@@ -149,8 +149,15 @@ + }; + }; + ++&gmac { ++ status = "okay"; ++}; ++ + &hdmi { +- ddc-i2c-bus = <&i2c3>; ++ status = "okay"; ++}; ++ ++&hdmi_sound { + status = "okay"; + }; + +@@ -186,9 +193,22 @@ + }; + }; + +-&i2c6 { ++&i2c7 { ++ eeprom@50 { ++ reg = <0x50>; ++ compatible = "atmel,24c01"; ++ pagesize = <8>; ++ size = <128>; ++ vcc-supply = <&vcc3v3_baseboard>; ++ }; ++}; ++ ++&i2s0 { ++ status = "okay"; ++}; ++ ++&i2s2 { + status = "okay"; +- clock-frequency = <400000>; + }; + + &pcie_phy { +@@ -292,14 +312,6 @@ + status = "okay"; + }; + +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- + &vopb { + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi +index 995b30a7aae..587e89d7fc5 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi +@@ -60,16 +60,6 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc5v0_host: regulator-vcc5v0-host { +- compatible = "regulator-fixed"; +- gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -183,7 +173,6 @@ + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x10>; + rx_delay = <0x23>; +- status = "okay"; + }; + + &gpu { +@@ -389,6 +378,14 @@ + }; + }; + ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++}; ++ ++&i2c6 { ++ clock-frequency = <400000>; ++}; ++ + &i2c7 { + status = "okay"; + clock-frequency = <400000>; +@@ -439,7 +436,6 @@ + pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; +- status = "okay"; + }; + + /* +@@ -521,10 +517,10 @@ + }; + }; + +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { ++ usb { ++ cy3304_reset: cy3304-reset { + rockchip,pins = +- <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ <4 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + +@@ -589,11 +585,6 @@ + u2phy1_otg: otg-port { + status = "okay"; + }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; + }; + + &usbdrd3_1 { +@@ -603,12 +594,27 @@ + &usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +-}; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cy3304_reset>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb4b4,6502", "usb4b4,6506"; ++ reg = <1>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; ++ vdd-supply = <&vcc1v2_phy>; ++ vdd2-supply = <&vcc3v3_sys>; + +-&usb_host1_ehci { +- status = "okay"; +-}; ++ }; + +-&usb_host1_ohci { +- status = "okay"; ++ hub_3_0: hub@2 { ++ compatible = "usb4b4,6500", "usb4b4,6504"; ++ reg = <2>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; ++ vdd-supply = <&vcc1v2_phy>; ++ vdd2-supply = <&vcc3v3_sys>; ++ }; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts +index e2e9279fa26..8e3858cf988 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts +@@ -112,7 +112,7 @@ + + &i2c1 { + es8388: es8388@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + #sound-dai-cells = <0>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi +index 541dca12bf1..046dbe32901 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi +@@ -43,7 +43,7 @@ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; +- clock-names = "lpo"; ++ clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi +index 26c3559d6a6..7f1ffd6003f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi +@@ -404,9 +404,10 @@ + + uart3: serial@ffa08000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xffa08000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; +- reg = <0x0 0xffa08000 0x0 0x100>; ++ interrupts = ; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi +index a4835147176..e7ba477e75f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi +@@ -775,7 +775,7 @@ + rockchip,default-sample-phase = <90>; + status = "okay"; + +- sdio-wifi@1 { ++ wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi +index 2d3ae154482..3613661417b 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi +@@ -9,6 +9,8 @@ + #include "rk3566.dtsi" + + / { ++ chassis-type = "tablet"; ++ + aliases { + mmc0 = &sdhci; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts +index 98e75df8b15..3c127c5c260 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts +@@ -265,8 +265,12 @@ + }; + + &gmac1 { +- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; +- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, ++ <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>, ++ <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts +index 24928a12944..5707321a114 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts +@@ -173,8 +173,12 @@ + }; + + &gmac1 { +- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; +- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, ++ <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>, ++ <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts +index 53e71528e4c..6224d72813e 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts +@@ -636,6 +636,7 @@ + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; ++ vcc-supply = <&vcc_1v8>; + }; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi b/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi +index 00c479aa187..a28b4af10d1 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi +@@ -486,9 +486,12 @@ + &sdhci { + bus-width = <8>; + max-frequency = <200000000>; ++ mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; +- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +index 7bd32d230ad..b80d628c426 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +@@ -619,6 +619,8 @@ + bus-width = <8>; + max-frequency = <200000000>; + non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts +index ac79140a9ec..44cfdfeed66 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts +@@ -778,20 +778,6 @@ + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk809 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; +- vbat-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- /* vddio comes from regulator on module, use IO bank voltage instead */ +- }; + }; + + &uart2 { +diff --git a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi +index e5539062911..fd2214b6fad 100644 +--- a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi +@@ -174,6 +174,18 @@ + method = "smc"; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ scmi_shmem: shmem@10f000 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x0 0x0010f000 0x0 0x100>; ++ no-map; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , +@@ -199,19 +211,6 @@ + #clock-cells = <0>; + }; + +- sram@10f000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x0010f000 0x0 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x0010f000 0x100>; +- +- scmi_shmem: sram@0 { +- compatible = "arm,scmi-shmem"; +- reg = <0x0 0x100>; +- }; +- }; +- + sata1: sata@fc400000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; +@@ -284,6 +283,18 @@ + mbi-alias = <0x0 0xfd410000>; + mbi-ranges = <296 24>; + msi-controller; ++ ranges; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ dma-noncoherent; ++ ++ its: msi-controller@fd440000 { ++ compatible = "arm,gic-v3-its"; ++ reg = <0x0 0xfd440000 0 0x20000>; ++ dma-noncoherent; ++ msi-controller; ++ #msi-cells = <1>; ++ }; + }; + + usb_host0_ehci: usb@fd800000 { +@@ -957,7 +968,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; +- msi-map = <0x0 &gic 0x0 0x1000>; ++ msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; +@@ -1032,6 +1043,11 @@ + status = "disabled"; + }; + ++ /* ++ * Testing showed that the HWRNG found in RK3566 produces unacceptably ++ * low quality of random data, so the HWRNG isn't enabled for all RK356x ++ * SoC variants despite its presence. ++ */ + rng: rng@fe388000 { + compatible = "rockchip,rk3568-rng"; + reg = <0x0 0xfe388000 0x0 0x4000>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts b/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts +index 7c7331936a7..314067ba6f3 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include "rk3576.dtsi" + +@@ -26,6 +27,17 @@ + stdout-path = "serial0:1500000n8"; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds: leds { + compatible = "gpio-leds"; + +@@ -182,8 +194,7 @@ + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk +- ð0m0_rgmii_bus +- ðm0_clk0_25m_out>; ++ ð0m0_rgmii_bus>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +@@ -214,6 +225,26 @@ + status = "okay"; + }; + ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdptxphy { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + +@@ -579,7 +610,7 @@ + reg = <0x51>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; +- interrupts = ; ++ interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; +@@ -656,3 +687,18 @@ + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts +index 782ca000a64..e368691fd28 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include "rk3576.dtsi" + + / { +@@ -57,6 +58,17 @@ + }; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds: leds { + compatible = "gpio-leds"; + +@@ -270,6 +282,26 @@ + status = "okay"; + }; + ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdptxphy { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + +@@ -729,3 +761,18 @@ + dr_mode = "host"; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi +index 29b47799849..3824242f8ae 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi +@@ -111,7 +111,7 @@ + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <120>; +@@ -124,7 +124,7 @@ + reg = <0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -135,7 +135,7 @@ + reg = <0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -146,7 +146,7 @@ + reg = <0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -157,7 +157,7 @@ + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <320>; +@@ -170,7 +170,7 @@ + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -181,7 +181,7 @@ + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -192,7 +192,7 @@ + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -393,6 +393,11 @@ + }; + }; + ++ display_subsystem: display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vop_out>; ++ }; ++ + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; +@@ -620,6 +625,11 @@ + }; + }; + ++ hdptxphy_grf: syscon@26032000 { ++ compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; ++ reg = <0x0 0x26032000 0x0 0x100>; ++ }; ++ + vo1_grf: syscon@26036000 { + compatible = "rockchip,rk3576-vo1-grf", "syscon"; + reg = <0x0 0x26036000 0x0 0x100>; +@@ -922,7 +932,7 @@ + gpu: gpu@27800000 { + compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; + reg = <0x0 0x27800000 0x0 0x200000>; +- assigned-clocks = <&scmi_clk CLK_GPU>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <198000000>; + clocks = <&cru CLK_GPU>; + clock-names = "core"; +@@ -937,6 +947,109 @@ + status = "disabled"; + }; + ++ vop: vop@27d00000 { ++ compatible = "rockchip,rk3576-vop"; ++ reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; ++ reg-names = "vop", "gamma-lut"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "sys", ++ "vp0", ++ "vp1", ++ "vp2"; ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VP0>, ++ <&cru DCLK_VP1>, ++ <&cru DCLK_VP2>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2"; ++ iommus = <&vop_mmu>; ++ power-domains = <&power RK3576_PD_VOP>; ++ rockchip,grf = <&sys_grf>; ++ rockchip,pmu = <&pmu>; ++ status = "disabled"; ++ ++ vop_out: ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vp0: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ vp1: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ vp2: port@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ }; ++ }; ++ ++ vop_mmu: iommu@27d07e00 { ++ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ power-domains = <&power RK3576_PD_VOP>; ++ status = "disabled"; ++ }; ++ ++ hdmi: hdmi@27da0000 { ++ compatible = "rockchip,rk3576-dw-hdmi-qp"; ++ reg = <0x0 0x27da0000 0x0 0x20000>; ++ clocks = <&cru PCLK_HDMITX0>, ++ <&cru CLK_HDMITX0_EARC>, ++ <&cru CLK_HDMITX0_REF>, ++ <&cru MCLK_SAI6_8CH>, ++ <&cru CLK_HDMITXHDP>, ++ <&cru HCLK_VO0_ROOT>; ++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "avp", "cec", "earc", "main", "hpd"; ++ phys = <&hdptxphy>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; ++ power-domains = <&power RK3576_PD_VO0>; ++ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; ++ reset-names = "ref", "hdp"; ++ rockchip,grf = <&ioc_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ + qos_hdcp1: qos@27f02000 { + compatible = "rockchip,rk3576-qos", "syscon"; + reg = <0x0 0x27f02000 0x0 0x20>; +@@ -1221,6 +1334,42 @@ + }; + }; + ++ ufshc: ufshc@2a2d0000 { ++ compatible = "rockchip,rk3576-ufshc"; ++ reg = <0x0 0x2a2d0000 0x0 0x10000>, ++ <0x0 0x2b040000 0x0 0x10000>, ++ <0x0 0x2601f000 0x0 0x1000>, ++ <0x0 0x2603c000 0x0 0x1000>, ++ <0x0 0x2a2e0000 0x0 0x10000>; ++ reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; ++ clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, ++ <&cru CLK_REF_UFS_CLKOUT>; ++ clock-names = "core", "pclk", "pclk_mphy", "ref_out"; ++ assigned-clocks = <&cru CLK_REF_OSC_MPHY>; ++ assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; ++ interrupts = ; ++ power-domains = <&power RK3576_PD_USB>; ++ pinctrl-0 = <&ufs_refclk>; ++ pinctrl-names = "default"; ++ resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, ++ <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; ++ reset-names = "biu", "sys", "ufs", "grf"; ++ reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; ++ status = "disabled"; ++ }; ++ ++ sfc1: spi@2a300000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0x2a300000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ power-domains = <&power RK3576_PD_SDGMAC>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + sdmmc: mmc@2a310000 { + compatible = "rockchip,rk3576-dw-mshc"; + reg = <0x0 0x2a310000 0x0 0x4000>; +@@ -1260,6 +1409,18 @@ + status = "disabled"; + }; + ++ sfc0: spi@2a340000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0x2a340000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ power-domains = <&power RK3576_PD_NVM>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; +@@ -1795,6 +1956,19 @@ + status = "disabled"; + }; + ++ hdptxphy: hdmiphy@2b000000 { ++ compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0x2b000000 0x0 0x2000>; ++ clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; ++ clock-names = "ref", "apb"; ++ resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, ++ <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; ++ reset-names = "apb", "init", "cmn", "lane"; ++ rockchip,grf = <&hdptxphy_grf>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + sram: sram@3ff88000 { + compatible = "mmio-sram"; + reg = <0x0 0x3ff88000 0x0 0x78000>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi +index a3138d2d384..e44125e9a8f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi +@@ -114,6 +114,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts +index 08f09053a06..ae9274365be 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -33,6 +34,17 @@ + "Headphone", "Headphones"; + }; + ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -164,6 +176,30 @@ + status = "okay"; + }; + ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -258,6 +294,10 @@ + }; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ + /* phy1 - right ethernet port */ + &pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; +@@ -268,6 +308,22 @@ + &pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x300000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ device_type = "pci"; ++ bus-range = <0x30 0x3f>; ++ ++ wifi: wifi@0,0 { ++ compatible = "pci14e4,449d"; ++ reg = <0x310000 0 0 0 0>; ++ clocks = <&hym8563>; ++ clock-names = "lpo"; ++ }; ++ }; + }; + + /* phy0 - left ethernet port */ +@@ -286,6 +342,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -723,3 +783,18 @@ + dr_mode = "host"; + status = "okay"; + }; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +index 2623afa7963..c52af310c70 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +@@ -358,11 +358,6 @@ + }; + + firmware { +- optee: optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; +@@ -382,6 +377,22 @@ + }; + }; + ++ hdmi0_sound: hdmi0-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi0"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi0>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s5_8ch>; ++ }; ++ }; ++ + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; +@@ -428,16 +439,15 @@ + #clock-cells = <0>; + }; + +- pmu_sram: sram@10f000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x0010f000 0x0 0x100>; +- ranges = <0 0x0 0x0010f000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; + +- scmi_shmem: sram@0 { ++ scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; +- reg = <0x0 0x100>; ++ reg = <0x0 0x0010f000 0x0 0x100>; ++ no-map; + }; + }; + +@@ -864,7 +874,7 @@ + }; + }; + /* These power domains are grouped by VD_GPU */ +- power-domain@RK3588_PD_GPU { ++ pd_gpu: power-domain@RK3588_PD_GPU { + reg = ; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, +@@ -1261,14 +1271,16 @@ + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, +- <&cru PCLK_VOP_ROOT>; ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", +- "pclk_vop"; ++ "pclk_vop", ++ "pll_hdmiphy0"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; +@@ -1318,6 +1330,21 @@ + status = "disabled"; + }; + ++ spdif_tx2: spdif-tx@fddb0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfddb0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; ++ dma-names = "tx"; ++ dmas = <&dmac1 6>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO0>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; +@@ -1335,6 +1362,21 @@ + status = "disabled"; + }; + ++ spdif_tx3: spdif-tx@fdde0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfdde0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF3_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; ++ dma-names = "tx"; ++ dmas = <&dmac1 7>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO1>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; +@@ -1385,7 +1427,7 @@ + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; +- phys = <&hdptxphy_hdmi0>; ++ phys = <&hdptxphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; +@@ -1394,6 +1436,7 @@ + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; + status = "disabled"; + + ports { +@@ -2024,12 +2067,47 @@ + status = "disabled"; + }; + ++ spdif_tx0: spdif-tx@fe4e0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe4e0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF0_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; ++ dma-names = "tx"; ++ dmas = <&dmac0 5>; ++ interrupts = ; ++ pinctrl-0 = <&spdif0m0_tx>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spdif_tx1: spdif-tx@fe4f0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe4f0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF1_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; ++ dma-names = "tx"; ++ dmas = <&dmac1 5>; ++ interrupts = ; ++ pinctrl-0 = <&spdif1m0_tx>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = ; + interrupt-controller; ++ dma-noncoherent; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; +@@ -2041,6 +2119,7 @@ + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; +@@ -2048,6 +2127,7 @@ + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; +@@ -2815,11 +2895,12 @@ + #dma-cells = <1>; + }; + +- hdptxphy_hdmi0: phy@fed60000 { ++ hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts +index 9d525c8ff72..9eda6972266 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts +@@ -129,7 +129,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts +index bc6b43a7715..6dc10da5215 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts +@@ -166,7 +166,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +index 71ed680621b..cc37f082ade 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +@@ -277,6 +277,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi +index 5e72d0eff0e..8a783dc64c0 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi +@@ -126,6 +126,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + led_user_en: led_user_en { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi +index 7125790bbed..08920344a4b 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi +@@ -4,12 +4,24 @@ + */ + + #include ++#include + + / { + chosen { + stdout-path = "serial2:1500000n8"; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; +@@ -81,6 +93,26 @@ + status = "okay"; + }; + ++&hdmi1 { ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ + &i2c6 { + status = "okay"; + +@@ -275,3 +307,18 @@ + &usb_host2_xhci { + status = "okay"; + }; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts +index ba49f0bbaac..8e912da299a 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts +@@ -132,6 +132,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; +@@ -364,7 +375,27 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi1 { ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { + status = "okay"; + }; + +@@ -441,7 +472,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -519,6 +550,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + audio { + hp_detect: headphone-detect { +@@ -1371,11 +1406,11 @@ + status = "okay"; + }; + +-&vop_mmu { ++&vop { + status = "okay"; + }; + +-&vop { ++&vop_mmu { + status = "okay"; + }; + +@@ -1385,3 +1420,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi +index 840b638af1c..099edb3fd0f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi +@@ -7,6 +7,46 @@ + #include "rk3588-extra-pinctrl.dtsi" + + / { ++ hdmi1_sound: hdmi1-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi1"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi1>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s6_8ch>; ++ }; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* ++ * The 4k HDMI capture controller works only with 32bit ++ * phys addresses and doesn't support IOMMU. HDMI RX CMA ++ * must be reserved below 4GB. ++ * The size of 160MB was determined as follows: ++ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB ++ * To ensure sufficient support for practical use-cases, ++ * we doubled the 66MB value. ++ */ ++ hdmi_receiver_cma: hdmi-receiver-cma { ++ compatible = "shared-dma-pool"; ++ alloc-ranges = <0x0 0x0 0x0 0xffffffff>; ++ size = <0x0 (160 * 0x100000)>; /* 160MiB */ ++ alignment = <0x0 0x40000>; /* 64K */ ++ no-map; ++ status = "disabled"; ++ }; ++ }; ++ + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; +@@ -67,6 +107,26 @@ + }; + }; + ++ hdptxphy1_grf: syscon@fd5e4000 { ++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; ++ reg = <0x0 0xfd5e4000 0x0 0x100>; ++ }; ++ ++ spdif_tx5: spdif-tx@fddb8000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfddb8000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; ++ dma-names = "tx"; ++ dmas = <&dmac1 22>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO0>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; +@@ -84,6 +144,21 @@ + status = "disabled"; + }; + ++ spdif_tx4: spdif-tx@fdde8000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfdde8000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF4_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; ++ dma-names = "tx"; ++ dmas = <&dmac1 8>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO1>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; +@@ -135,6 +210,79 @@ + status = "disabled"; + }; + ++ hdmi1: hdmi@fdea0000 { ++ compatible = "rockchip,rk3588-dw-hdmi-qp"; ++ reg = <0x0 0xfdea0000 0x0 0x20000>; ++ clocks = <&cru PCLK_HDMITX1>, ++ <&cru CLK_HDMITX1_EARC>, ++ <&cru CLK_HDMITX1_REF>, ++ <&cru MCLK_I2S6_8CH_TX>, ++ <&cru CLK_HDMIHDP1>, ++ <&cru HCLK_VO1>; ++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "avp", "cec", "earc", "main", "hpd"; ++ phys = <&hdptxphy1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; ++ reset-names = "ref", "hdp"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi1_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi1_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ hdmi_receiver: hdmi_receiver@fdee0000 { ++ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; ++ reg = <0x0 0xfdee0000 0x0 0x6000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "cec", "hdmi", "dma"; ++ clocks = <&cru ACLK_HDMIRX>, ++ <&cru CLK_HDMIRX_AUD>, ++ <&cru CLK_CR_PARA>, ++ <&cru PCLK_HDMIRX>, ++ <&cru CLK_HDMIRX_REF>, ++ <&cru PCLK_S_HDMIRX>, ++ <&cru HCLK_VO1>; ++ clock-names = "aclk", ++ "audio", ++ "cr_para", ++ "pclk", ++ "ref", ++ "hclk_s_hdmirx", ++ "hclk_vo1"; ++ memory-region = <&hdmi_receiver_cma>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, ++ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; ++ reset-names = "axi", "apb", "ref", "biu"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo1-grf = <&vo1_grf>; ++ status = "disabled"; ++ }; ++ + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; +@@ -398,6 +546,23 @@ + }; + }; + ++ hdptxphy1: phy@fed70000 { ++ compatible = "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0xfed70000 0x0 0x2000>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; ++ clock-names = "ref", "apb"; ++ #clock-cells = <0>; ++ #phy-cells = <0>; ++ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, ++ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, ++ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, ++ <&cru SRST_HDPTX1_LCPLL>; ++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", ++ "lcpll"; ++ rockchip,grf = <&hdptxphy1_grf>; ++ status = "disabled"; ++ }; ++ + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; +@@ -449,3 +614,24 @@ + status = "disabled"; + }; + }; ++ ++&vop { ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>, ++ <&hdptxphy1>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop", ++ "pll_hdmiphy0", ++ "pll_hdmiphy1"; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi +index 39005131738..4331cdc70f9 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi +@@ -205,6 +205,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + led_rgb_b: led-rgb-b { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi +index 42c523b553c..80e16ea4154 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi +@@ -108,6 +108,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &sdhci { + bus-width = <8>; + no-sdio; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts +index 2be5251d3e3..e086114c763 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts +@@ -337,7 +337,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts +index b3a04ca370b..8171fbfd819 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts +@@ -335,7 +335,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi +index e3a9598b99f..af431fdcbea 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi +@@ -222,6 +222,10 @@ + compatible = "realtek,rt5616"; + reg = <0x1b>; + #sound-dai-cells = <0>; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; + }; + }; + +@@ -256,6 +260,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + gpio-leds { + led_sys_pin: led-sys-pin { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts +index 4791b77f357..73d8ce4fde2 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts +@@ -140,6 +140,24 @@ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; ++ ++ spdif_dit: spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ }; ++ ++ spdif_sound: spdif-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif_tx0>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; + }; + + &combphy0_ps { +@@ -207,7 +225,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -316,6 +334,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -400,6 +422,12 @@ + status = "okay"; + }; + ++&spdif_tx0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif0m1_tx>; ++ status = "okay"; ++}; ++ + &spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +index 7f457ab7801..9fceea6c139 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +@@ -303,7 +303,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -333,6 +333,56 @@ + }; + }; + ++ typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio4>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cc_int1>; ++ vbus-supply = <&vcc_5v0_usb_c1>; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USBC-1 P11"; ++ power-role = "source"; ++ self-powered; ++ source-pdos = ++ ; ++ vbus-supply = <&vcc_5v0_usb_c1>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usbc0_hs: endpoint { ++ remote-endpoint = <&usb_host0_xhci_drd_sw>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usbc0_ss: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_ss>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ usbc0_sbu: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_sbu>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; +@@ -394,6 +444,56 @@ + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; + ++ typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio4>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cc_int2>; ++ vbus-supply = <&vcc_5v0_usb_c2>; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USBC-2 P12"; ++ power-role = "source"; ++ self-powered; ++ source-pdos = ++ ; ++ vbus-supply = <&vcc_5v0_usb_c2>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usbc1_hs: endpoint { ++ remote-endpoint = <&usb_host1_xhci_drd_sw>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usbc1_ss: endpoint { ++ remote-endpoint = <&usbdp_phy1_typec_ss>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ usbc1_sbu: endpoint { ++ remote-endpoint = <&usbdp_phy1_typec_sbu>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; +@@ -451,6 +551,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + emmc { + emmc_reset: emmc-reset { +@@ -483,6 +587,26 @@ + rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; + }; + }; ++ ++ usb3 { ++ cc_int1: cc-int1 { ++ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ cc_int2: cc-int2 { ++ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ typec0_sbu_dc_pins: typec0-sbu-dc-pins { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>, ++ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ typec1_sbu_dc_pins: typec1-sbu-dc-pins { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, ++ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; + }; + + &saradc { +@@ -850,6 +974,24 @@ + status = "okay"; + }; + ++/* USB-C P11 connector */ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++/* USB-C P12 connector */ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -892,6 +1034,56 @@ + status = "okay"; + }; + ++/* Type-C on P11 */ ++&usbdp_phy0 { ++ orientation-switch; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec0_sbu_dc_pins>; ++ sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ ++ sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_typec_ss: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_ss>; ++ }; ++ ++ usbdp_phy0_typec_sbu: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&usbc0_sbu>; ++ }; ++ }; ++}; ++ ++/* Type-C on P12 */ ++&usbdp_phy1 { ++ orientation-switch; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec1_sbu_dc_pins>; ++ sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ ++ sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy1_typec_ss: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc1_ss>; ++ }; ++ ++ usbdp_phy1_typec_sbu: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&usbc1_sbu>; ++ }; ++ }; ++}; ++ + /* host0 on P10 USB-A */ + &usb_host0_ehci { + status = "okay"; +@@ -902,6 +1094,36 @@ + status = "okay"; + }; + ++/* host0 on P11 USB-C */ ++&usb_host0_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usb_host0_xhci_drd_sw: endpoint { ++ remote-endpoint = <&usbc0_hs>; ++ }; ++ }; ++}; ++ ++/* host1 on P12 USB-C */ ++&usb_host1_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usb_host1_xhci_drd_sw: endpoint { ++ remote-endpoint = <&usbc1_hs>; ++ }; ++ }; ++}; ++ + /* host1 on M.2 E-key */ + &usb_host1_ehci { + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi +index cb350727d11..bbe500cc924 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi +@@ -360,7 +360,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -565,6 +565,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts +index 1c0851b45eb..fbe1d5c06d9 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts +@@ -312,6 +312,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi +index 87090cb9802..f748c6f760d 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi +@@ -7,9 +7,6 @@ + #include "rk3588-orangepi-5.dtsi" + + / { +- model = "Xunlong Orange Pi 5 Max"; +- compatible = "xunlong,orangepi-5-max", "rockchip,rk3588"; +- + vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -62,18 +59,12 @@ + + &led_blue_pwm { + /* PWM_LED1 */ +- pwms = <&pwm4 0 25000 0>; + status = "okay"; + }; + +-&led_green_pwm { +- /* PWM_LED2 */ +- pwms = <&pwm5 0 25000 0>; +-}; +- + /* phy2 */ + &pcie2x1l1 { +- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_eth>; + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts +index ce44549babf..8b1d35760c3 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts +@@ -21,6 +21,17 @@ + }; + }; + }; ++ ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; + }; + + &hdmi0 { +@@ -39,10 +50,57 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { + status = "okay"; + }; + ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ ++&led_blue_pwm { ++ pwms = <&pwm4 0 25000 0>; ++}; ++ ++&led_green_pwm { ++ pwms = <&pwm5 0 25000 0>; ++}; ++ + &pinctrl { + + usb { +@@ -58,3 +116,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +index 255e33c5dbd..121e4d1c3fa 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +@@ -26,6 +26,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; +@@ -113,6 +124,10 @@ + status = "okay"; + }; + ++&hdmi0_sound { ++ status = "okay"; ++}; ++ + &hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; +@@ -125,7 +140,31 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi1 { ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { + status = "okay"; + }; + +@@ -189,6 +228,14 @@ + }; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ + &led_blue_gpio { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +@@ -342,3 +389,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi +index a98e804a094..91d56c34a1e 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi +@@ -276,7 +276,7 @@ + + /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc_3v3_s0>; +@@ -348,6 +348,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts +index 088cfade6f6..78aaa6635b5 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts +@@ -311,7 +311,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; +@@ -347,6 +347,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts +index 2a059020946..7de17117df7 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include "dt-bindings/usb/pd.h" + #include "rk3588.dtsi" + +@@ -72,6 +73,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; +@@ -261,6 +273,28 @@ + status = "okay"; + }; + ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -564,6 +598,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + rtc_int: rtc-int { +@@ -1208,3 +1246,18 @@ + rockchip,dp-lane-mux = <2 3>; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +index d597112f1d5..d22068475c5 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +@@ -49,6 +49,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -220,7 +231,48 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdmi_receiver_cma { ++ status = "okay"; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { + status = "okay"; + }; + +@@ -318,6 +370,14 @@ + }; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ + &package_thermal { + polling-delay = <1000>; + +@@ -376,7 +436,17 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -891,11 +961,11 @@ + status = "okay"; + }; + +-&vop_mmu { ++&vop { + status = "okay"; + }; + +-&vop { ++&vop_mmu { + status = "okay"; + }; + +@@ -905,3 +975,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +index 3187b4918a3..a3d8ff64783 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +@@ -189,7 +189,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -310,8 +310,10 @@ + status = "okay"; + }; + ++/* DB9 RS232/RS485 when SW2 in "UART1" mode */ + &uart5 { + rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; ++ status = "okay"; + }; + + &usbdp_phy0 { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +index e8fa449517c..c4933a08dd1 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +@@ -173,7 +173,6 @@ + + &i2c2 { + pinctrl-0 = <&i2c2m3_xfer>; +- status = "okay"; + }; + + &i2c2m3_xfer { +@@ -336,6 +335,10 @@ + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + emmc { + emmc_reset: emmc-reset { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts +index 3cbee5b9747..5a428e00ab9 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts +@@ -289,6 +289,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi +index 6bc46734cc1..60ad272982a 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi +@@ -214,6 +214,8 @@ + }; + + &package_thermal { ++ polling-delay = <1000>; ++ + trips { + package_active1: trip-active1 { + temperature = <45000>; +@@ -287,6 +289,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + fan { + fan_int: fan-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi +index bce72bac450..3045cb3bd68 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi +@@ -11,20 +11,15 @@ + compatible = "operating-points-v2"; + opp-shared; + +- opp-1416000000 { +- opp-hz = /bits/ 64 <1416000000>; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <887500 887500 950000>; +- clock-latency-ns = <40000>; +- }; +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <937500 937500 950000>; ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <775000 775000 950000>; + clock-latency-ns = <40000>; + }; + }; +@@ -33,9 +28,14 @@ + compatible = "operating-points-v2"; + opp-shared; + ++ opp-1200000000{ ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <750000 750000 950000>; ++ opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { +@@ -43,25 +43,20 @@ + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <875000 875000 950000>; +- clock-latency-ns = <40000>; +- }; +- opp-2016000000 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-microvolt = <950000 950000 950000>; +- clock-latency-ns = <40000>; +- }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + ++ opp-1200000000{ ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <750000 750000 950000>; ++ opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { +@@ -69,16 +64,6 @@ + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <875000 875000 950000>; +- clock-latency-ns = <40000>; +- }; +- opp-2016000000 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-microvolt = <950000 950000 950000>; +- clock-latency-ns = <40000>; +- }; + }; + + gpu_opp_table: opp-table { +@@ -104,10 +89,6 @@ + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>; + }; +- opp-850000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <787500 787500 850000>; +- }; + }; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts +index 9c394f733bb..8b717c4017a 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts +@@ -236,7 +236,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -361,6 +361,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -429,7 +433,7 @@ + }; + + &pwm13 { +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + pinctrl-0 = <&pwm13m2_pins>; + status = "okay"; + }; +@@ -803,6 +807,14 @@ + status = "okay"; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -832,6 +844,16 @@ + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; + }; + ++&usbdp_phy0 { ++ /* ++ * USBDP PHY0 is wired to a USB3 Type-A OTG connector. Additionally ++ * the differential pairs 0+1 and the aux channel are wired to a ++ * mini DP connector. ++ */ ++ rockchip,dp-lane-mux = <0 1>; ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -840,6 +862,11 @@ + status = "okay"; + }; + ++&usb_host0_xhci { ++ extcon = <&u2phy0>; ++ status = "okay"; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts +index bc4077575be..9f4aca9c2e3 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts +@@ -242,7 +242,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -340,6 +340,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + audio { + hp_detect: headphone-detect { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts +index 812bba0aef1..873a2bd6a6d 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts +@@ -611,7 +611,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -675,6 +675,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + audio-amplifier { + headphone_amplifier_en: headphone-amplifier-en { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +index 4a3aa80f222..4189a88ecf4 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +@@ -278,7 +278,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -412,7 +412,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -455,6 +455,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + bluetooth-pins { + bt_reset: bt-reset { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts +index ac48e7fd392..88a5e822ed1 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts +@@ -233,6 +233,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + vdd_sd { + vdd_sd_en: vdd-sd-en { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi +index d2eddea1840..fbf062ec3bf 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi +@@ -251,7 +251,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -359,6 +359,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + gpio-key { + key1_pin: key1-pin { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts +index 8f034c6d494..a72063c5514 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts +@@ -264,7 +264,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -433,6 +433,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + lcd { + lcd_pwren: lcd-pwren { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi +index d86aeacca23..4fedc50cce8 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi +@@ -197,7 +197,11 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdptxphy0 { + status = "okay"; + }; + +@@ -268,7 +272,7 @@ + status = "okay"; + + es8388: audio-codec@10 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + AVDD-supply = <&vcc_3v3_s0>; +@@ -355,6 +359,10 @@ + status = "okay"; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ + &mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +@@ -365,6 +373,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +index 70a43432bdc..f894742b1eb 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +@@ -334,7 +334,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -359,6 +359,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + io_led: io-led { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts +index 9b14d5383cd..dd7317bab61 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts +@@ -68,10 +68,10 @@ + }; + }; + +- fan { ++ fan: fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; +- cooling-levels = <0 64 128 192 255>; ++ cooling-levels = <0 24 44 64 128 192 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 10000 0>; + }; +@@ -278,7 +278,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -417,6 +417,36 @@ + }; + }; + ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_2_perstn_m0>; +@@ -425,6 +455,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + led_pins: led-pins { +@@ -843,6 +877,8 @@ + }; + + &tsadc { ++ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; + }; + +-- +2.49.0 + diff --git a/Add-pmem-node-for-preserving-distro-ISO-s.patch b/Add-pmem-node-for-preserving-distro-ISO-s.patch deleted file mode 100644 index bc8620b..0000000 --- a/Add-pmem-node-for-preserving-distro-ISO-s.patch +++ /dev/null @@ -1,1288 +0,0 @@ -From patchwork Fri Feb 28 08:45:24 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sughosh Ganu -X-Patchwork-Id: 2053441 -X-Patchwork-Delegate: xypron.glpk@gmx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1)) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4Z41yQ5Fkdz1yKH - for ; Fri, 28 Feb 2025 19:46:06 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 2504E81100; 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- Fri, 28 Feb 2025 00:46:12 -0800 (PST) -Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) - by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C1F13F673; - Fri, 28 Feb 2025 00:45:53 -0800 (PST) -From: Sughosh Ganu -To: u-boot@lists.denx.de -Cc: Ilias Apalodimas , - Simon Glass , Tom Rini , - Heinrich Schuchardt , - Anton Antonov , - Tobias Waldekranz , Bin Meng , - Masahisa Kojima , - Sughosh Ganu -Subject: [PATCH v6 1/6] fdt: add support for adding pmem nodes -Date: Fri, 28 Feb 2025 14:15:24 +0530 -Message-Id: <20250228084529.127823-2-sughosh.ganu@linaro.org> -X-Mailer: git-send-email 2.34.1 -In-Reply-To: <20250228084529.127823-1-sughosh.ganu@linaro.org> -References: <20250228084529.127823-1-sughosh.ganu@linaro.org> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Masahisa Kojima - -One of the problems OS installers face, when running in EFI, is that -the mounted ISO after calling ExitBootServices goes away. For some -distros this is a problem since they rely on finding some core packages -before continuing the installation. Distros have works around this -- -e.g Fedora has a special kernel command line parameter called -inst.stage2 [0]. - -ACPI has NFIT and NVDIMM support to provide ramdisks to the OS, but we -don't have anything in place for DTs. Linux and device trees have support -for persistent memory devices. So add a function that can inject a pmem -node in a DT, so we can use it when launhing OS installers with EFI. - -[0] -https://docs.redhat.com/en/documentation/red_hat_enterprise_linux/7/html/installation_guide/chap-anaconda-boot-options#sect-boot-options-installer - -Signed-off-by: Masahisa Kojima -Signed-off-by: Sughosh Ganu ---- -Changes since V5: None - - boot/fdt_support.c | 41 ++++++++++++++++++++++++++++++++++++++++- - include/fdt_support.h | 14 ++++++++++++++ - 2 files changed, 54 insertions(+), 1 deletion(-) - -diff --git a/boot/fdt_support.c b/boot/fdt_support.c -index 49efeec3681..e20b9759138 100644 ---- a/boot/fdt_support.c -+++ b/boot/fdt_support.c -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -464,7 +465,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat, - do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create); - } - --#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY - /* - * fdt_pack_reg - pack address and size array into the "reg"-suitable stream - */ -@@ -493,6 +493,7 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size, - return p - (char *)buf; - } - -+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY - #if CONFIG_NR_DRAM_BANKS > 4 - #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS - #else -@@ -2222,3 +2223,41 @@ int fdt_valid(struct fdt_header **blobp) - } - return 1; - } -+ -+int fdt_fixup_pmem_region(void *blob, ulong addr, u32 size) -+{ -+ u64 pmem_start[2] = { 0 }; -+ u64 pmem_size[2] = { 0 }; -+ char pmem_node[32] = {0}; -+ int nodeoffset, len; -+ int err; -+ u8 tmp[4 * 16]; /* Up to 64-bit address + 64-bit size */ -+ -+ if (!IS_ALIGNED(addr, SZ_2M) || !IS_ALIGNED(addr + size, SZ_2M)) { -+ printf("Start and end address must be 2MiB aligned\n"); -+ return -1; -+ } -+ -+ snprintf(pmem_node, sizeof(pmem_node), "pmem@%lx", addr); -+ nodeoffset = fdt_find_or_add_subnode(blob, 0, pmem_node); -+ if (nodeoffset < 0) -+ return nodeoffset; -+ -+ err = fdt_setprop_string(blob, nodeoffset, "compatible", "pmem-region"); -+ if (err) -+ return err; -+ err = fdt_setprop_empty(blob, nodeoffset, "volatile"); -+ if (err) -+ return err; -+ pmem_start[0] = addr; -+ pmem_size[0] = size; -+ len = fdt_pack_reg(blob, tmp, pmem_start, pmem_size, 1); -+ err = fdt_setprop(blob, nodeoffset, "reg", tmp, len); -+ if (err < 0) { -+ printf("WARNING: could not set pmem %s %s.\n", "reg", -+ fdt_strerror(err)); -+ return err; -+ } -+ -+ return 0; -+} -diff --git a/include/fdt_support.h b/include/fdt_support.h -index f0ad2e6b365..b72cd2920de 100644 ---- a/include/fdt_support.h -+++ b/include/fdt_support.h -@@ -507,4 +507,18 @@ void fdt_fixup_pstore(void *blob); - */ - int fdt_kaslrseed(void *blob, bool overwrite); - -+/** -+ * fdt_fixup_pmem_region() - add a pmem node on the device tree -+ * -+ * This functions adds/updates a pmem node to the device tree. -+ * Usually used with EFI installers to preserve installer -+ * images -+ * -+ * @blob: device tree provided by caller -+ * @addr: start address of the pmem node -+ * @size: size of the memory of the pmem node -+ * Return: 0 on success or < 0 on failure -+ */ -+int fdt_fixup_pmem_region(void *blob, ulong addr, u32 size); -+ - #endif /* ifndef __FDT_SUPPORT_H */ - -From patchwork Fri Feb 28 08:45:25 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sughosh Ganu -X-Patchwork-Id: 2053442 -X-Patchwork-Delegate: xypron.glpk@gmx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1)) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4Z41yc0t0Hz1yKH - for ; Fri, 28 Feb 2025 19:46:16 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 70EA880BA4; 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- Fri, 28 Feb 2025 00:46:16 -0800 (PST) -Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) - by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E0A503F673; - Fri, 28 Feb 2025 00:45:57 -0800 (PST) -From: Sughosh Ganu -To: u-boot@lists.denx.de -Cc: Ilias Apalodimas , - Simon Glass , Tom Rini , - Heinrich Schuchardt , - Anton Antonov , - Tobias Waldekranz , Bin Meng , - Sughosh Ganu , - Heinrich Schuchardt -Subject: [PATCH v6 2/6] efi_loader: add a function to remove memory from the - EFI map -Date: Fri, 28 Feb 2025 14:15:25 +0530 -Message-Id: <20250228084529.127823-3-sughosh.ganu@linaro.org> -X-Mailer: git-send-email 2.34.1 -In-Reply-To: <20250228084529.127823-1-sughosh.ganu@linaro.org> -References: <20250228084529.127823-1-sughosh.ganu@linaro.org> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Ilias Apalodimas - -With upcoming changes supporting pmem nodes, we need to remove the -pmem area from the EFI memory map. Add a function to do that. - -Signed-off-by: Ilias Apalodimas -Signed-off-by: Sughosh Ganu -Reviewed-by: Heinrich Schuchardt ---- -Changes since V5: None - - include/efi_loader.h | 18 ++++++++++++ - lib/efi_loader/efi_memory.c | 56 ++++++++++++++++++++++++++----------- - 2 files changed, 58 insertions(+), 16 deletions(-) - -diff --git a/include/efi_loader.h b/include/efi_loader.h -index 1d75d97ebbc..0ac00911598 100644 ---- a/include/efi_loader.h -+++ b/include/efi_loader.h -@@ -852,6 +852,24 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, - /* Adds a range into the EFI memory map */ - efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type); - -+/** -+ * efi_update_memory_map() - update the memory map by adding/removing pages -+ * -+ * @start: start address, must be a multiple of -+ * EFI_PAGE_SIZE -+ * @pages: number of pages to add -+ * @memory_type: type of memory added -+ * @overlap_conventional: region may only overlap free(conventional) -+ * memory -+ * @remove: remove memory map -+ * Return: status code -+ */ -+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type, -+ bool overlap_conventional, bool remove); -+ -+/* Remove memory from the EFI memory map */ -+efi_status_t efi_remove_memory_map(u64 start, u64 size, int memory_type); -+ - /* Called by board init to initialize the EFI drivers */ - efi_status_t efi_driver_init(void); - /* Called when a block device is added */ -diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c -index 6d00b186250..3fec40b6de5 100644 ---- a/lib/efi_loader/efi_memory.c -+++ b/lib/efi_loader/efi_memory.c -@@ -258,7 +258,7 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map, - } - - /** -- * efi_add_memory_map_pg() - add pages to the memory map -+ * efi_update_memory_map() - update the memory map by adding/removing pages - * - * @start: start address, must be a multiple of - * EFI_PAGE_SIZE -@@ -266,12 +266,11 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map, - * @memory_type: type of memory added - * @overlap_conventional: region may only overlap free(conventional) - * memory -+ * @remove: remove memory map - * Return: status code - */ --static --efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, -- int memory_type, -- bool overlap_conventional) -+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type, -+ bool overlap_conventional, bool remove) - { - struct efi_mem_list *lmem; - struct efi_mem_list *newlist; -@@ -279,9 +278,9 @@ efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, - uint64_t carved_pages = 0; - struct efi_event *evt; - -- EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__, -+ EFI_PRINT("%s: 0x%llx 0x%llx %d %s %s\n", __func__, - start, pages, memory_type, overlap_conventional ? -- "yes" : "no"); -+ "yes" : "no", remove ? "remove" : "add"); - - if (memory_type >= EFI_MAX_MEMORY_TYPE) - return EFI_INVALID_PARAMETER; -@@ -364,7 +363,10 @@ efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, - } - - /* Add our new map */ -- list_add_tail(&newlist->link, &efi_mem); -+ if (!remove) -+ list_add_tail(&newlist->link, &efi_mem); -+ else -+ free(newlist); - - /* And make sure memory is listed in descending order */ - efi_mem_sort(); -@@ -401,7 +403,29 @@ efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type) - pages = efi_size_in_pages(size + (start & EFI_PAGE_MASK)); - start &= ~EFI_PAGE_MASK; - -- return efi_add_memory_map_pg(start, pages, memory_type, false); -+ return efi_update_memory_map(start, pages, memory_type, false, false); -+} -+ -+/** -+ * efi_remove_memory_map() - remove memory area to the memory map -+ * -+ * @start: start address of the memory area -+ * @size: length in bytes of the memory area -+ * @memory_type: type of memory removed -+ * -+ * Return: status code -+ * -+ * This function automatically aligns the start and size of the memory area -+ * to EFI_PAGE_SIZE. -+ */ -+efi_status_t efi_remove_memory_map(u64 start, u64 size, int memory_type) -+{ -+ u64 pages; -+ -+ pages = efi_size_in_pages(size + (start & EFI_PAGE_MASK)); -+ start &= ~EFI_PAGE_MASK; -+ -+ return efi_update_memory_map(start, pages, memory_type, false, true); - } - - /** -@@ -502,7 +526,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, - - efi_addr = (u64)(uintptr_t)map_sysmem(addr, 0); - /* Reserve that map in our memory maps */ -- ret = efi_add_memory_map_pg(efi_addr, pages, memory_type, true); -+ ret = efi_update_memory_map(efi_addr, pages, memory_type, true, false); - if (ret != EFI_SUCCESS) { - /* Map would overlap, bail out */ - lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags); -@@ -823,8 +847,8 @@ static void add_u_boot_and_runtime(void) - uboot_stack_size) & ~EFI_PAGE_MASK; - uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) - - uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; -- efi_add_memory_map_pg(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE, -- false); -+ efi_update_memory_map(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE, -+ false, false); - #if defined(__aarch64__) - /* - * Runtime Services must be 64KiB aligned according to the -@@ -842,8 +866,8 @@ static void add_u_boot_and_runtime(void) - runtime_end = (uintptr_t)__efi_runtime_stop; - runtime_end = (runtime_end + runtime_mask) & ~runtime_mask; - runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT; -- efi_add_memory_map_pg(runtime_start, runtime_pages, -- EFI_RUNTIME_SERVICES_CODE, false); -+ efi_update_memory_map(runtime_start, runtime_pages, -+ EFI_RUNTIME_SERVICES_CODE, false, false); - } - - int efi_memory_init(void) -@@ -878,11 +902,11 @@ int efi_map_update_notify(phys_addr_t addr, phys_size_t size, - pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); - efi_addr &= ~EFI_PAGE_MASK; - -- status = efi_add_memory_map_pg(efi_addr, pages, -+ status = efi_update_memory_map(efi_addr, pages, - op == LMB_MAP_OP_RESERVE ? - EFI_BOOT_SERVICES_DATA : - EFI_CONVENTIONAL_MEMORY, -- false); -+ false, false); - if (status != EFI_SUCCESS) { - log_err("LMB Map notify failure %lu\n", - status & ~EFI_ERROR_MASK); - -From patchwork Fri Feb 28 08:45:26 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sughosh Ganu -X-Patchwork-Id: 2053443 -X-Patchwork-Delegate: xypron.glpk@gmx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1)) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4Z41ym1cNCz1yKH - for ; Fri, 28 Feb 2025 19:46:24 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id BD37E810F1; - Fri, 28 Feb 2025 09:46:08 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=linaro.org -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 4D257810F1; Fri, 28 Feb 2025 09:46:07 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, - RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_SOFTFAIL autolearn=no - autolearn_force=no version=3.4.2 -Received: from foss.arm.com (foss.arm.com [217.140.110.172]) - by phobos.denx.de (Postfix) with ESMTP id 23B3B80FE1 - for ; Fri, 28 Feb 2025 09:46:05 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=linaro.org -Authentication-Results: phobos.denx.de; - spf=fail smtp.mailfrom=sughosh.ganu@linaro.org -Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) - by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB084113E; - Fri, 28 Feb 2025 00:46:19 -0800 (PST) -Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) - by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A01053F673; - Fri, 28 Feb 2025 00:46:01 -0800 (PST) -From: Sughosh Ganu -To: u-boot@lists.denx.de -Cc: Ilias Apalodimas , - Simon Glass , Tom Rini , - Heinrich Schuchardt , - Anton Antonov , - Tobias Waldekranz , Bin Meng , - Sughosh Ganu -Subject: [PATCH v6 3/6] efi_loader: preserve installer images in pmem -Date: Fri, 28 Feb 2025 14:15:26 +0530 -Message-Id: <20250228084529.127823-4-sughosh.ganu@linaro.org> -X-Mailer: git-send-email 2.34.1 -In-Reply-To: <20250228084529.127823-1-sughosh.ganu@linaro.org> -References: <20250228084529.127823-1-sughosh.ganu@linaro.org> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Ilias Apalodimas - -One of the problems OS installers face, when running in EFI, is that -the mounted ISO after calling ExitBootServices goes away. For some -distros this is a problem since they rely on finding some core packages -before continuing the installation. Distros have works around this -- -e.g Fedora has a special kernel command line parameter called -inst.stage2 [0]. - -ACPI has NFIT and NVDIMM support to provide ramdisks to the OS, but we -don't have anything in place for DTs. Linux and device trees have support -for persistent memory devices. - -It's worth noting that for linux to instantiate the /dev/pmemX device, -the memory described in the pmem node has to be omitted from the EFI -memory map we hand over to the OS if ZONE_DEVICES and SPARSEMEM is -enabled. With those enabled the pmem driver ends up calling -devm_memremap_pages() instead of devm_memremap(). The latter works -whether the memory is omitted or marked as reserved, but mapping pages -only works if the memory is omitted. - -On top of that, depending on how the kernel is configured, that memory -area must be page aligned or 2MB aligned. PowerPC is an exception here -and requires 16MB alignment, but since we don't have EFI support for -it, limit the alignment to 2MB. - -Ensure that the ISO image is 2MB aligned and remove the region -occupied by the image from the EFI memory map. - -Signed-off-by: Ilias Apalodimas -Signed-off-by: Sughosh Ganu ---- -Changes since V5: None - - lib/efi_loader/efi_bootmgr.c | 22 +++++++++++++++++----- - 1 file changed, 17 insertions(+), 5 deletions(-) - -diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c -index c6124c590d9..081eff057f4 100644 ---- a/lib/efi_loader/efi_bootmgr.c -+++ b/lib/efi_loader/efi_bootmgr.c -@@ -18,6 +18,8 @@ - #include - #include - #include -+#include -+#include - - static const struct efi_boot_services *bs; - static const struct efi_runtime_services *rs; -@@ -362,13 +364,16 @@ static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size, - } - - /* -- * TODO: expose the ramdisk to OS. -- * Need to pass the ramdisk information by the architecture-specific -- * methods such as 'pmem' device-tree node. -+ * Linux supports 'pmem' which allows OS installers to find, reclaim -+ * the mounted images and continue the installation since the contents -+ * of the pmem region are treated as local media. -+ * -+ * The memory regions used for it needs to be carved out of the EFI -+ * memory map. - */ -- ret = efi_add_memory_map(addr, size, EFI_RESERVED_MEMORY_TYPE); -+ ret = efi_remove_memory_map(addr, size, EFI_CONVENTIONAL_MEMORY); - if (ret != EFI_SUCCESS) { -- log_err("Memory reservation failed\n"); -+ log_err("Failed to reserve memory\n"); - goto err; - } - -@@ -490,6 +495,13 @@ static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp, - ret = EFI_INVALID_PARAMETER; - goto err; - } -+ /* -+ * Depending on the kernel configuration, pmem memory area must be page -+ * aligned or 2MB aligned. PowerPC is an exception here and requires -+ * 16MB alignment, but since we don't have EFI support for it, limit -+ * the alignment to 2MB. -+ */ -+ image_size = ALIGN(image_size, SZ_2M); - - /* - * If the file extension is ".iso" or ".img", mount it and try to load - -From patchwork Fri Feb 28 08:45:27 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sughosh Ganu -X-Patchwork-Id: 2053444 -X-Patchwork-Delegate: xypron.glpk@gmx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1)) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4Z41z21cqkz1yKH - for ; Fri, 28 Feb 2025 19:46:38 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id B7A2B810FE; - Fri, 28 Feb 2025 09:46:11 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=linaro.org -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 9A8D9811C5; Fri, 28 Feb 2025 09:46:10 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, - RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_SOFTFAIL autolearn=no - autolearn_force=no version=3.4.2 -Received: from foss.arm.com (foss.arm.com [217.140.110.172]) - by phobos.denx.de (Postfix) with ESMTP id A52C180FE1 - for ; Fri, 28 Feb 2025 09:46:08 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=linaro.org -Authentication-Results: phobos.denx.de; - spf=fail smtp.mailfrom=sughosh.ganu@linaro.org -Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) - by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 48F081688; - Fri, 28 Feb 2025 00:46:23 -0800 (PST) -Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) - by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1E23D3F673; - Fri, 28 Feb 2025 00:46:04 -0800 (PST) -From: Sughosh Ganu -To: u-boot@lists.denx.de -Cc: Ilias Apalodimas , - Simon Glass , Tom Rini , - Heinrich Schuchardt , - Anton Antonov , - Tobias Waldekranz , Bin Meng , - Sughosh Ganu -Subject: [PATCH v6 4/6] blkmap: store type of blkmap slice in corresponding - structure -Date: Fri, 28 Feb 2025 14:15:27 +0530 -Message-Id: <20250228084529.127823-5-sughosh.ganu@linaro.org> -X-Mailer: git-send-email 2.34.1 -In-Reply-To: <20250228084529.127823-1-sughosh.ganu@linaro.org> -References: <20250228084529.127823-1-sughosh.ganu@linaro.org> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -Add information about the type of blkmap slice as an attribute in the -corresponding slice structure. Put information in the blkmap slice -structure to identify if it is associated with a memory or linear -mapped device. Which can then be used to take specific action based on -the type of the blkmap slice. - -Signed-off-by: Sughosh Ganu -Reviewed-by: Tobias Waldekranz -Reviewed-by: Ilias Apalodimas ---- -Changes since V5: None - - drivers/block/blkmap.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c -index 34eed1380dc..453510cca62 100644 ---- a/drivers/block/blkmap.c -+++ b/drivers/block/blkmap.c -@@ -16,6 +16,10 @@ - - struct blkmap; - -+/* Attributes of blkmap slice */ -+#define BLKMAP_SLICE_LINEAR BIT(0) -+#define BLKMAP_SLICE_MEM BIT(1) -+ - /** - * struct blkmap_slice - Region mapped to a blkmap - * -@@ -25,12 +29,14 @@ struct blkmap; - * @node: List node used to associate this slice with a blkmap - * @blknr: Start block number of the mapping - * @blkcnt: Number of blocks covered by this mapping -+ * @attr: Attributes of blkmap slice - */ - struct blkmap_slice { - struct list_head node; - - lbaint_t blknr; - lbaint_t blkcnt; -+ uint attr; - - /** - * @read: - Read from slice -@@ -169,6 +175,7 @@ int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, - .slice = { - .blknr = blknr, - .blkcnt = blkcnt, -+ .attr = BLKMAP_SLICE_LINEAR, - - .read = blkmap_linear_read, - .write = blkmap_linear_write, -@@ -248,6 +255,7 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, - .slice = { - .blknr = blknr, - .blkcnt = blkcnt, -+ .attr = BLKMAP_SLICE_MEM, - - .read = blkmap_mem_read, - .write = blkmap_mem_write, - -From patchwork Fri Feb 28 08:45:28 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sughosh Ganu -X-Patchwork-Id: 2053445 -X-Patchwork-Delegate: xypron.glpk@gmx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4Z41zB6lfpz1yKH - for ; Fri, 28 Feb 2025 19:46:46 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 1822281111; - Fri, 28 Feb 2025 09:46:15 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=linaro.org -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id A6651807D7; Fri, 28 Feb 2025 09:46:14 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, - RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_SOFTFAIL autolearn=no - autolearn_force=no version=3.4.2 -Received: from foss.arm.com (foss.arm.com [217.140.110.172]) - by phobos.denx.de (Postfix) with ESMTP id 7B487811C5 - for ; Fri, 28 Feb 2025 09:46:12 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=linaro.org -Authentication-Results: phobos.denx.de; - spf=fail smtp.mailfrom=sughosh.ganu@linaro.org -Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) - by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3B092113E; - Fri, 28 Feb 2025 00:46:27 -0800 (PST) -Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) - by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 103233F673; - Fri, 28 Feb 2025 00:46:08 -0800 (PST) -From: Sughosh Ganu -To: u-boot@lists.denx.de -Cc: Ilias Apalodimas , - Simon Glass , Tom Rini , - Heinrich Schuchardt , - Anton Antonov , - Tobias Waldekranz , Bin Meng , - Sughosh Ganu -Subject: [PATCH v6 5/6] blkmap: add an attribute to preserve the mem mapping -Date: Fri, 28 Feb 2025 14:15:28 +0530 -Message-Id: <20250228084529.127823-6-sughosh.ganu@linaro.org> -X-Mailer: git-send-email 2.34.1 -In-Reply-To: <20250228084529.127823-1-sughosh.ganu@linaro.org> -References: <20250228084529.127823-1-sughosh.ganu@linaro.org> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -Some blkmap memory mapped devices might have to be be relevant even -after U-Boot passes control to the next image as part of the platform -boot. An example of such a mapping would be an OS installer ISO image, -information for which has to be provided to the OS kernel. Use the -'preserve' attribute for such mappings. The code for adding a pmem -node to the device-tree then checks if this attribute is set, and adds -a node only for mappings which have this attribute. - -Signed-off-by: Sughosh Ganu -Reviewed-by: Tobias Waldekranz -Reviewed-by: Ilias Apalodimas ---- -Changes since V5: None - - cmd/blkmap.c | 9 +++++++-- - drivers/block/blkmap.c | 12 ++++++++---- - drivers/block/blkmap_helper.c | 2 +- - include/blkmap.h | 4 +++- - 4 files changed, 19 insertions(+), 8 deletions(-) - -diff --git a/cmd/blkmap.c b/cmd/blkmap.c -index 164f80f1387..86a123b1cd3 100644 ---- a/cmd/blkmap.c -+++ b/cmd/blkmap.c -@@ -62,13 +62,18 @@ static int do_blkmap_map_mem(struct map_ctx *ctx, int argc, char *const argv[]) - { - phys_addr_t addr; - int err; -+ bool preserve = false; - - if (argc < 2) - return CMD_RET_USAGE; - - addr = hextoul(argv[1], NULL); - -- err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr); -+ if (argc == 3 && !strcmp(argv[2], "preserve")) -+ preserve = true; -+ -+ err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr, -+ preserve); - if (err) { - printf("Unable to map %#llx at block 0x" LBAF ": %d\n", - (unsigned long long)addr, ctx->blknr, err); -@@ -221,7 +226,7 @@ U_BOOT_CMD_WITH_SUBCMDS( - "blkmap create