diff --git a/0001-Add-bcm2712-compat.patch b/0001-Add-bcm2712-compat.patch new file mode 100644 index 0000000..1e497b8 --- /dev/null +++ b/0001-Add-bcm2712-compat.patch @@ -0,0 +1,24 @@ +From 83612ecf30e9192247ad8c2f67f585360f5ea68b Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 11 Mar 2026 14:27:21 +0000 +Subject: [PATCH] Add bcm2712 compat + +--- + drivers/video/bcm2835.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c +index 0c81e606622..0e0cc1979eb 100644 +--- a/drivers/video/bcm2835.c ++++ b/drivers/video/bcm2835.c +@@ -66,6 +66,7 @@ static int bcm2835_video_probe(struct udevice *dev) + static const struct udevice_id bcm2835_video_ids[] = { + { .compatible = "brcm,bcm2835-hdmi" }, + { .compatible = "brcm,bcm2711-hdmi0" }, ++ { .compatible = "brcm,bcm2712-hdmi0" }, + { .compatible = "brcm,bcm2708-fb" }, + #if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB) + { .compatible = "simple-framebuffer" }, +-- +2.53.0 + diff --git a/0001-Revert-efi_loader-install-device-tree-on-configurati.patch b/0001-Revert-efi_loader-install-device-tree-on-configurati.patch new file mode 100644 index 0000000..0cc6786 --- /dev/null +++ b/0001-Revert-efi_loader-install-device-tree-on-configurati.patch @@ -0,0 +1,85 @@ +From 72a5b6b3cafc7d1f58f451c26eedfb678e54bd9f Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sun, 7 Sep 2025 16:32:30 +0100 +Subject: [PATCH] Revert "efi_loader: install device-tree on configuration + table on every invocation" + +This reverts commit 7e624377e99314bdfac6cb5a3d216dff49a047e9. +--- + lib/efi_loader/efi_helper.c | 39 ++++++++++--------------------------- + 1 file changed, 10 insertions(+), 29 deletions(-) + +diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c +index 44b806aadc4..f211782389a 100644 +--- a/lib/efi_loader/efi_helper.c ++++ b/lib/efi_loader/efi_helper.c +@@ -456,30 +456,11 @@ efi_status_t efi_env_set_load_options(efi_handle_t handle, + */ + static efi_status_t copy_fdt(void **fdtp) + { ++ unsigned long fdt_pages; + efi_status_t ret = 0; + void *fdt, *new_fdt; +- static u64 new_fdt_addr; +- static efi_uintn_t fdt_pages; +- ulong fdt_size; +- +- /* +- * Remove the configuration table that might already be +- * installed, ignoring EFI_NOT_FOUND if no device-tree +- * is installed +- */ +- efi_install_configuration_table(&efi_guid_fdt, NULL); +- +- if (new_fdt_addr) { +- log_debug("%s: Found allocated memory at %#llx, with %#zx pages\n", +- __func__, new_fdt_addr, fdt_pages); +- +- ret = efi_free_pages(new_fdt_addr, fdt_pages); +- if (ret != EFI_SUCCESS) +- log_err("Unable to free up existing FDT memory region\n"); +- +- new_fdt_addr = 0; +- fdt_pages = 0; +- } ++ u64 new_fdt_addr; ++ uint fdt_size; + + /* + * Give us at least 12 KiB of breathing room in case the device tree +@@ -494,18 +475,15 @@ static efi_status_t copy_fdt(void **fdtp) + &new_fdt_addr); + if (ret != EFI_SUCCESS) { + log_err("Failed to reserve space for FDT\n"); +- return ret; ++ goto done; + } +- log_debug("%s: Allocated memory at %#llx, with %#zx pages\n", +- __func__, new_fdt_addr, fdt_pages); +- + new_fdt = (void *)(uintptr_t)new_fdt_addr; + memcpy(new_fdt, fdt, fdt_totalsize(fdt)); + fdt_set_totalsize(new_fdt, fdt_size); + +- *fdtp = new_fdt; +- +- return EFI_SUCCESS; ++ *fdtp = (void *)(uintptr_t)new_fdt_addr; ++done: ++ return ret; + } + + /** +@@ -558,6 +536,9 @@ efi_status_t efi_install_fdt(void *fdt) + const char *fdt_opt; + uintptr_t fdt_addr; + ++ /* Look for device tree that is already installed */ ++ if (efi_get_configuration_table(&efi_guid_fdt)) ++ return EFI_SUCCESS; + /* Check if there is a hardware device tree */ + fdt_opt = env_get("fdt_addr"); + /* Use our own device tree as fallback */ +-- +2.51.0 + diff --git a/ARM-RPi-PCIe-fixes.patch b/ARM-RPi-PCIe-fixes.patch new file mode 100644 index 0000000..2700935 --- /dev/null +++ b/ARM-RPi-PCIe-fixes.patch @@ -0,0 +1,172 @@ +From 354971c474d8a595f3fc610942bf160ac9959343 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 11 Apr 2026 16:14:50 +0100 +Subject: [PATCH 1/2] pci: brcmstb: fix iBAR inbound window address for + pre-BCM2712 + +The reworked brcm_pcie_set_inbound_windows() writes bar_pci (the raw +PCI bus address) directly into the RC BAR config register, and relies +on the UBUS remap registers to supply the CPU-side translation. + +This model works on BCM2712 (RPi5), which has a capable UBUS/AXI +remap block. On BCM2711 (RPi4) the BAR config register expects the +address *offset* (bus_start - phys_start), not the raw bus address, +and the older UBUS remap registers cannot compensate for the +difference. The result is a misconfigured inbound DMA window that +renders the PCIe-attached XHCI USB controller non-functional. + +Fix by branching on the chip type inside brcm_pcie_set_inbound_windows(): + +- Pre-BCM2712: write the offset (bus_start - phys_start) into the BAR + config register, matching the behaviour of the code that was removed. + Skip the UBUS remap registers because the older hardware does not + need them for a single DMA region and setting them to an incorrect + value causes the regression. + +- BCM2712: keep the new behaviour unchanged (raw PCI address in BAR + config, CPU address in UBUS remap registers). + +Also restore the power-of-two size rounding that was present in the +original code (1ULL << fls64(size - 1)) for pre-BCM2712 paths, since +brcm_pcie_encode_ibar_size() is documented to require a power-of-two +input and the DT size value is not guaranteed to already be one. + +Signed-off-by: Peter Robinson +--- + drivers/pci/pcie_brcmstb.c | 58 +++++++++++++++++++++++++++++--------- + 1 file changed, 44 insertions(+), 14 deletions(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index bd1dd17e690..796c3b9ff9c 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -476,10 +476,22 @@ static u32 brcm_ubus_reg_offset(int bar) + return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4); + } + ++/* ++ * Round size up to the next power of two, as required by ++ * brcm_pcie_encode_ibar_size(). If size is already a power of two ++ * fls64(size - 1) still gives the correct result because the hardware ++ * encodes the exponent, not the raw value. ++ */ ++static u64 brcm_ibar_round_size(u64 size) ++{ ++ return 1ULL << fls64(size - 1); ++} ++ + static void brcm_pcie_set_inbound_windows(struct udevice *dev) + { + struct brcm_pcie *pcie = dev_get_priv(dev); + void __iomem *base = pcie->base; ++ bool is_2712 = (pcie->pcie_cfg->type == BCM2712); + int i, ibar_no, ret; + u32 tmp; + +@@ -504,20 +516,38 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) + bar_cpu = region.phys_start; + bar_size = region.size; + +- tmp = lower_32_bits(bar_pci); +- u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), +- RC_BAR2_CONFIG_LO_SIZE_MASK); +- writel(tmp, base + rc_bar_offset); +- writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); +- +- tmp = lower_32_bits(bar_cpu) & +- PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; +- tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; +- writel(tmp, base + ubus_bar_offset); +- +- tmp = upper_32_bits(bar_cpu) & +- PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; +- writel(tmp, base + ubus_bar_offset + 4); ++ if (is_2712) { ++ /* BCM2712: BAR holds raw PCI address; UBUS remap ++ * registers supply the CPU-side translation. */ ++ tmp = lower_32_bits(bar_pci); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); ++ ++ tmp = lower_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; ++ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; ++ writel(tmp, base + ubus_bar_offset); ++ ++ tmp = upper_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; ++ writel(tmp, base + ubus_bar_offset + 4); ++ } else { ++ /* Pre-BCM2712 (e.g. BCM2711 / RPi4): the BAR config ++ * register holds the offset (bus_start - phys_start), ++ * not the raw PCI address. The size must be rounded ++ * up to the next power of two before encoding. */ ++ u64 bar_offset = bar_pci - bar_cpu; ++ u64 bar_size_po2 = brcm_ibar_round_size(bar_size); ++ ++ tmp = lower_32_bits(bar_offset); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size_po2), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_offset), base + rc_bar_offset + 4); ++ /* UBUS remap registers are not used on pre-2712 hardware. */ ++ } + } + } + +-- +2.53.0 + +From d03a2f8be5519519cd1336295cb8627f6a685c07 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 11 Apr 2026 16:21:31 +0100 +Subject: [PATCH 2/2] pci: brcmstb: restore dynamic SCB0 size for pre-BCM2712 + +The reworked probe code hardcodes SCB0 size to 20 (32GB) for all chip +variants. On BCM2712 (RPi5) this is intentional. On BCM2711 (RPi4) +the original code derived the SCB0 size from the actual DMA region size +using ilog2(size) - 15, e.g. 1GB -> value 15 (0xf). Writing 20 +instead misconfigures the inbound memory window and is the remaining +cause of the USB regression after the BAR offset fix. + +Restore the dynamic calculation for pre-BCM2712 chips. + +Signed-off-by: Peter Robinson +--- + drivers/pci/pcie_brcmstb.c | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 796c3b9ff9c..f0b0f1cc117 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -638,9 +638,22 @@ static int brcm_pcie_probe(struct udevice *dev) + MISC_CTRL_PCIE_RCB_MPS_MODE_MASK | + tmp); + +- /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); +- u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); ++ if (pcie->pcie_cfg->type == BCM2712) { ++ /* BCM2712: fixed 32GB SCB0 window */ ++ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); ++ } else { ++ /* Pre-BCM2712: size SCB0 to match the actual DMA region. ++ * rc_bar2_size must be a power of two; ilog2(size) - 15 ++ * gives the hardware encoding (e.g. 1GB -> 15). */ ++ struct pci_region region; ++ u64 rc_bar2_size; ++ ++ pci_get_dma_regions(dev, ®ion, 0); ++ rc_bar2_size = brcm_ibar_round_size(region.size); ++ u32p_replace_bits(&tmp, rc_bar2_size ? ilog2(rc_bar2_size) - 15 : 0xf, ++ MISC_CTRL_SCB0_SIZE_MASK); ++ } + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + if (pcie->pcie_cfg->type == BCM2712) { +-- +2.53.0 + diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch new file mode 100644 index 0000000..68a3274 --- /dev/null +++ b/ARM-RPi5-Enable-PCIe.patch @@ -0,0 +1,2027 @@ +From patchwork Fri Feb 27 15:23:26 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202409 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsY408lKz1xy2 + for ; Sat, 28 Feb 2026 02:23:35 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 15CF383EB3; + Fri, 27 Feb 2026 16:23:33 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id CD42E83E8E; Fri, 27 Feb 2026 16:23:31 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, + RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no + autolearn_force=no version=3.4.2 +Received: from verein.lst.de (verein.lst.de [213.95.11.211]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by phobos.denx.de (Postfix) with ESMTPS id 2240A83CDF + for ; Fri, 27 Feb 2026 16:23:29 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id EAEE468B05; Fri, 27 Feb 2026 16:23:26 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152326.EAEE468B05@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:26 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Add a mapping region for the PCIe bus address spaces to the BCM2712 +memory controller setup. Generously merging the PCIe address spaces +works sufficiently well for a boot loader. + +Signed-off-by: Torsten Duwe +--- + arch/arm/mach-bcm283x/init.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 7a1de22e0ae..7a2faaa4de6 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -18,7 +18,7 @@ + #ifdef CONFIG_ARM64 + #include + +-#define MEM_MAP_MAX_ENTRIES (4) ++#define MEM_MAP_MAX_ENTRIES (5) + + static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { + { +@@ -83,6 +83,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ /* Whole PCIe section */ ++ .virt = 0x1800000000UL, ++ .phys = 0x1800000000UL, ++ .size = 0x0800000000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* SoC bus */ + .virt = 0x107c000000UL, + +From patchwork Fri Feb 27 15:23:29 2026 +Content-Type: text/plain; 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Fri, 27 Feb 2026 16:23:29 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 2/9] pci: brcmstb: Fix PCIe bus numbers +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152329.7C72C68BFE@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:29 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Andrea della Porta + +The linux kernel assigns a new domain for every Root Complex where bus +numbering starts from 0 for each domain. U-Boot does not have domains +and uses a flattened bus numbering scheme instead. This means that any +device or bridge on the second enumerated RC will receive a bus number +equal to the last assigned one +1. This bus number contributes to the +address written into the index register, which will select the +configuration space to be read. Compensate for this contribution by +subtracting the base bus number. + +Signed-off-by: Andrea della Porta +Signed-off-by: Torsten Duwe +--- + drivers/pci/pcie_brcmstb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index f089c48f028..47c0802df23 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -125,7 +125,7 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, + uint offset, void **paddress) + { + struct brcm_pcie *pcie = dev_get_priv(dev); +- unsigned int pci_bus = PCI_BUS(bdf); ++ unsigned int pci_bus = PCI_BUS(bdf) - dev_seq(dev); + unsigned int pci_dev = PCI_DEV(bdf); + unsigned int pci_func = PCI_FUNC(bdf); + int idx; + +From patchwork Fri Feb 27 15:23:31 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202411 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYM0tXtz1xy2 + for ; Sat, 28 Feb 2026 02:23:51 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 98AF483E96; + Fri, 27 Feb 2026 16:23:36 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id C1F7983EF9; Fri, 27 Feb 2026 16:23:34 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, + RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no + autolearn_force=no version=3.4.2 +Received: from verein.lst.de (verein.lst.de [213.95.11.211]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by phobos.denx.de (Postfix) with ESMTPS id AAFE683E76 + for ; Fri, 27 Feb 2026 16:23:32 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id 9A6CD68C7B; Fri, 27 Feb 2026 16:23:31 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 3/9] pci: brcmstb: Support different variants using a cfg + struct +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152331.9A6CD68C7B@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:31 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +The Linux kernel driver already had support for multiple hardware +variants when the bcm2712 was added (see e.g. linux commit +10dbedad3c818 which is the last in a longer set of changes). This +patch brings in this required infrastructure and adds a +differentiation between 2711 and 2712 register layouts on top. +It also accounts for the bcm2712 reset logic quirk that the software +init bit must not remain set, albeit the reset control location is +only corrected in patch#6 of this series. + +Signed-off-by: Torsten Duwe +--- + .../mach-bcm283x/include/mach/acpi/bcm2711.h | 6 +- + drivers/pci/pcie_brcmstb.c | 122 ++++++++++++++++-- + 2 files changed, 114 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +index a86875b1833..6eb5389b858 100644 +--- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h ++++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +@@ -70,6 +70,7 @@ + #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 + #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c + #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f ++#define PCIE_MISC_PCIE_CTRL 0x4064 + #define PCIE_MISC_PCIE_STATUS 0x4068 + #define STATUS_PCIE_PORT_MASK 0x80 + #define STATUS_PCIE_PORT_SHIFT 7 +@@ -107,7 +108,10 @@ + #define PCIE_MSI_INTR2_MASK_SET 0x4510 + + #define PCIE_RGR1_SW_INIT_1 0x9210 +-#define PCIE_EXT_CFG_INDEX 0x9000 ++#define RGR1_SW_INIT_1_PERST_MASK 0x1 ++#define RGR1_SW_INIT_1_PERSTB_MASK 0x4 ++#define RGR1_SW_INIT_1_INIT_MASK 0x2 ++ + /* A small window pointing at the ECAM of the device selected by CFG_INDEX */ + #define PCIE_EXT_CFG_DATA 0x8000 + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 47c0802df23..261f8790528 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -49,6 +49,28 @@ + #define SSC_STATUS_PLL_LOCK_MASK 0x800 + #define SSC_STATUS_PLL_LOCK_SHIFT 11 + ++enum { ++ RGR1_SW_INIT_1, ++ EXT_CFG_INDEX, ++ EXT_CFG_DATA, ++ PCIE_HARD_DEBUG, ++}; ++ ++enum brcm_pcie_type { ++ BCM2711, ++ BCM2712 ++}; ++ ++struct brcm_pcie; ++ ++struct brcm_pcie_cfg_data { ++ const int *offsets; ++ const enum brcm_pcie_type type; ++ void (*perst_set)(struct brcm_pcie *pcie, u32 val); ++ void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); ++ bool (*rc_mode)(struct brcm_pcie *pcie); ++}; ++ + /** + * struct brcm_pcie - the PCIe controller state + * @base: Base address of memory mapped IO registers of the controller +@@ -61,6 +83,7 @@ struct brcm_pcie { + + int gen; + bool ssc; ++ const struct brcm_pcie_cfg_data *pcie_cfg; + }; + + /** +@@ -104,6 +127,36 @@ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) + return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; + } + ++static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) ++{ ++ if (val) ++ setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_PERST_MASK); ++ else ++ clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_PERST_MASK); ++} ++ ++static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) ++{ ++ u32 tmp; ++ ++ /* Perst bit has moved and assert value is 0 */ ++ tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); ++ u32p_replace_bits(&tmp, !val, RGR1_SW_INIT_1_PERSTB_MASK); ++ writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); ++} ++ ++static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) ++{ ++ if (val) ++ setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_INIT_MASK); ++ else ++ clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_INIT_MASK); ++} ++ + /** + * brcm_pcie_link_up() - Check whether the PCIe link is up + * @pcie: Pointer to the PCIe controller state +@@ -150,8 +203,8 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, + /* For devices, write to the config space index register */ + idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0); + +- writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); +- *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; ++ writel(idx, pcie->base + pcie->pcie_cfg->offsets[EXT_CFG_INDEX]); ++ *paddress = pcie->base + pcie->pcie_cfg->offsets[EXT_CFG_DATA] + offset; + + return 0; + } +@@ -365,8 +418,9 @@ static int brcm_pcie_probe(struct udevice *dev) + * e.g. BCM7278, the fundamental reset should not be asserted here. + * This will need to be changed when support for other SoCs is added. + */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, +- PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK); ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 1); ++ if (pcie->pcie_cfg->type != BCM2712) ++ pcie->pcie_cfg->perst_set(pcie, 1); + /* + * The delay is a safety precaution to preclude the reset signal + * from looking like a glitch. +@@ -374,9 +428,9 @@ static int brcm_pcie_probe(struct udevice *dev) + udelay(100); + + /* Take the bridge out of reset */ +- clrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 0); + +- clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], + PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); + + /* Wait for SerDes to be stable */ +@@ -426,8 +480,7 @@ static int brcm_pcie_probe(struct udevice *dev) + brcm_pcie_set_gen(pcie, pcie->gen); + + /* Unassert the fundamental reset */ +- clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, +- PCIE_RGR1_SW_INIT_1_PERST_MASK); ++ pcie->pcie_cfg->perst_set(pcie, 0); + + /* + * Wait for 100ms after PERST# deassertion; see PCIe CEM specification +@@ -446,7 +499,7 @@ static int brcm_pcie_probe(struct udevice *dev) + return -EINVAL; + } + +- if (!brcm_pcie_rc_mode(pcie)) { ++ if (!pcie->pcie_cfg->rc_mode(pcie)) { + printf("PCIe misconfigured; is in EP mode\n"); + return -EINVAL; + } +@@ -514,14 +567,25 @@ static int brcm_pcie_remove(struct udevice *dev) + void __iomem *base = pcie->base; + + /* Assert fundamental reset */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK); ++ setbits_le32(base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ PCIE_RGR1_SW_INIT_1_PERST_MASK); + + /* Turn off SerDes */ +- setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ setbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], + PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); + + /* Shutdown bridge */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 1); ++ ++ /* ++ * For the controllers that are utilizing reset for bridge Sw init, ++ * such as BCM2712, reset should be deasserted after assertion. ++ * Leaving it in asserted state may lead to unexpected hangs in ++ * the Linux Kernel driver because it do not perform reset initialization ++ * and start accessing device memory. ++ */ ++ if (pcie->pcie_cfg->type == BCM2712) ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 0); + + return 0; + } +@@ -546,6 +610,7 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) + else + pcie->gen = max_link_speed; + ++ pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); + return 0; + } + +@@ -554,8 +619,39 @@ static const struct dm_pci_ops brcm_pcie_ops = { + .write_config = brcm_pcie_write_config, + }; + ++static const int pcie_offsets[] = { ++ [RGR1_SW_INIT_1] = 0x9210, ++ [EXT_CFG_INDEX] = 0x9000, ++ [EXT_CFG_DATA] = 0x8000, ++ [PCIE_HARD_DEBUG] = 0x4204, ++}; ++ ++static const struct brcm_pcie_cfg_data bcm2711_cfg = { ++ .offsets = pcie_offsets, ++ .type = BCM2711, ++ .perst_set = brcm_pcie_perst_set_generic, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++ .rc_mode = brcm_pcie_rc_mode, ++}; ++ ++static const int pcie_offsets_bcm2712[] = { ++ [RGR1_SW_INIT_1] = 0x0, ++ [EXT_CFG_INDEX] = 0x9000, ++ [EXT_CFG_DATA] = 0x8000, ++ [PCIE_HARD_DEBUG] = 0x4304, ++}; ++ ++static const struct brcm_pcie_cfg_data bcm2712_cfg = { ++ .offsets = pcie_offsets_bcm2712, ++ .type = BCM2712, ++ .perst_set = brcm_pcie_perst_set_2712, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++ .rc_mode = brcm_pcie_rc_mode, ++}; ++ + static const struct udevice_id brcm_pcie_ids[] = { +- { .compatible = "brcm,bcm2711-pcie" }, ++ { .compatible = "brcm,bcm2711-pcie", .data = (ulong)&bcm2711_cfg }, ++ { .compatible = "brcm,bcm2712-pcie", .data = (ulong)&bcm2712_cfg }, + { } + }; + + +From patchwork Fri Feb 27 15:23:34 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202412 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYX5WvXz1xy2 + for ; Sat, 28 Feb 2026 02:24:00 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id D5E9983F14; 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spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id 4A0BE68D07; Fri, 27 Feb 2026 16:23:34 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 4/9] pci: brcmstb: Add RPi5 reset facilities +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152334.4A0BE68D07@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:34 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +A driver for Broadcom reset controllers ported from +linux/drivers/reset/reset-brcmstb.c to U-Boot. + +Signed-off-by: Torsten Duwe +--- + configs/rpi_arm64_defconfig | 1 + + drivers/reset/Kconfig | 7 +++ + drivers/reset/Makefile | 1 + + drivers/reset/reset-brcmstb.c | 97 +++++++++++++++++++++++++++++++++++ + 4 files changed, 106 insertions(+) + create mode 100644 drivers/reset/reset-brcmstb.c + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 69e8e72c5d7..153d7ed301e 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -44,6 +44,7 @@ CONFIG_BCMGENET=y + CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set ++CONFIG_RESET_BRCMSTB=y + CONFIG_DM_RNG=y + CONFIG_RNG_IPROC200=y + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 2fd91d6299c..46ffc103320 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -64,6 +64,13 @@ config RESET_BCM6345 + help + Support reset controller on BCM6345. + ++config RESET_BRCMSTB ++ bool "Generic Reset controller driver for Broadcom" ++ help ++ This enables reset controller for Broadcom devices. ++ If you wish to use reset resources managed by the Broadcom ++ Reset Controller, say Y here. Otherwise, say N. ++ + config RESET_UNIPHIER + bool "Reset controller driver for UniPhier SoCs" + depends on ARCH_UNIPHIER +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index ee5b009d134..ebf3d7425a4 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o + obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o + obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o + obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o ++obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o + obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o + obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o + obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c +new file mode 100644 +index 00000000000..7861f7c9baf +--- /dev/null ++++ b/drivers/reset/reset-brcmstb.c +@@ -0,0 +1,97 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB generic reset controller ++ * ++ * Copyright (C) 2024 EPAM Systems ++ * ++ * Moved from linux kernel: ++ * Author: Florian Fainelli ++ * Copyright (C) 2018 Broadcom ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct brcmstb_reset { ++ void __iomem *base; ++}; ++ ++#define SW_INIT_SET 0x00 ++#define SW_INIT_CLEAR 0x04 ++#define SW_INIT_STATUS 0x08 ++ ++#define SW_INIT_BIT(id) BIT((id) & 0x1f) ++#define SW_INIT_BANK(id) ((id) >> 5) ++ ++#define usleep_range(a, b) udelay((b)) ++ ++/* A full bank contains extra registers that we are not utilizing but still ++ * qualify as a single bank. ++ */ ++#define SW_INIT_BANK_SIZE 0x18 ++ ++static int brcmstb_reset_assert(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset *priv = dev_get_priv(rst->dev); ++ ++ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_SET); ++ return 0; ++} ++ ++static int brcmstb_reset_deassert(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset *priv = dev_get_priv(rst->dev); ++ ++ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_CLEAR); ++ /* Maximum reset delay after de-asserting a line and seeing block ++ * operation is typically 14us for the worst case, build some slack ++ * here. ++ */ ++ usleep_range(100, 200); ++ return 0; ++} ++ ++static int brcmstb_reset_status(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset *priv = dev_get_priv(rst->dev); ++ ++ return readl_relaxed(priv->base + off + SW_INIT_STATUS) & ++ SW_INIT_BIT(rst->id); ++} ++ ++struct reset_ops brcmstb_reset_reset_ops = { ++ .rst_assert = brcmstb_reset_assert, ++ .rst_deassert = brcmstb_reset_deassert, ++ .rst_status = brcmstb_reset_status}; ++ ++static int brcmstb_reset_probe(struct udevice *dev) ++{ ++ struct brcmstb_reset *priv = dev_get_priv(dev); ++ ++ priv->base = dev_remap_addr(dev); ++ if (!priv->base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct udevice_id brcmstb_reset_ids[] = { ++ {.compatible = "brcm,brcmstb-reset"}, {/* sentinel */}}; ++ ++U_BOOT_DRIVER(brcmstb_reset) = { ++ .name = "brcmstb-reset", ++ .id = UCLASS_RESET, ++ .of_match = brcmstb_reset_ids, ++ .ops = &brcmstb_reset_reset_ops, ++ .probe = brcmstb_reset_probe, ++ .priv_auto = sizeof(struct brcmstb_reset), ++}; + +From patchwork Fri Feb 27 15:23:36 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202413 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYk0pstz1xy2 + for ; Sat, 28 Feb 2026 02:24:10 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 327F183E8E; + Fri, 27 Feb 2026 16:23:41 +0100 (CET) +Authentication-Results: phobos.denx.de; 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Fri, 27 Feb 2026 16:23:36 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 5/9] pci: brcmstb: Add RPi5 rescal reset facilities +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152336.C7C2E68D0A@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:36 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +A driver for Broadcom rescal reset controllers ported from +linux/drivers/reset/reset-brcmstb-rescal.c to U-Boot. + +Signed-off-by: Torsten Duwe +--- + configs/rpi_arm64_defconfig | 1 + + drivers/reset/Kconfig | 7 ++ + drivers/reset/Makefile | 1 + + drivers/reset/reset-brcmstb-rescal.c | 103 +++++++++++++++++++++++++++ + 4 files changed, 112 insertions(+) + create mode 100644 drivers/reset/reset-brcmstb-rescal.c + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 153d7ed301e..38af5029403 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -45,6 +45,7 @@ CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_RESET_BRCMSTB=y ++CONFIG_RESET_BRCMSTB_RESCAL=y + CONFIG_DM_RNG=y + CONFIG_RNG_IPROC200=y + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 46ffc103320..b7d2d4b18d5 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -71,6 +71,13 @@ config RESET_BRCMSTB + If you wish to use reset resources managed by the Broadcom + Reset Controller, say Y here. Otherwise, say N. + ++config RESET_BRCMSTB_RESCAL ++ bool "Generic Rescal Reset controller driver for Broadcom" ++ help ++ Support rescal reset controller on Broadcom. ++ If you wish to use reset resources managed by the Broadcom ++ Reset Controller, say Y here. Otherwise, say N. ++ + config RESET_UNIPHIER + bool "Reset controller driver for UniPhier SoCs" + depends on ARCH_UNIPHIER +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index ebf3d7425a4..c7a9da3268d 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o + obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o + obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o + obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o ++obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o + obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o + obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o + obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c +new file mode 100644 +index 00000000000..fc8fcfa8b3f +--- /dev/null ++++ b/drivers/reset/reset-brcmstb-rescal.c +@@ -0,0 +1,103 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB generic reset controller ++ * ++ * Copyright (C) 2024 EPAM Systems ++ * Moved from linux kernel: ++ * Copyright (C) 2018-2020 Broadcom ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BRCM_RESCAL_START 0x0 ++#define BRCM_RESCAL_START_BIT BIT(0) ++#define BRCM_RESCAL_CTRL 0x4 ++#define BRCM_RESCAL_STATUS 0x8 ++#define BRCM_RESCAL_STATUS_BIT BIT(0) ++ ++struct brcm_rescal_reset { ++ void __iomem *base; ++}; ++ ++/* Also doubles a deassert */ ++static int brcm_rescal_reset_set(struct reset_ctl *rst) ++{ ++ struct brcm_rescal_reset *data = dev_get_priv(rst->dev); ++ void __iomem *base = data->base; ++ u32 reg; ++ int ret; ++ ++ reg = readl(base + BRCM_RESCAL_START); ++ writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); ++ reg = readl(base + BRCM_RESCAL_START); ++ if (!(reg & BRCM_RESCAL_START_BIT)) { ++ dev_err(rst->dev, "failed to start SATA/PCIe rescal\n"); ++ return -EIO; ++ } ++ ++ ret = readl_poll_timeout(base + BRCM_RESCAL_STATUS, reg, ++ (reg & BRCM_RESCAL_STATUS_BIT), 100); ++ if (ret) { ++ dev_err(rst->dev, "time out on SATA/PCIe rescal\n"); ++ return ret; ++ } ++ ++ reg = readl(base + BRCM_RESCAL_START); ++ writel(reg & ~BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); ++ ++ dev_dbg(rst->dev, "SATA/PCIe rescal success\n"); ++ return 0; ++} ++ ++/* A dummy function - deassert/reset does all the work */ ++static int brcm_rescal_reset_assert(struct reset_ctl *rst) ++{ ++ return 0; ++} ++ ++static int brcm_rescal_reset_xlate(struct reset_ctl *reset_ctl, ++ struct ofnode_phandle_args *args) ++{ ++ /* This is needed if #reset-cells == 0. */ ++ return 0; ++} ++ ++static const struct reset_ops brcm_rescal_reset_ops = { ++ .rst_deassert = brcm_rescal_reset_set, ++ .rst_assert = brcm_rescal_reset_assert, ++ .of_xlate = brcm_rescal_reset_xlate, ++}; ++ ++static int brcm_rescal_reset_probe(struct udevice *dev) ++{ ++ struct brcm_rescal_reset *data = dev_get_priv(dev); ++ ++ data->base = dev_remap_addr(dev); ++ if (!data->base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct udevice_id brcm_rescal_reset_of_match[] = { ++ {.compatible = "brcm,bcm7216-pcie-sata-rescal"}, ++ {}, ++}; ++ ++U_BOOT_DRIVER(brcmstb_reset_rescal) = { ++ .name = "brcmstb-reset-rescal", ++ .id = UCLASS_RESET, ++ .of_match = brcm_rescal_reset_of_match, ++ .ops = &brcm_rescal_reset_ops, ++ .probe = brcm_rescal_reset_probe, ++ .priv_auto = sizeof(struct brcm_rescal_reset), ++}; + +From patchwork Fri Feb 27 15:23:41 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202414 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYt68Kqz1xy2 + for ; Sat, 28 Feb 2026 02:24:18 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 720AC83F37; + Fri, 27 Feb 2026 16:23:46 +0100 (CET) +Authentication-Results: phobos.denx.de; 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Fri, 27 Feb 2026 16:23:41 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 6/9] pci: brcmstb: Get and use bridge and rescal reset + properties +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152341.3B6C468D13@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:41 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Check whether the device tree has nodes for the two reset controls and use +them if so. + +Signed-off-by: Torsten Duwe +--- + drivers/pci/pcie_brcmstb.c | 51 +++++++++++++++++++++++++++++++++++++- + 1 file changed, 50 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 261f8790528..1f97cda5cc7 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + /* PCIe parameters */ + #define BRCM_NUM_PCIE_OUT_WINS 4 +@@ -83,6 +84,8 @@ struct brcm_pcie { + + int gen; + bool ssc; ++ struct reset_ctl rescal; ++ struct reset_ctl bridge_reset; + const struct brcm_pcie_cfg_data *pcie_cfg; + }; + +@@ -147,6 +150,34 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); + } + ++static void brcm_pcie_get_resets_dt(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ int ret; ++ ++ ret = reset_get_by_name(dev, "rescal", &pcie->rescal); ++ if (ret) { ++ printf("Unable to get rescal reset\n"); ++ return; ++ } ++ ++ ret = reset_get_by_name(dev, "bridge", &pcie->bridge_reset); ++ if (ret) { ++ printf("Unable to get bridge reset\n"); ++ return; ++ } ++} ++ ++static void brcm_pcie_do_reset(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ int ret; ++ ++ ret = reset_deassert(&pcie->rescal); ++ if (ret) ++ printf("failed to deassert 'rescal'\n"); ++} ++ + static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) + { + if (val) +@@ -157,6 +188,14 @@ static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val + RGR1_SW_INIT_1_INIT_MASK); + } + ++static void brcm_pcie_bridge_sw_init_set_2712(struct brcm_pcie *pcie, u32 val) ++{ ++ if (val) ++ reset_assert(&pcie->bridge_reset); ++ else ++ reset_deassert(&pcie->bridge_reset); ++} ++ + /** + * brcm_pcie_link_up() - Check whether the PCIe link is up + * @pcie: Pointer to the PCIe controller state +@@ -413,6 +452,12 @@ static int brcm_pcie_probe(struct udevice *dev) + u16 nlw, cls, lnksta; + u32 tmp; + ++ /* ++ * Ensure rescal reset for BCM2712 is really disabled. ++ */ ++ if (pcie->pcie_cfg->type == BCM2712) ++ brcm_pcie_do_reset(dev); ++ + /* + * Reset the bridge, assert the fundamental reset. Note for some SoCs, + * e.g. BCM7278, the fundamental reset should not be asserted here. +@@ -611,6 +656,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) + pcie->gen = max_link_speed; + + pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); ++ ++ if (pcie->pcie_cfg->type == BCM2712) ++ brcm_pcie_get_resets_dt(dev); ++ + return 0; + } + +@@ -645,7 +694,7 @@ static const struct brcm_pcie_cfg_data bcm2712_cfg = { + .offsets = pcie_offsets_bcm2712, + .type = BCM2712, + .perst_set = brcm_pcie_perst_set_2712, +- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_2712, + .rc_mode = brcm_pcie_rc_mode, + }; + + +From patchwork Fri Feb 27 15:23:44 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202415 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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+- else if (log2_in >= 16 && log2_in <= 37) +- /* Covers 64KB to 32GB, (inclusive) */ ++ else if (log2_in >= 16 && log2_in <= 36) ++ /* Covers 64KB to 64GB, (inclusive) */ + return log2_in - 15; + + /* Something is awry so disable */ + +From patchwork Fri Feb 27 15:23:48 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202416 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsZG0Fbrz1xy2 + for ; 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Fri, 27 Feb 2026 16:23:49 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id BFF2568BFE; Fri, 27 Feb 2026 16:23:48 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 8/9] pci: brcmstb: rework iBAR handling +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152348.BFF2568BFE@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:48 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Rework the setup of inbound PCIe windows: use the convenience functions +from Linux kernel commit ae6476c6de187 to calculate the BAR offsets and +factor out the setup code into a separate function. + +The Linux kernel first allocates and populates an array of inbound_win[] +and sets the BARs from it later, while U-Boot does it all on the fly, +in one go, so the code is not 1:1 comparable. + +Signed-off-by: Torsten Duwe +--- + drivers/pci/pcie_brcmstb.c | 107 ++++++++++++++++++++++++++++++------- + 1 file changed, 88 insertions(+), 19 deletions(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 8a25fb04563..e5c848c9e8e 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -50,6 +50,29 @@ + #define SSC_STATUS_PLL_LOCK_MASK 0x800 + #define SSC_STATUS_PLL_LOCK_SHIFT 11 + ++#define PCIE_RC_PL_PHY_CTL_15 0x184c ++#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 ++#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff ++ ++#define PCIE_MISC_UBUS_CTRL 0x40a4 ++#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK BIT(13) ++#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK BIT(19) ++#define PCIE_MISC_AXI_READ_ERROR_DATA 0x4170 ++#define PCIE_MISC_UBUS_TIMEOUT 0x40A8 ++#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c ++#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 ++#define PCIE_MISC_RC_BAR4_CONFIG_HI 0x40d8 ++#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK 0xff ++#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI 0x4110 ++#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE 0x1 ++#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK 0xfffff000 ++#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO 0x410c ++ ++#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac ++#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP 0x40b4 ++#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0) ++#define MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 ++ + enum { + RGR1_SW_INIT_1, + EXT_CFG_INDEX, +@@ -437,17 +460,75 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); + } + ++static u32 brcm_bar_reg_offset(int bar) ++{ ++ if (bar <= 3) ++ return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); ++ else ++ return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); ++} ++ ++static u32 brcm_ubus_reg_offset(int bar) ++{ ++ if (bar <= 3) ++ return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); ++ else ++ return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4); ++} ++ ++static void brcm_pcie_set_inbound_windows(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ void __iomem *base = pcie->base; ++ int i, ibar_no, ret; ++ u32 tmp; ++ ++ ibar_no = 0; ++ /* pre-2712 chips leave the first entry empty */ ++ if (pcie->pcie_cfg->type != BCM2712) ++ ibar_no++; ++ ++ /* program inbound windows from OF property "dma-regions" */ ++ for (i = 0; i < 7; i++, ibar_no++) { ++ u64 bar_cpu, bar_size, bar_pci; ++ struct pci_region region; ++ int ubus_bar_offset, rc_bar_offset; ++ ++ ret = pci_get_dma_regions(dev, ®ion, i); ++ if (ret) /* no region #i? Then we're done. */ ++ break; ++ ubus_bar_offset = brcm_ubus_reg_offset(ibar_no + 1); ++ rc_bar_offset = brcm_bar_reg_offset(ibar_no + 1); ++ ++ bar_pci = region.bus_start; ++ bar_cpu = region.phys_start; ++ bar_size = region.size; ++ ++ tmp = lower_32_bits(bar_pci); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); ++ ++ tmp = lower_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; ++ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; ++ writel(tmp, base + ubus_bar_offset); ++ ++ tmp = upper_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; ++ writel(tmp, base + ubus_bar_offset + 4); ++ } ++} ++ + static int brcm_pcie_probe(struct udevice *dev) + { + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + struct brcm_pcie *pcie = dev_get_priv(dev); + void __iomem *base = pcie->base; +- struct pci_region region; + bool ssc_good = false; + int num_out_wins = 0; +- u64 rc_bar2_offset, rc_bar2_size; +- unsigned int scb_size_val; + int i, ret; + u16 nlw, cls, lnksta; + u32 tmp; +@@ -488,23 +569,9 @@ static int brcm_pcie_probe(struct udevice *dev) + MISC_CTRL_CFG_READ_UR_MODE_MASK | + MISC_CTRL_MAX_BURST_SIZE_128); + +- pci_get_dma_regions(dev, ®ion, 0); +- rc_bar2_offset = region.bus_start - region.phys_start; +- rc_bar2_size = 1ULL << fls64(region.size - 1); +- +- tmp = lower_32_bits(rc_bar2_offset); +- u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), +- RC_BAR2_CONFIG_LO_SIZE_MASK); +- writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); +- writel(upper_32_bits(rc_bar2_offset), +- base + PCIE_MISC_RC_BAR2_CONFIG_HI); +- +- scb_size_val = rc_bar2_size ? +- ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ +- ++ /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); +- u32p_replace_bits(&tmp, scb_size_val, +- MISC_CTRL_SCB0_SIZE_MASK); ++ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + /* Disable the PCIe->GISB memory window (RC_BAR1) */ +@@ -521,6 +588,8 @@ static int brcm_pcie_probe(struct udevice *dev) + /* Clear any interrupts we find on boot */ + writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); + ++ brcm_pcie_set_inbound_windows(dev); ++ + if (pcie->gen) + brcm_pcie_set_gen(pcie, pcie->gen); + + +From patchwork Fri Feb 27 15:23:52 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202417 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsZR5GzHz1xy2 + for ; Sat, 28 Feb 2026 02:24:47 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 2D46783EDF; + Fri, 27 Feb 2026 16:23:57 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id 5671E83F63; Fri, 27 Feb 2026 16:23:56 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, + RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no + autolearn_force=no version=3.4.2 +Received: from verein.lst.de (verein.lst.de [213.95.11.211]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by phobos.denx.de (Postfix) with ESMTPS id 300CA83F56 + for ; Fri, 27 Feb 2026 16:23:54 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id F152968D16; Fri, 27 Feb 2026 16:23:52 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 9/9] pci: brcmstb: Adapt to AXI bridge +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152352.F152968D16@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:52 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Fix-ups for the BCM root complex when it is located behind an AXI +bridge and clocked with 54MHz. Some are from kernel commit +377bced88c326, some where picked by Oleksii off a now-stale older +branch. All reworked for the simpler setup code in U-Boot. + +Signed-off-by: Torsten Duwe +--- + .../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 + + drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++- + 2 files changed, 64 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +index 6eb5389b858..869482eaffe 100644 +--- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h ++++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +@@ -54,6 +54,7 @@ + #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 + #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 + #define MISC_CTRL_MAX_BURST_SIZE_128 0x0 ++#define MISC_CTRL_MAX_BURST_SIZE_128_2712 0x100000 + #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 + + #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index e5c848c9e8e..bd1dd17e690 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -521,6 +521,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) + } + } + ++static void brcm_pcie_munge_pll(struct brcm_pcie *pcie) ++{ ++ u32 tmp; ++ int ret, i; ++ u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; ++ u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; ++ ++ ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, ++ 0x1600); ++ for (i = 0; i < ARRAY_SIZE(regs); i++) { ++ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); ++ debug("PCIE MDIO pre_refclk 0x%02x = 0x%04x\n", ++ regs[i], tmp); ++ } ++ for (i = 0; i < ARRAY_SIZE(regs); i++) { ++ brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); ++ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); ++ debug("PCIE MDIO post_refclk 0x%02x = 0x%04x\n", ++ regs[i], tmp); ++ } ++ ++ udelay(200); ++} ++ + static int brcm_pcie_probe(struct udevice *dev) + { + struct udevice *ctlr = pci_get_controller(dev); +@@ -562,18 +586,56 @@ static int brcm_pcie_probe(struct udevice *dev) + /* Wait for SerDes to be stable */ + udelay(100); + ++ if (pcie->pcie_cfg->type == BCM2712) { ++ /* Allow a 54MHz (xosc) refclk source */ ++ brcm_pcie_munge_pll(pcie); ++ /* Fix for L1SS errata */ ++ tmp = readl(base + PCIE_RC_PL_PHY_CTL_15); ++ tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; ++ /* PM clock period is 18.52ns (round down) */ ++ tmp |= 0x12; ++ writel(tmp, base + PCIE_RC_PL_PHY_CTL_15); ++ } ++ ++ tmp = (pcie->pcie_cfg->type == BCM2712) ? ++ MISC_CTRL_MAX_BURST_SIZE_128_2712 : ++ MISC_CTRL_MAX_BURST_SIZE_128; + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, + MISC_CTRL_MAX_BURST_SIZE_MASK, + MISC_CTRL_SCB_ACCESS_EN_MASK | + MISC_CTRL_CFG_READ_UR_MODE_MASK | +- MISC_CTRL_MAX_BURST_SIZE_128); ++ MISC_CTRL_PCIE_RCB_MPS_MODE_MASK | ++ tmp); + + /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); + u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + ++ if (pcie->pcie_cfg->type == BCM2712) { ++ /* Suppress AXI error responses and return 1s for read failures */ ++ tmp = readl(base + PCIE_MISC_UBUS_CTRL); ++ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK); ++ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK); ++ writel(tmp, base + PCIE_MISC_UBUS_CTRL); ++ writel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA); ++ ++ /* ++ * Adjust timeouts. The UBUS timeout also affects CRS ++ * completion retries, as the request will get terminated if ++ * either timeout expires, so both have to be a large value ++ * (in clocks of 750MHz). ++ * Set UBUS timeout to 250ms, then set RC config retry timeout ++ * to be ~240ms. ++ * ++ * Setting CRSVis=1 will stop the core from blocking on a CRS ++ * response, but does require the device to be well-behaved... ++ */ ++ writel(0xB2D0000, base + PCIE_MISC_UBUS_TIMEOUT); ++ writel(0xABA0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT); ++ } ++ + /* Disable the PCIe->GISB memory window (RC_BAR1) */ + clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, + RC_BAR1_CONFIG_LO_SIZE_MASK); +From 9e0fc68de1424b3db495f8a661d578435c4137c1 Mon Sep 17 00:00:00 2001 +From: Torsten Duwe +Date: Mon, 2 Mar 2026 13:59:40 +0100 +Subject: [PATCH] Fix NVMe for non-zero bus offsets + +Hi all, + +working on the RPi5 I found that the U-Boot NVMe code is lacking a significant +feature. The NVMe protocol heavily relies on device access into main memory, +in the medieval times of computing this was called "bus master DMA". The NVMe +device must generate memory addresses and read or write contents there. The +current U-Boot code does in no way account for PCIe bridges in the path that +add an offset to such "inbound accesses". Consequently, U-Boot can only boot +from NVMe on platforms where this address offset is zero. +(These are surprisingly many!) + +This proposed patch uses the already existent dev_phys_to_bus(), which can +dig up the correct offset from associated DT nodes and subtract it. I have +no strong opinion on the macro naming, and whether it should silently pull +in the "dev" from the outer scope or have it better passed explicitly. + +Signed-off-by: Torsten Duwe +--- + drivers/nvme/nvme.c | 29 ++++++++++++++++------------- + 1 file changed, 16 insertions(+), 13 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 2b14437f69c..039fbe0bc75 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -27,6 +28,8 @@ + #define IO_TIMEOUT 30 + #define MAX_PRP_POOL 512 + ++#define BUS_ADDR(a) dev_phys_to_bus(dev->udev, (a)) ++ + static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) + { + int timeout; +@@ -91,12 +94,12 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + i = 0; + while (nprps) { + if ((i == (prps_per_page - 1)) && nprps > 1) { +- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + +- page_size); ++ *(prp_pool + i) = cpu_to_le64(BUS_ADDR((ulong)prp_pool + ++ page_size)); + i = 0; + prp_pool += page_size; + } +- *(prp_pool + i++) = cpu_to_le64(dma_addr); ++ *(prp_pool + i++) = cpu_to_le64(BUS_ADDR(dma_addr)); + dma_addr += page_size; + nprps--; + } +@@ -393,8 +396,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) + dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; + + writel(aqa, &dev->bar->aqa); +- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); +- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); ++ nvme_writeq(BUS_ADDR((ulong)nvmeq->sq_cmds), &dev->bar->asq); ++ nvme_writeq(BUS_ADDR((ulong)nvmeq->cqes), &dev->bar->acq); + + result = nvme_enable_ctrl(dev); + if (result) +@@ -420,7 +423,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_cq.opcode = nvme_admin_create_cq; +- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); ++ c.create_cq.prp1 = cpu_to_le64(BUS_ADDR((ulong)nvmeq->cqes)); + c.create_cq.cqid = cpu_to_le16(qid); + c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_cq.cq_flags = cpu_to_le16(flags); +@@ -437,7 +440,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_sq.opcode = nvme_admin_create_sq; +- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); ++ c.create_sq.prp1 = cpu_to_le64(BUS_ADDR((ulong)nvmeq->sq_cmds)); + c.create_sq.sqid = cpu_to_le16(qid); + c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_sq.sq_flags = cpu_to_le16(flags); +@@ -458,14 +461,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.identify.opcode = nvme_admin_identify; + c.identify.nsid = cpu_to_le32(nsid); +- c.identify.prp1 = cpu_to_le64(dma_addr); ++ c.identify.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); + + length -= (page_size - offset); + if (length <= 0) { + c.identify.prp2 = 0; + } else { + dma_addr += (page_size - offset); +- c.identify.prp2 = cpu_to_le64(dma_addr); ++ c.identify.prp2 = cpu_to_le64(BUS_ADDR(dma_addr)); + } + + c.identify.cns = cpu_to_le32(cns); +@@ -490,7 +493,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_get_features; + c.features.nsid = cpu_to_le32(nsid); +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + + ret = nvme_submit_admin_cmd(dev, &c, result); +@@ -516,7 +519,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, + + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_set_features; +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + c.features.dword11 = cpu_to_le32(dword11); + +@@ -785,8 +788,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + c.rw.slba = cpu_to_le64(slba); + slba += lbas; + c.rw.length = cpu_to_le16(lbas - 1); +- c.rw.prp1 = cpu_to_le64(temp_buffer); +- c.rw.prp2 = cpu_to_le64(prp2); ++ c.rw.prp1 = cpu_to_le64(BUS_ADDR(temp_buffer)); ++ c.rw.prp2 = cpu_to_le64(BUS_ADDR(prp2)); + status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], + &c, NULL, IO_TIMEOUT); + if (status) +-- +2.53.0 + +From 253adf9d1bbf0a166f63b30f6ce38cac69239a34 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sun, 29 Mar 2026 20:28:41 +0100 +Subject: [PATCH] rpi: enable nvme + +Signed-off-by: Peter Robinson +--- + configs/rpi_arm64_defconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 38af5029403..ed4ae6ff522 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -15,7 +15,7 @@ CONFIG_BOOTSTD_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_FDT_SIMPLEFB=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="pci enum; usb start;" ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_SYS_PBSIZE=1049 + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -41,6 +41,7 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_MMC_SDHCI_BCMSTB=y + CONFIG_BCMGENET=y ++CONFIG_NVME_PCI=y + CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set +-- +2.53.0 + diff --git a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch deleted file mode 100644 index a52ce84..0000000 --- a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch +++ /dev/null @@ -1,405 +0,0 @@ -From patchwork Mon Jul 6 17:21:47 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2265604 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gvB431Qwzz1xqc - for ; Tue, 07 Jul 2026 03:21:55 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 179C084942; - Mon, 6 Jul 2026 19:21:52 +0200 (CEST) -Authentication-Results: phobos.denx.de; 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Mon, 6 Jul 2026 19:21:47 +0200 (CEST) -In-Reply-To: <20260706172028.C148E68BEB@verein.lst.de> -References: <20260706172028.C148E68BEB@verein.lst.de> -Subject: [PATCH v2 1/4] core: Skip parent device nodes without a DT reference - when looking for dma-ranges -To: Neil Armstrong , - Andrew Goodbody , Bin Meng , - Simon Glass -Cc: Tom Rini , Matthias Brugger , - Peter Robinson , - Mattijs Korpershoek , - Marek Vasut , - Heiko Schocher , Svyatoslav Ryhel , - "Lucien.Jheng" , Rasmus Villemoes , - Martin Schwan , - "Markus Schneider-Pargmann (TI.com)" , - Prashant Kamble , - Denis Mukhin , Sughosh Ganu , - u-boot@lists.denx.de -Message-Id: <20260706172147.C934268B05@verein.lst.de> -Date: Mon, 6 Jul 2026 19:21:47 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -If a device node got created dynamically, there is no guarantee that the -parent node has an associated device tree node which could specify dma -constraints. Especially PCI(e) enumeration adds intermediate "bus nodes", -also dynamically. - -Try harder to find the correct configuration by walking up the tree until -a DT association is found. - -Suggested-by: Neil Armstrong -Signed-off-by: Torsten Duwe -Reviewed-by: Peter Robinson -Tested-by: Peter Robinson ---- - drivers/core/device.c | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - -diff --git a/drivers/core/device.c b/drivers/core/device.c -index d365204ba11..b6d00cf4714 100644 ---- a/drivers/core/device.c -+++ b/drivers/core/device.c -@@ -459,7 +459,19 @@ static int device_get_dma_constraints(struct udevice *dev) - u64 size = 0; - int ret; - -- if (!CONFIG_IS_ENABLED(DM_DMA) || !parent || !dev_has_ofnode(parent)) -+ if (!CONFIG_IS_ENABLED(DM_DMA) || !parent) -+ return 0; -+ -+ /* Look for the first node in the parent chain */ -+ while (parent) { -+ if (dev_has_ofnode(parent)) -+ break; -+ -+ parent = dev_get_parent(parent); -+ } -+ -+ /* No parents have a node, bail out */ -+ if (!parent) - return 0; - - /* - -From patchwork Mon Jul 6 17:21:50 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2265605 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gvB481pfXz1xqc - for ; Tue, 07 Jul 2026 03:22:00 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 9A59684994; - Mon, 6 Jul 2026 19:21:55 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id EB7D384979; Mon, 6 Jul 2026 19:21:53 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham - autolearn_force=no version=3.4.2 -Received: from verein.lst.de (verein.lst.de [213.95.11.211]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id EE61C846B4 - for ; Mon, 6 Jul 2026 19:21:51 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id 464E868BEB; Mon, 6 Jul 2026 19:21:50 +0200 (CEST) -In-Reply-To: <20260706172028.C148E68BEB@verein.lst.de> -References: <20260706172028.C148E68BEB@verein.lst.de> -Subject: [PATCH v2 2/4] test: Add a unit test in phys_to_bus for dynamically - created device nodes -To: Neil Armstrong , - Andrew Goodbody , Bin Meng , - Simon Glass -Cc: Tom Rini , Matthias Brugger , - Peter Robinson , - Mattijs Korpershoek , - Marek Vasut , - Heiko Schocher , Svyatoslav Ryhel , - "Lucien.Jheng" , Rasmus Villemoes , - Martin Schwan , - "Markus Schneider-Pargmann (TI.com)" , - Prashant Kamble , - Denis Mukhin , Sughosh Ganu , - u-boot@lists.denx.de -Message-Id: <20260706172150.464E868BEB@verein.lst.de> -Date: Mon, 6 Jul 2026 19:21:50 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -In order to test whether device_get_dma_constraints() is now able to skip -device nodes without a DT association, temporarily remove those on 2 newly- -created nodes. - -Signed-off-by: Torsten Duwe ---- - -This test indeed makes a different whether the previous change is -applied or not, but *only* reliably for the non-flat-tree case (!?). -On the flat tree, it always fails after (reverse) applying it. - -Either the previous patch is incomplete, or, more likely, the test -assumptions here are not all valid. Suggestions welcome (especially -how to create device nodes from a device tree without a reference to -their origin ;-) - ---- - arch/sandbox/dts/test.dts | 9 +++++++++ - test/dm/phys2bus.c | 25 ++++++++++++++++++++++++- - 2 files changed, 33 insertions(+), 1 deletion(-) - -diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts -index 0887de4333b..1d92e85c739 100644 ---- a/arch/sandbox/dts/test.dts -+++ b/arch/sandbox/dts/test.dts -@@ -656,6 +656,15 @@ - subnode@0 { - compatible = "denx,u-boot-fdt-test"; - }; -+ bus@7 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "denx,u-boot-test-bus"; -+ -+ subnode@8 { -+ compatible = "denx,u-boot-fdt-test"; -+ }; -+ }; - }; - - mmio-bus@1 { -diff --git a/test/dm/phys2bus.c b/test/dm/phys2bus.c -index 67f33904943..858ed5410e2 100644 ---- a/test/dm/phys2bus.c -+++ b/test/dm/phys2bus.c -@@ -15,7 +15,8 @@ - - static int dm_test_phys_to_bus(struct unit_test_state *uts) - { -- struct udevice *dev; -+ struct udevice *dev, *pdev; -+ ofnode psave, nsave; - ofnode node; - - node = ofnode_path("/mmio-bus@0"); -@@ -31,6 +32,29 @@ static int dm_test_phys_to_bus(struct unit_test_state *uts) - ut_asserteq_addr((void*)0x1003ffffULL, (void*)dev_phys_to_bus(dev, 0x3ffff)); - ut_asserteq_addr((void*)0x3ffffULL, (void*)(ulong)dev_bus_to_phys(dev, 0x1003ffff)); - -+#if CONFIG_IS_ENABLED(OF_REAL) -+ /* dma-ranges are on the grandparent bus node, -+ * OF nodes neither here nor at parent -+ */ -+ node = ofnode_path("/mmio-bus@0/bus@7"); -+ ut_assert(ofnode_valid(node)); -+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_BUS, node, &pdev)); -+ -+ /* pretend the devices were discovered dynamically and have no OF node */ -+ psave = pdev->node_; -+ pdev->node_.np = NULL; -+ node = ofnode_path("/mmio-bus@0/bus@7/subnode@8"); -+ ut_assert(ofnode_valid(node)); -+ nsave = dev->node_; -+ dev->node_.np = NULL; -+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_FDT, node, &dev)); -+ -+ ut_asserteq_addr((void *)0x1003ffffULL, (void *)dev_phys_to_bus(dev, 0x3ffff)); -+ ut_asserteq_addr((void *)0x3ffffULL, (void *)(ulong)dev_bus_to_phys(dev, 0x1003ffff)); -+ -+ pdev->node_ = psave; -+ dev->node_ = nsave; -+#endif - return 0; - } - DM_TEST(dm_test_phys_to_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT); - -From patchwork Mon Jul 6 17:21:54 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2265607 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gvB4R378Lz1xqc - for ; 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usb start;" -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_SYS_PBSIZE=1049 - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -44,6 +44,7 @@ CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_MMC_SDHCI_BCMSTB=y - CONFIG_BCMGENET=y -+CONFIG_NVME_PCI=y - CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set diff --git a/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch b/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch new file mode 100644 index 0000000..f48690e --- /dev/null +++ b/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch @@ -0,0 +1,1527 @@ +From patchwork Thu Feb 12 20:44:55 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196073 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + ffacd0b85a97d-43796ac82f7sm466079f8f.28.2026.02.12.12.45.15 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:15 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 1/7] disk: part_dos: Move header to the main include + directory +Date: Thu, 12 Feb 2026 21:44:55 +0100 +Message-ID: <20260212204511.619392-2-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: IPRNvMIm13yQ-FtMhxNzZkK7Dpa5P_eKViUiJ6XWg7c_1770929117 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +There are two different struct definitions for MBR partition table +entries: one in part_dos.h and a nearly identical one in part_efi.h. + +To enable future consolidation of these two structures, move part_dos.h +to the main include directory. This makes it accessible from other parts +of the codebase, such as part_efi.h, and is the first step toward removing +the redundant definition. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Tom Rini +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_dos.c | 2 +- + {disk => include}/part_dos.h | 0 + 2 files changed, 1 insertion(+), 1 deletion(-) + rename {disk => include}/part_dos.h (100%) + +diff --git a/disk/part_dos.c b/disk/part_dos.c +index 18dd35c9b98e..2545cc6bf5d2 100644 +--- a/disk/part_dos.c ++++ b/disk/part_dos.c +@@ -19,7 +19,7 @@ + #include + #include + #include +-#include "part_dos.h" ++#include + #include + + #define DOS_PART_DEFAULT_SECTOR 512 +diff --git a/disk/part_dos.h b/include/part_dos.h +similarity index 100% +rename from disk/part_dos.h +rename to include/part_dos.h + +From patchwork Thu Feb 12 20:44:56 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196075 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48371a298ebsm1026155e9.13.2026.02.12.12.45.17 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:17 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 2/7] disk: part_dos: Align dos_partition_t with struct + partition +Date: Thu, 12 Feb 2026 21:44:56 +0100 +Message-ID: <20260212204511.619392-3-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: fPt7jBSAujrv4TDFANb7Za8r3XesZKgoNdRV6-QyxLM_1770929120 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The dos_partition_t struct defined in part_dos.h is nearly identical to +the struct partition defined in part_efi.h. They differ primarily in how +define their starting sector and number of sectors fields. + +The former uses unsigned char arrays while the latter uses __le32 types. +Using __le32 is preferable, as it removes the ambiguity and potential +misuse of a raw byte array. This also aligns the structure with how the +Linux kernel defines it nowadays, which is the original source of it. + +To prepare for future consolidation where one of the data structures can +be removed, this change aligns both definitions and updates all accessors +for dos_partition_t. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Tom Rini +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_dos.c | 16 ++++++++-------- + include/part_dos.h | 6 +++--- + 2 files changed, 11 insertions(+), 11 deletions(-) + +diff --git a/disk/part_dos.c b/disk/part_dos.c +index 2545cc6bf5d2..60c3d6773696 100644 +--- a/disk/part_dos.c ++++ b/disk/part_dos.c +@@ -49,8 +49,8 @@ static int get_bootable(dos_partition_t *p) + static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector, + int part_num, unsigned int disksig) + { +- lbaint_t lba_start = ext_part_sector + get_unaligned_le32(p->start4); +- lbaint_t lba_size = get_unaligned_le32(p->size4); ++ lbaint_t lba_start = ext_part_sector + get_unaligned_le32(&p->start_sect); ++ lbaint_t lba_size = get_unaligned_le32(&p->nr_sects); + + printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength + "u\t%08x-%02x\t%02x%s%s\n", +@@ -185,7 +185,7 @@ static void print_partition_extended(struct blk_desc *desc, + for (i = 0; i < 4; i++, pt++) { + if (is_extended (pt->sys_ind)) { + lbaint_t lba_start +- = get_unaligned_le32 (pt->start4) + relative; ++ = get_unaligned_le32 (&pt->start_sect) + relative; + + print_partition_extended(desc, lba_start, + !ext_part_sector ? lba_start : +@@ -252,8 +252,8 @@ static int part_get_info_extended(struct blk_desc *desc, + else + info->blksz = DOS_PART_DEFAULT_SECTOR; + info->start = (lbaint_t)(ext_part_sector + +- get_unaligned_le32(pt->start4)); +- info->size = (lbaint_t)get_unaligned_le32(pt->size4); ++ get_unaligned_le32(&pt->start_sect)); ++ info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); + part_set_generic_name(desc, part_num, + (char *)info->name); + /* sprintf(info->type, "%d, pt->sys_ind); */ +@@ -281,7 +281,7 @@ static int part_get_info_extended(struct blk_desc *desc, + for (i = 0; i < 4; i++, pt++) { + if (is_extended (pt->sys_ind)) { + lbaint_t lba_start +- = get_unaligned_le32 (pt->start4) + relative; ++ = get_unaligned_le32 (&pt->start_sect) + relative; + + return part_get_info_extended(desc, lba_start, + ext_part_sector == 0 ? lba_start : relative, +@@ -356,8 +356,8 @@ static void mbr_fill_pt_entry(dos_partition_t *pt, lbaint_t start, + pt->sys_ind = sys_ind; + lba_to_chs(start, &pt->cyl, &pt->head, &pt->sector); + lba_to_chs(start + size - 1, &pt->end_cyl, &pt->end_head, &pt->end_sector); +- put_unaligned_le32(relative, &pt->start4); +- put_unaligned_le32(size, &pt->size4); ++ put_unaligned_le32(relative, &pt->start_sect); ++ put_unaligned_le32(size, &pt->nr_sects); + } + + int write_mbr_partitions(struct blk_desc *dev, +diff --git a/include/part_dos.h b/include/part_dos.h +index 505582242281..92956d530637 100644 +--- a/include/part_dos.h ++++ b/include/part_dos.h +@@ -30,8 +30,8 @@ typedef struct dos_partition { + unsigned char end_head; /* end head */ + unsigned char end_sector; /* end sector */ + unsigned char end_cyl; /* end cylinder */ +- unsigned char start4[4]; /* starting sector counting from 0 */ +- unsigned char size4[4]; /* nr of sectors in partition */ +-} dos_partition_t; ++ __le32 start_sect; /* starting sector counting from 0 */ ++ __le32 nr_sects; /* nr of sectors in partition */ ++} __packed dos_partition_t; + + #endif /* _DISK_PART_DOS_H */ + +From patchwork Thu Feb 12 20:44:57 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196076 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (1024-bit key; + unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 + header.s=mimecast20190719 header.b=BA1s+RGr; + dkim-atps=neutral +Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48370a3ecadsm3205185e9.3.2026.02.12.12.45.19 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:20 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 3/7] disk: part_efi: Remove redundant struct partition + definition +Date: Thu, 12 Feb 2026 21:44:57 +0100 +Message-ID: <20260212204511.619392-4-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: waoFTyp5Nb4lUw3OUZ2FyujC5g1lrXxsAubBNTuInkI_1770929122 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +Now that dos_partition_t and struct partition are identical, the duplicated +data structure definition in the part_efi.h header can just be removed. + +This results in a single, shared definition for MBR partition table +entries, instead of having the same definition in two different places. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Tom Rini +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_efi.c | 4 ++-- + include/part_efi.h | 19 +++---------------- + 2 files changed, 5 insertions(+), 18 deletions(-) + +diff --git a/disk/part_efi.c b/disk/part_efi.c +index fb1ed534f861..d8b17ec2e91a 100644 +--- a/disk/part_efi.c ++++ b/disk/part_efi.c +@@ -51,7 +51,7 @@ static inline u32 efi_crc32(const void *buf, u32 len) + * Private function prototypes + */ + +-static int pmbr_part_valid(struct partition *part); ++static int pmbr_part_valid(dos_partition_t *part); + static int is_pmbr_valid(legacy_mbr * mbr); + static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head, + gpt_entry **pgpt_pte); +@@ -990,7 +990,7 @@ int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf) + * + * Returns: 1 if EFI GPT partition type is found. + */ +-static int pmbr_part_valid(struct partition *part) ++static int pmbr_part_valid(dos_partition_t *part) + { + if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && + get_unaligned_le32(&part->start_sect) == 1UL) { +diff --git a/include/part_efi.h b/include/part_efi.h +index fb402df6f13e..2cea50880465 100644 +--- a/include/part_efi.h ++++ b/include/part_efi.h +@@ -18,6 +18,7 @@ + #define _DISK_PART_EFI_H + + #include ++#include + + #define MSDOS_MBR_SIGNATURE 0xAA55 + #define MSDOS_MBR_BOOT_CODE_SIZE 440 +@@ -77,20 +78,6 @@ + /* linux/include/efi.h */ + typedef u16 efi_char16_t; + +-/* based on linux/include/genhd.h */ +-struct partition { +- u8 boot_ind; /* 0x80 - active */ +- u8 head; /* starting head */ +- u8 sector; /* starting sector */ +- u8 cyl; /* starting cylinder */ +- u8 sys_ind; /* What partition type */ +- u8 end_head; /* end head */ +- u8 end_sector; /* end sector */ +- u8 end_cyl; /* end cylinder */ +- __le32 start_sect; /* starting sector counting from 0 */ +- __le32 nr_sects; /* nr of sectors in partition */ +-} __packed; +- + /* based on linux/fs/partitions/efi.h */ + typedef struct _gpt_header { + __le64 signature; +@@ -134,7 +121,7 @@ typedef struct _legacy_mbr { + u8 boot_code[MSDOS_MBR_BOOT_CODE_SIZE]; + __le32 unique_mbr_signature; + __le16 unknown; +- struct partition partition_record[4]; ++ dos_partition_t partition_record[4]; + __le16 signature; + } __packed legacy_mbr; + +@@ -153,7 +140,7 @@ struct efi_partition_info { + u8 system; + u8 reserved[7]; + union { +- struct partition mbr; ++ dos_partition_t mbr; + gpt_entry gpt; + } info; + } __packed; + +From patchwork Thu Feb 12 20:44:58 2026 +Content-Type: text/plain; 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+ } + +-/* Print a partition that is relative to its Extended partition table ++/** ++ * part_get_info_extended() - get partition info for a DOS partition ++ * ++ * @desc: Block device descriptor ++ * @ext_part_sector: Partition table sector ++ * @relative: Relative offset for the partition ++ * @part_num: Current partition number ++ * @which_part: Target partition number ++ * @info: Returns a pointer to the partition info ++ * @disksig: Disk signature ++ * ++ * Return: 0 on success, negative on error + */ + static int part_get_info_extended(struct blk_desc *desc, + lbaint_t ext_part_sector, lbaint_t relative, + +From patchwork Thu Feb 12 20:44:59 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196079 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-4835dcfaae1sm112461635e9.10.2026.02.12.12.45.24 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:24 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas , + Casey Connolly , + Jan Kiszka , Javier Tia , + Rasmus Villemoes , + Varadarajan Narayanan +Subject: [PATCH v2 5/7] disk: part_dos: Refactor to allow retrieving raw MBR + partition data +Date: Thu, 12 Feb 2026 21:44:59 +0100 +Message-ID: <20260212204511.619392-6-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: Zs6NXSgdnPvAWNkwYY8acCGlkSTO_JLJJjyY6Cc_c5o_1770929127 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +Refactor the part_get_info_extended() helper function (which already +recursively traverses DOS partitions) to optionally return the raw MBR +partition structure (dos_partition_t). + +This allows other subsystems, such as EFI, to retrieve the partition +details in the legacy MBR format. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_dos.c | 66 ++++++++++++++++++++++++++++++------------------- + include/part.h | 14 +++++++++++ + 2 files changed, 55 insertions(+), 25 deletions(-) + +diff --git a/disk/part_dos.c b/disk/part_dos.c +index a69ad8962106..4e1d01b2f21e 100644 +--- a/disk/part_dos.c ++++ b/disk/part_dos.c +@@ -204,7 +204,8 @@ static void print_partition_extended(struct blk_desc *desc, + * @relative: Relative offset for the partition + * @part_num: Current partition number + * @which_part: Target partition number +- * @info: Returns a pointer to the partition info ++ * @info: Returns partition information (optional) ++ * @mbr: Returns MBR partition entry (optional) + * @disksig: Disk signature + * + * Return: 0 on success, negative on error +@@ -212,7 +213,9 @@ static void print_partition_extended(struct blk_desc *desc, + static int part_get_info_extended(struct blk_desc *desc, + lbaint_t ext_part_sector, lbaint_t relative, + int part_num, int which_part, +- struct disk_partition *info, uint disksig) ++ struct disk_partition *info, ++ dos_partition_t *mbr, ++ uint disksig) + { + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz); + struct disk_partition wdinfo = { 0 }; +@@ -243,9 +246,11 @@ static int part_get_info_extended(struct blk_desc *desc, + if (CONFIG_IS_ENABLED(PARTITION_UUIDS) && !ext_part_sector) + disksig = get_unaligned_le32(&buffer[DOS_PART_DISKSIG_OFFSET]); + +- ret = part_get_info_whole_disk(desc, &wdinfo); +- if (ret) +- return ret; ++ if (info) { ++ ret = part_get_info_whole_disk(desc, &wdinfo); ++ if (ret) ++ return ret; ++ } + + /* Print all primary/logical partitions */ + pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); +@@ -258,25 +263,29 @@ static int part_get_info_extended(struct blk_desc *desc, + (pt->sys_ind != 0) && + (part_num == which_part) && + (ext_part_sector == 0 || is_extended(pt->sys_ind) == 0)) { +- if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) +- info->blksz = wdinfo.blksz; +- else +- info->blksz = DOS_PART_DEFAULT_SECTOR; +- info->start = (lbaint_t)(ext_part_sector + +- get_unaligned_le32(&pt->start_sect)); +- info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); +- part_set_generic_name(desc, part_num, +- (char *)info->name); +- /* sprintf(info->type, "%d, pt->sys_ind); */ +- strcpy((char *)info->type, "U-Boot"); +- info->bootable = get_bootable(pt); +- if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { +- char str[12]; +- +- sprintf(str, "%08x-%02x", disksig, part_num); +- disk_partition_set_uuid(info, str); ++ if (info) { ++ if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) ++ info->blksz = wdinfo.blksz; ++ else ++ info->blksz = DOS_PART_DEFAULT_SECTOR; ++ info->start = (lbaint_t)(ext_part_sector + ++ get_unaligned_le32(&pt->start_sect)); ++ info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); ++ part_set_generic_name(desc, part_num, ++ (char *)info->name); ++ /* sprintf(info->type, "%d, pt->sys_ind); */ ++ strcpy((char *)info->type, "U-Boot"); ++ info->bootable = get_bootable(pt); ++ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { ++ char str[12]; ++ ++ sprintf(str, "%08x-%02x", disksig, part_num); ++ disk_partition_set_uuid(info, str); ++ } ++ info->sys_ind = pt->sys_ind; + } +- info->sys_ind = pt->sys_ind; ++ if (mbr) ++ memcpy(mbr, pt, sizeof(*mbr)); + return 0; + } + +@@ -296,7 +305,8 @@ static int part_get_info_extended(struct blk_desc *desc, + + return part_get_info_extended(desc, lba_start, + ext_part_sector == 0 ? lba_start : relative, +- part_num, which_part, info, disksig); ++ part_num, which_part, info, ++ mbr, disksig); + } + } + +@@ -328,7 +338,13 @@ static void __maybe_unused part_print_dos(struct blk_desc *desc) + static int __maybe_unused part_get_info_dos(struct blk_desc *desc, int part, + struct disk_partition *info) + { +- return part_get_info_extended(desc, 0, 0, 1, part, info, 0); ++ return part_get_info_extended(desc, 0, 0, 1, part, info, NULL, 0); ++} ++ ++int __maybe_unused part_get_mbr(struct blk_desc *desc, int part, ++ dos_partition_t *mbr) ++{ ++ return part_get_info_extended(desc, 0, 0, 1, part, NULL, mbr, 0); + } + + int is_valid_dos_buf(void *buf) +diff --git a/include/part.h b/include/part.h +index daebbbc2e68f..aed089d00f64 100644 +--- a/include/part.h ++++ b/include/part.h +@@ -704,6 +704,20 @@ int write_mbr_partitions(struct blk_desc *dev, + int layout_mbr_partitions(struct disk_partition *p, int count, + lbaint_t total_sectors); + ++/** ++ * part_get_mbr() - get the MBR partition record of a partition ++ * ++ * This function reads the MBR partition record for a given block ++ * device and partition number. ++ * ++ * @desc: block device descriptor ++ * @part: partition number for which to return the partition record ++ * @mbr: MBR partition record ++ * ++ * Return: 0 on success, otherwise error ++ */ ++int part_get_mbr(struct blk_desc *desc, int part, dos_partition_t *mbr); ++ + #endif + + #if CONFIG_IS_ENABLED(PARTITIONS) + +From patchwork Thu Feb 12 20:45:00 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196081 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (1024-bit key; + unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 + header.s=mimecast20190719 header.b=CXh1R16n; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48371a49dc7sm790085e9.31.2026.02.12.12.45.27 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:27 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas , + Maks Mishin , Simon Glass +Subject: [PATCH v2 6/7] efi_loader: disk: Extend EFI_PARTITION_INFO_PROTOCOL + to support MBR +Date: Thu, 12 Feb 2026 21:45:00 +0100 +Message-ID: <20260212204511.619392-7-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: We4wNEbtQuTUTq6Fkgi3HWr3Fx0Twiws4fhF79FLAjg_1770929129 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The EFI_PARTITION_INFO_PROTOCOL provides detailed information about +partitions. The UEFI specification mentions that both GPT and MBR +partition schemes are supported, but the U-Boot implementation only +supports the former. + +This can cause compatibility issues for platforms whose boot ROM only +supports MBR. This change adds support for MBR partition tables to +the protocol, making U-Boot compatible with systems that require a +legacy MBR table. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + lib/efi_loader/efi_disk.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c +index 130c4db9606f..f8a57539ec61 100644 +--- a/lib/efi_loader/efi_disk.c ++++ b/lib/efi_loader/efi_disk.c +@@ -475,9 +475,12 @@ static efi_status_t efi_disk_add_dev( + #if CONFIG_IS_ENABLED(DOS_PARTITION) + case PART_TYPE_DOS: + info->type = PARTITION_TYPE_MBR; +- +- /* TODO: implement support for MBR partition types */ +- log_debug("EFI_PARTITION_INFO_PROTOCOL doesn't support MBR\n"); ++ ret = part_get_mbr(desc, part, &info->info.mbr); ++ if (ret) { ++ log_debug("get MBR for part %d failed %ld\n", ++ part, ret); ++ goto error; ++ } + break; + #endif + default: + +From patchwork Thu Feb 12 20:45:01 2026 +Content-Type: text/plain; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48370ac3564sm6753225e9.5.2026.02.12.12.45.29 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:29 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 7/7] efi_selftest: Enhance MBR test for + PARTITION_INFO_PROTOCOL +Date: Thu, 12 Feb 2026 21:45:01 +0100 +Message-ID: <20260212204511.619392-8-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: yunYq1YIsh16Z4DQJL5hOi7pdkGhTA9a43HFld0F1eg_1770929132 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The EFI_PARTITION_INFO_PROTOCOL test was added before the protocol fully +supported MBR partitions. As a result, it lacked specific checks for the +content of the raw MBR partition record. + +Now that MBR support has been implemented, enhance the selftest to provide +coverage for the MBR entries too. + +This verifies that the protocol correctly reads and exposes MBR partition +records and prevents this functionality to regress due future changes. + +Signed-off-by: Javier Martinez Canillas +Acked-by: Ilias Apalodimas +Reviewed-by: Heinrich Schuchardt +--- + +(no changes since v1) + + lib/efi_selftest/efi_selftest_block_device.c | 26 ++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c +index f145e58a267a..9c4be834eebb 100644 +--- a/lib/efi_selftest/efi_selftest_block_device.c ++++ b/lib/efi_selftest/efi_selftest_block_device.c +@@ -19,6 +19,7 @@ + #include "efi_selftest_disk_image.h" + #include + #include ++#include + + /* Block size of compressed disk image */ + #define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8 +@@ -319,6 +320,25 @@ static int execute(void) + u64 pos; + char block_io_aligned[1 << LB_BLOCK_SIZE] __aligned(1 << LB_BLOCK_SIZE); + ++ /* ++ * The test disk image is defined in efi_selftest_disk_image.h, ++ * it contains a single FAT12 partition of 127 sectors size. ++ */ ++ static const dos_partition_t mbr_expected = { ++ .boot_ind = 0x00, ++ .head = 0x00, ++ .sector = 0x02, ++ .cyl = 0x00, ++ .sys_ind = 0x01, /* FAT12 */ ++ .end_head = 0x02, ++ .end_sector = 0x02, ++ .end_cyl = 0x00, ++ /* LBA 1 */ ++ .start_sect = cpu_to_le32(1), ++ /* Size 127 sectors (0x7f) */ ++ .nr_sects = cpu_to_le32(127), ++ }; ++ + /* Connect controller to virtual disk */ + ret = boottime->connect_controller(disk_handle, NULL, NULL, 1); + if (ret != EFI_SUCCESS) { +@@ -405,6 +425,12 @@ static int execute(void) + return EFI_ST_FAILURE; + } + ++ /* Compare the obtained MBR with the expected one for the test partition */ ++ if (memcmp(&part_info->info.mbr, &mbr_expected, sizeof(mbr_expected))) { ++ efi_st_error("MBR partition record mismatch\n"); ++ return EFI_ST_FAILURE; ++ } ++ + /* Open the simple file system protocol */ + ret = boottime->open_protocol(handle_partition, + &guid_simple_file_system_protocol, diff --git a/rockchip-Enable-preboot-start-for-pci-usb.patch b/rockchip-Enable-preboot-start-for-pci-usb.patch index 30aad4d..155c570 100644 --- a/rockchip-Enable-preboot-start-for-pci-usb.patch +++ b/rockchip-Enable-preboot-start-for-pci-usb.patch @@ -1,6 +1,6 @@ -From a6909a16b4cc301f1007d9e75d02abb6d06a1ea7 Mon Sep 17 00:00:00 2001 +From 020f67a37342b091c74dab93a133253401d4d899 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Thu, 28 May 2026 21:29:29 +0100 +Date: Tue, 31 Dec 2024 14:15:41 +0000 Subject: [PATCH] rockchip: Enable preboot start for pci/usb Enable the preboot so nvme works OOTB @@ -29,18 +29,14 @@ Signed-off-by: Peter Robinson configs/neu6b-io-rk3588_defconfig | 2 ++ configs/nova-rk3588s_defconfig | 2 ++ configs/odroid-m1-rk3568_defconfig | 2 ++ - configs/odroid-m1s-rk3566_defconfig | 2 ++ - configs/odroid-m2-rk3588s_defconfig | 2 ++ configs/orangepi-3b-rk3566_defconfig | 2 ++ - configs/orangepi-5-max-rk3588_defconfig | 2 ++ configs/orangepi-5-plus-rk3588_defconfig | 2 ++ configs/orangepi-5-rk3588s_defconfig | 2 ++ - configs/orangepi-5-ultra-rk3588_defconfig | 2 ++ configs/pinebook-pro-rk3399_defconfig | 1 + configs/pinetab2-rk3566_defconfig | 2 ++ configs/powkiddy-x55-rk3566_defconfig | 2 ++ configs/quartz64-a-rk3566_defconfig | 2 ++ - configs/quartz64-b-rk3566_defconfig | 4 ++++ + configs/quartz64-b-rk3566_defconfig | 2 ++ configs/quartzpro64-rk3588_defconfig | 2 ++ configs/radxa-cm3-io-rk3566_defconfig | 2 ++ configs/radxa-e25-rk3568_defconfig | 2 ++ @@ -52,7 +48,6 @@ Signed-off-by: Peter Robinson configs/rock-4c-plus-rk3399_defconfig | 2 ++ configs/rock-4se-rk3399_defconfig | 2 ++ configs/rock-5-itx-rk3588_defconfig | 2 ++ - configs/rock-5c-rk3588s_defconfig | 2 ++ configs/rock-pi-4-rk3399_defconfig | 2 ++ configs/rock-pi-4c-rk3399_defconfig | 2 ++ configs/rock-pi-n10-rk3399pro_defconfig | 2 ++ @@ -67,10 +62,10 @@ Signed-off-by: Peter Robinson configs/tiger-rk3588_defconfig | 2 ++ configs/toybrick-rk3588_defconfig | 2 ++ configs/turing-rk1-rk3588_defconfig | 2 ++ - 60 files changed, 121 insertions(+) + 55 files changed, 109 insertions(+) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig -index 854de8b00a4..cd91f18ba80 100644 +index 14c97b4c5bf..de92e1b4141 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -12,6 +12,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -83,7 +78,7 @@ index 854de8b00a4..cd91f18ba80 100644 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig -index c5199a39448..603e07f2456 100644 +index d84ea2f955f..de777817c37 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -92,11 +87,11 @@ index c5199a39448..603e07f2456 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/cm3588-nas-rk3588_defconfig b/configs/cm3588-nas-rk3588_defconfig -index 5b5ef8d5ac1..53147d115dd 100644 +index fd0a32d6d79..e561be511d4 100644 --- a/configs/cm3588-nas-rk3588_defconfig +++ b/configs/cm3588-nas-rk3588_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -109,7 +104,7 @@ index 5b5ef8d5ac1..53147d115dd 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig -index e6772622403..75e0b373ce9 100644 +index ea985b81670..96d7cffb075 100644 --- a/configs/coolpi-4b-rk3588s_defconfig +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -118,11 +113,11 @@ index e6772622403..75e0b373ce9 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig -index 4326e116849..a005e4441d3 100644 +index 58ffe7baf5f..5eadc091242 100644 --- a/configs/coolpi-cm5-evb-rk3588_defconfig +++ b/configs/coolpi-cm5-evb-rk3588_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -131,11 +126,11 @@ index 4326e116849..a005e4441d3 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig -index 4a5a7454e10..7ec199a08af 100644 +index a068bc6846c..8c94f7b21bc 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -148,7 +143,7 @@ index 4a5a7454e10..7ec199a08af 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig -index c7f6256a626..cfa73c660e7 100644 +index 3d4d2747145..051015fd811 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -161,7 +156,7 @@ index c7f6256a626..cfa73c660e7 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig -index 83b9de5feb9..2ba8f5029c3 100644 +index 3871627318b..b96aadc78eb 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -174,7 +169,7 @@ index 83b9de5feb9..2ba8f5029c3 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig -index a33c3af9255..20966793568 100644 +index f79f0e84400..ba5339a004f 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -187,7 +182,7 @@ index a33c3af9255..20966793568 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig -index ac450e6d757..b5424ac9f16 100644 +index 51e31dce3a9..1c767caa06a 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -200,7 +195,7 @@ index ac450e6d757..b5424ac9f16 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig -index ed3883b4f9c..47dbd834f30 100644 +index 6e853991d1d..a5a56a33d09 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -16,6 +16,8 @@ CONFIG_DEBUG_UART_BASE=0xfeb50000 @@ -213,7 +208,7 @@ index ed3883b4f9c..47dbd834f30 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig -index 7548bf60b06..2fb8a432503 100644 +index 46cc3c03fff..8915d5bfba9 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -226,10 +221,10 @@ index 7548bf60b06..2fb8a432503 100644 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig -index f8ae436a1ee..7aa8e1a8d42 100644 +index 26c12c51078..33f7e838c2c 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig -@@ -15,6 +15,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 +@@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y @@ -239,7 +234,7 @@ index f8ae436a1ee..7aa8e1a8d42 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig -index ba9a5adece7..eaf7fa5a0fc 100644 +index 772b7df1555..ba6cf48308c 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -252,7 +247,7 @@ index ba9a5adece7..eaf7fa5a0fc 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig -index e75a24dadc8..159ef033932 100644 +index 4a43b17ccb1..91c95b491d5 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -265,7 +260,7 @@ index e75a24dadc8..159ef033932 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig -index c971f376b38..60b5e8fa014 100644 +index a60d229fbbf..355d8114a9b 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -278,7 +273,7 @@ index c971f376b38..60b5e8fa014 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r6c-rk3588s_defconfig b/configs/nanopi-r6c-rk3588s_defconfig -index 861e3234d29..bb6e2082e3b 100644 +index c4de5518a72..92697c536d9 100644 --- a/configs/nanopi-r6c-rk3588s_defconfig +++ b/configs/nanopi-r6c-rk3588s_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -291,7 +286,7 @@ index 861e3234d29..bb6e2082e3b 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r6s-rk3588s_defconfig b/configs/nanopi-r6s-rk3588s_defconfig -index 743dfca441b..903ec56ad6f 100644 +index 2726729b9ac..63a3690db8e 100644 --- a/configs/nanopi-r6s-rk3588s_defconfig +++ b/configs/nanopi-r6s-rk3588s_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -304,7 +299,7 @@ index 743dfca441b..903ec56ad6f 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig -index 19f129e96f0..08ed699b01d 100644 +index 291e0d26d42..e385aba7bc4 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -317,7 +312,7 @@ index 19f129e96f0..08ed699b01d 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig -index 2cf5aeccf51..8cafd779a1c 100644 +index 4e22852f23c..79f4e66cb9b 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -330,7 +325,7 @@ index 2cf5aeccf51..8cafd779a1c 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig -index f7d7492ff46..5abb6ebbe18 100644 +index fb30dfd1db8..e99898355e1 100644 --- a/configs/nova-rk3588s_defconfig +++ b/configs/nova-rk3588s_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -343,7 +338,7 @@ index f7d7492ff46..5abb6ebbe18 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig -index b00985b0405..19d7af53c7f 100644 +index a8e8a8781e1..a3ea2e592b9 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -352,37 +347,11 @@ index b00985b0405..19d7af53c7f 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y -diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig -index d59882a2a59..20f6dc3c26e 100644 ---- a/configs/odroid-m1s-rk3566_defconfig -+++ b/configs/odroid-m1s-rk3566_defconfig -@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 - CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_PCI=y - CONFIG_DEBUG_UART=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y -diff --git a/configs/odroid-m2-rk3588s_defconfig b/configs/odroid-m2-rk3588s_defconfig -index e71e61ddb0b..561c2b28b7a 100644 ---- a/configs/odroid-m2-rk3588s_defconfig -+++ b/configs/odroid-m2-rk3588s_defconfig -@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 - CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_PCI=y - CONFIG_DEBUG_UART=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/orangepi-3b-rk3566_defconfig b/configs/orangepi-3b-rk3566_defconfig -index 1cd78789fa1..dcf182231da 100644 +index 2181c9caf58..fee0c719f25 100644 --- a/configs/orangepi-3b-rk3566_defconfig +++ b/configs/orangepi-3b-rk3566_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -391,24 +360,11 @@ index 1cd78789fa1..dcf182231da 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y -diff --git a/configs/orangepi-5-max-rk3588_defconfig b/configs/orangepi-5-max-rk3588_defconfig -index 0861df962cf..744aad89c4a 100644 ---- a/configs/orangepi-5-max-rk3588_defconfig -+++ b/configs/orangepi-5-max-rk3588_defconfig -@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y - CONFIG_SPL_SPI=y - CONFIG_PCI=y - CONFIG_DEBUG_UART=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig -index 52523f87aec..e3bb4e43da9 100644 +index 9050fceda45..2e1fe2c6dc5 100644 --- a/configs/orangepi-5-plus-rk3588_defconfig +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -417,11 +373,11 @@ index 52523f87aec..e3bb4e43da9 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig -index e0eba389289..33fe68add7b 100644 +index 6e2ff7d338a..7ec7d13e1f9 100644 --- a/configs/orangepi-5-rk3588s_defconfig +++ b/configs/orangepi-5-rk3588s_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -430,24 +386,11 @@ index e0eba389289..33fe68add7b 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y -diff --git a/configs/orangepi-5-ultra-rk3588_defconfig b/configs/orangepi-5-ultra-rk3588_defconfig -index fb7f4432983..62419609695 100644 ---- a/configs/orangepi-5-ultra-rk3588_defconfig -+++ b/configs/orangepi-5-ultra-rk3588_defconfig -@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y - CONFIG_SPL_SPI=y - CONFIG_PCI=y - CONFIG_DEBUG_UART=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index cbf95b4692f..9e4d1b1061d 100644 +index dfa927ccb17..acc2a0a9fcd 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -22,6 +22,7 @@ CONFIG_PCI=y @@ -459,7 +402,7 @@ index cbf95b4692f..9e4d1b1061d 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig -index f284dadb99d..d87849f0a45 100644 +index 45e63b42d19..3ef0ddbbe31 100644 --- a/configs/pinetab2-rk3566_defconfig +++ b/configs/pinetab2-rk3566_defconfig @@ -18,6 +18,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -472,7 +415,7 @@ index f284dadb99d..d87849f0a45 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/powkiddy-x55-rk3566_defconfig b/configs/powkiddy-x55-rk3566_defconfig -index 37a359c91a9..70bc5ab6402 100644 +index 85280839889..f93a463087b 100644 --- a/configs/powkiddy-x55-rk3566_defconfig +++ b/configs/powkiddy-x55-rk3566_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -485,7 +428,7 @@ index 37a359c91a9..70bc5ab6402 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig -index 780fd581f0a..7938b5c0d1b 100644 +index fe3fa37611a..60b1f8f1784 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -494,31 +437,24 @@ index 780fd581f0a..7938b5c0d1b 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig -index 4d92a67cd73..fe8a168373d 100644 +index 929736f76af..c3155d9b835 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig -@@ -1,4 +1,6 @@ - CONFIG_ARM=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_SKIP_LOWLEVEL_INIT=y - CONFIG_COUNTER_FREQUENCY=24000000 - CONFIG_ARCH_ROCKCHIP=y -@@ -17,6 +19,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y +@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig -index 0ad74e8bbef..b9cbddfae77 100644 +index ade7be27e92..263d21bee8b 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -527,11 +463,11 @@ index 0ad74e8bbef..b9cbddfae77 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig -index 875f0b76fa5..2523dccd6a3 100644 +index 2655fdc3170..c1a27f6e310 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -544,7 +480,7 @@ index 875f0b76fa5..2523dccd6a3 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig -index 779d540e22d..7e003e74520 100644 +index 4df594ddc01..3830d27b264 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -553,11 +489,11 @@ index 779d540e22d..7e003e74520 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/radxa-zero-3-rk3566_defconfig b/configs/radxa-zero-3-rk3566_defconfig -index f5cf09a5e4a..7db7e3fcd3d 100644 +index 5989b07ad79..1b571ec3847 100644 --- a/configs/radxa-zero-3-rk3566_defconfig +++ b/configs/radxa-zero-3-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -570,7 +506,7 @@ index f5cf09a5e4a..7db7e3fcd3d 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig -index 8b4d8c1b0aa..54baa07aeae 100644 +index 3ab5fd69c62..ba254d8f6c0 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -21,6 +21,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -583,7 +519,7 @@ index 8b4d8c1b0aa..54baa07aeae 100644 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig -index e753185610f..19d303e7f70 100644 +index 733ce631457..3387796a0c5 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -592,11 +528,11 @@ index e753185610f..19d303e7f70 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-3b-rk3568_defconfig b/configs/rock-3b-rk3568_defconfig -index c3bf48b9e34..0cfa8eba168 100644 +index 2023feb36c2..84c6aab6b33 100644 --- a/configs/rock-3b-rk3568_defconfig +++ b/configs/rock-3b-rk3568_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -605,11 +541,11 @@ index c3bf48b9e34..0cfa8eba168 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig -index 417aa33a663..61d0e1b8c6a 100644 +index 2528c7c639c..0a0010b1268 100644 --- a/configs/rock-3c-rk3566_defconfig +++ b/configs/rock-3c-rk3566_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -618,11 +554,11 @@ index 417aa33a663..61d0e1b8c6a 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig -index 0f6bdfdfb06..f31cb061a83 100644 +index 0c73a212ea1..2ae2eff39e2 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -635,7 +571,7 @@ index 0f6bdfdfb06..f31cb061a83 100644 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig -index 7f22aede912..caf8e02bece 100644 +index 3ae19692155..12621b8a41b 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -644,11 +580,11 @@ index 7f22aede912..caf8e02bece 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y - # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig -index cb014de4188..e26a126533c 100644 +index d0dd1c20ece..b3a778907c8 100644 --- a/configs/rock-5-itx-rk3588_defconfig +++ b/configs/rock-5-itx-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -657,24 +593,11 @@ index cb014de4188..e26a126533c 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y -diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig -index 3d044a81498..27234c250d1 100644 ---- a/configs/rock-5c-rk3588s_defconfig -+++ b/configs/rock-5c-rk3588s_defconfig -@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 - CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_PCI=y - CONFIG_DEBUG_UART=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig -index e5c9072c27f..35852c017da 100644 +index f3a5c2c45f3..d95576e804a 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -683,11 +606,11 @@ index e5c9072c27f..35852c017da 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y - # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig -index 4be7b0f8130..eeee446a5bd 100644 +index 9bda50c8c77..d26eb3dcb44 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -696,11 +619,11 @@ index 4be7b0f8130..eeee446a5bd 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y - # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig -index 602a723ea7d..3dcc2932ae3 100644 +index a9c6d8a907a..1cde3859eef 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -13,6 +13,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -713,7 +636,7 @@ index 602a723ea7d..3dcc2932ae3 100644 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig -index 24b2eef35f2..c5830054921 100644 +index 9618d590009..9608f7e7e4c 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -726,7 +649,7 @@ index 24b2eef35f2..c5830054921 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig -index da5fb3a2c30..053346fc035 100644 +index 47ee2109f8e..e1c6961a3ab 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -735,11 +658,11 @@ index da5fb3a2c30..053346fc035 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -index db121f03ae6..e55f1b6a034 100644 +index aebfa73459c..8b60ad3bf00 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -752,7 +675,7 @@ index db121f03ae6..e55f1b6a034 100644 CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig -index 1d2bff35fc0..ea8e90b9f6a 100644 +index 08b7e2784e9..d80e120c66f 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -765,7 +688,7 @@ index 1d2bff35fc0..ea8e90b9f6a 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig -index 00b9759715b..1b837bd554c 100644 +index 8b033e22b84..978df10442c 100644 --- a/configs/sige7-rk3588_defconfig +++ b/configs/sige7-rk3588_defconfig @@ -13,6 +13,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -774,11 +697,11 @@ index 00b9759715b..1b837bd554c 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig -index 7de159a8881..4137f0459b5 100644 +index a1a51b2c657..4083f217c0b 100644 --- a/configs/soquartz-blade-rk3566_defconfig +++ b/configs/soquartz-blade-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -787,11 +710,11 @@ index 7de159a8881..4137f0459b5 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig -index 4455ee5b5aa..ad63ba0204f 100644 +index a8bca0eaccc..c3dd48d9dc1 100644 --- a/configs/soquartz-cm4-rk3566_defconfig +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -800,11 +723,11 @@ index 4455ee5b5aa..ad63ba0204f 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig -index abdab514496..9e01345bdaa 100644 +index f080d2e36d2..f6f2f67b0a6 100644 --- a/configs/soquartz-model-a-rk3566_defconfig +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -813,11 +736,11 @@ index abdab514496..9e01345bdaa 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig -index 105e8e10e0b..bcc2ae302a5 100644 +index f962ac416f3..1fc7301f6ae 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -830,7 +753,7 @@ index 105e8e10e0b..bcc2ae302a5 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig -index 14b231ae3e2..7af393731cd 100644 +index 5e70341c987..fd7e842f9e5 100644 --- a/configs/toybrick-rk3588_defconfig +++ b/configs/toybrick-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -843,7 +766,7 @@ index 14b231ae3e2..7af393731cd 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig -index 0b3efec23e6..515db2a2b0c 100644 +index 0eddf15833c..1a9aacc7b5d 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEBC0000 @@ -852,9 +775,9 @@ index 0b3efec23e6..515db2a2b0c 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y - CONFIG_SPL_FIT_SIGNATURE=y -- -2.54.0 +2.47.1 diff --git a/rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch b/rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch 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u-boot@lists.u-boot-project.org -X-Mailman-Version: 2.1.30 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.u-boot-project.org -Sender: "U-Boot" - -The Raspberry Pi has the "tryboot" feature where it can boot from a -different partition enabling failsafe A/B updates. After boot the -firmware sets 'partition' property in /chosen/bootloader. - -Copy the /chosen/bootloader node to the device tree. - -Set the env variable boot_partition accordingly to allow boards to -create a bootcmd based on the boot partition. - -Reviewed-by: Matthias Brugger -Signed-off-by: Gregor Herburger ---- -Changes in v3: -- Copy the complete '/chosen/bootloader' node instead of only the - partition property -- Link to v2: https://patch.msgid.link/20260803-tryboot2-v2-1-30c071f2ee15@linutronix.de - -Changes in v2: -- update Reviewed-by tag ---- - board/raspberrypi/rpi/rpi.c | 51 +++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 51 insertions(+) - - ---- -base-commit: baa64b2f892890f00a377eac4a3e685472bb56b5 -change-id: 20260803-tryboot2-8c5221376e5a - -Best regards, --- -Gregor Herburger - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index 1da5df92351c..ba8a2c1ba4cf 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -480,6 +480,20 @@ static void set_serial_number(void) - env_set("serial#", serial_string); - } - -+static void set_boot_partition_fdt(void) -+{ -+ void *fdtp = (void *)gd->fdt_blob; -+ u32 partition; -+ -+ partition = fdt_getprop_u32_default(fdtp, "/chosen/bootloader", "partition", 1); -+ if (!partition) { -+ printf("Failed to the get partition property.\n"); -+ return; -+ } -+ -+ env_set_ulong("boot_partition", partition); -+} -+ - int misc_init_r(void) - { - set_fdt_addr(); -@@ -489,6 +503,7 @@ int misc_init_r(void) - set_board_info(); - #endif - set_serial_number(); -+ set_boot_partition_fdt(); - - return 0; - } -@@ -579,6 +594,39 @@ int board_fdt_blob_setup(void **fdtp) - return 0; - } - -+int copy_node_all_properties(void *dst, void *src, const char *path, const char *node) -+{ -+ int src_parent, dst_parent; -+ int src_node, dst_node; -+ int prop; -+ int len; -+ -+ src_parent = fdt_path_offset(src, path); -+ dst_parent = fdt_path_offset(dst, path); -+ if (src_parent < 0 || dst_parent < 0) -+ return -1; -+ -+ src_node = fdt_subnode_offset(src, src_parent, node); -+ if (src_node < 0) -+ return -1; -+ -+ dst_node = fdt_find_or_add_subnode(dst, dst_parent, node); -+ if (dst_node < 0) -+ return -1; -+ -+ fdt_for_each_property_offset(prop, src, src_node) { -+ const char *name; -+ const void *value = fdt_getprop_by_offset(src, prop, &name, &len); -+ -+ if (!value || !name) -+ continue; -+ -+ fdt_setprop(dst, dst_node, name, value, len); -+ } -+ -+ return 0; -+} -+ - int copy_property(void *dst, void *src, char *path, char *property) - { - int dst_offset, src_offset; -@@ -641,6 +689,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) - - /* copy uart clk as provided by the firmware */ - copy_property(fdt, fw_fdt, "/clocks/clk-uart", "clock-frequency"); -+ -+ /* Copy the bootloader node */ -+ copy_node_all_properties(fdt, fw_fdt, "/chosen", "bootloader"); - } - - int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/sources b/sources index 282d22a..d751131 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-v2026.10-rc4.tar.bz2) = c454eb3ad16e3f5b3ee857171e4615dfa7ae413439a5ed77d145b63336de175f18e0557f93012ce067934816ba5d43daa0962e599cc9da6f94ccc659bd088768 +SHA512 (u-boot-2026.04.tar.bz2) = c5fca2abc533759985dfcc6d071d154007535787b0bbd569b61bda1fe2f3a31fba08481c8caf18cf5f2bc79609f50dee504977a8b65e8c4cc21f277268232e03 diff --git a/uboot-tools.spec b/uboot-tools.spec index 4578062..f39ee82 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc4 +#global candidate rc0 %if 0%{?rhel} %bcond_with toolsonly %else @@ -9,15 +9,15 @@ %global opensbi opensbi Name: uboot-tools -Version: 2026.10 -Release: 0.4%{?candidate:.%{candidate}}%{?dist} +Version: 2026.04 +Release: 2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. License: GPL-2.0-or-later AND LicenseRef-Callaway-BSD AND LGPL-2.1-or-later AND LGPL-2.0-or-later -URL: https://u-boot-project.org/ +URL: http://www.denx.de/wiki/U-Boot ExcludeArch: s390x -Source0: https://git.u-boot-project.org/u-boot/u-boot/-/archive/v%{version}%{?candidate:-%{candidate}}/u-boot-v%{version}%{?candidate:-%{candidate}}.tar.bz2 +Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: aarch64-boards Source2: riscv64-boards Source3: x86_64-boards @@ -29,18 +29,22 @@ Patch2: enable-bootmenu-by-default.patch Patch3: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch # Identify VFAT partitions as ESP, allows EFI setvar on our images Patch4: uefi-Add-all-options-for-EFI-System-Partitions.patch +# Upstream revert for rpi boot fix +Patch5: 0001-Revert-efi_loader-install-device-tree-on-configurati.patch # New function to find fdt for loading from disk -Patch5: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch +Patch6: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch # Enable UEFI SetVariable for devices without backed storage -Patch6: uefi-enable-SetVariableRT-with-volotile-storage.patch +Patch7: uefi-enable-SetVariableRT-with-volotile-storage.patch # Enable UEFI HTTPS boot for all Fedora firmware -Patch7: uefi-enable-https-boot-by-default.patch +Patch8: uefi-enable-https-boot-by-default.patch +Patch9: efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch # Device improvments # USB-PD improvements Patch10: USB-PD-TCPM-improvements.patch # Rockchips improvements Patch11: rockchip-Enable-preboot-start-for-pci-usb.patch +Patch12: rockchip-rk3568-nanopi-r5-Drop-duplicated-extra-sdhc.patch Patch13: rockchip-rk356x-Stop-overriding-sdhci-mmc-aliases.patch # Jetson fixes Patch14: p3450-fix-board.patch @@ -48,9 +52,10 @@ Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch # Fix AllWinner Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi -Patch20: Fix-NVMe-not-only-on-Raspberry-Pi-5.patch -Patch21: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch -Patch22: rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch +Patch20: ARM-RPi5-Enable-PCIe.patch +Patch21: 0001-Add-bcm2712-compat.patch +Patch22: ARM-RPi-PCIe-fixes.patch +Patch23: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch BuildRequires: bc BuildRequires: bison @@ -61,13 +66,8 @@ BuildRequires: gnutls-devel BuildRequires: libuuid-devel BuildRequires: make BuildRequires: ncurses-devel -%if 0%{?fedora} > 44 -BuildRequires: openssl3-devel -BuildRequires: openssl3-devel-engine -%else BuildRequires: openssl-devel BuildRequires: openssl-devel-engine -%endif BuildRequires: perl-interpreter BuildRequires: python3-devel BuildRequires: python3-setuptools @@ -122,7 +122,7 @@ U-Boot firmware binaries for x86_64 boards %endif %prep -%autosetup -p1 -n u-boot-v%{version}%{?candidate:-%{candidate}} +%autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} cp %SOURCE1 %SOURCE2 %SOURCE3 . @@ -314,40 +314,6 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog -* Tue Sep 08 2026 Peter Robinson - 1:2026.10-0.4.rc4 -- Update to 2026.10 RC4 - -* Thu Aug 27 2026 Peter Robinson - 1:2026.10-0.3.rc3 -- Update to 2026.10 RC3 - -* Wed Aug 12 2026 Peter Robinson - 1:2026.10-0.2.rc2 -- Update to 2026.10 RC2 - -* Thu Jul 30 2026 Peter Robinson - 1:2026.10-0.1.rc1 -- Update to 2026.10 RC1 -- Update source URL - -* Fri Jul 17 2026 Fedora Release Engineering - 1:2026.07-2 -- Rebuilt for https://fedoraproject.org/wiki/Fedora_45_Mass_Rebuild - -* Tue Jul 07 2026 Peter Robinson - 1:2026.07-1 -- Update to 2026.07 GA - -* Tue Jun 23 2026 Peter Robinson - 1:2026.07-0.4.rc5 -- Update to 2026.07 RC5 - -* Mon Jun 08 2026 Peter Robinson - 1:2026.07-0.3.rc4 -- Update to 2026.07 RC4 - -* Fri May 29 2026 Peter Robinson - 1:2026.07-0.2.rc3 -- Update to 2026.07 RC3 -- Update U-Boot Project URL -- Update RPi PCIe patches -- Various RPi fixes - -* Fri May 01 2026 Peter Robinson - 1:2026.07-0.1.rc1 -- Update to 2026.07 RC1 - * Sat Apr 11 2026 Peter Robinson - 1:2026.04-2 - Fix PCIe/USB on Raspberry Pi 4 (rhbz#2448365) - Fix detection of some revisions of RPi5 diff --git a/uefi-enable-https-boot-by-default.patch b/uefi-enable-https-boot-by-default.patch index dc0a683..a30879b 100644 --- a/uefi-enable-https-boot-by-default.patch +++ b/uefi-enable-https-boot-by-default.patch @@ -1,21 +1,41 @@ -From 7eabab2fda12b7a4417e5c7f29a507dfa9e7fffd Mon Sep 17 00:00:00 2001 +From 8253233373e608dd5b41544d63e0555f713fe876 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Sun, 3 May 2026 09:24:34 +0100 +Date: Wed, 10 Sep 2025 13:37:01 +0100 Subject: [PATCH] enable https boot by default -Signed-off-by: Peter Robinson --- + Kconfig | 3 ++- cmd/Kconfig | 1 + lib/efi_loader/Kconfig | 1 + lib/mbedtls/Kconfig | 3 ++- - net/Kconfig | 3 ++- 4 files changed, 6 insertions(+), 2 deletions(-) +diff --git a/Kconfig b/Kconfig +index 70125c4e5a6..89e82d7818f 100644 +--- a/Kconfig ++++ b/Kconfig +@@ -774,7 +774,7 @@ menu "Networking" + + choice + prompt "Networking stack" +- default NET ++ default NET_LWIP + + config NO_NET + bool "No networking support" +@@ -790,6 +790,7 @@ config NET + + config NET_LWIP + bool "Use lwIP for networking stack" ++ default y + imply NETDEVICES + help + Include networking support based on the lwIP (lightweight IP) diff --git a/cmd/Kconfig b/cmd/Kconfig -index c71c6824a19..8ff14adffe1 100644 +index 29de857ba7c..277b7be0b89 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -2289,6 +2289,7 @@ config CMD_WGET +@@ -2174,6 +2174,7 @@ config CMD_WGET config WGET_HTTPS bool "wget https" @@ -24,17 +44,17 @@ index c71c6824a19..8ff14adffe1 100644 depends on PROT_TCP_LWIP depends on MBEDTLS_LIB diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig -index 4cb13ae7c8a..20733429962 100644 +index 900113ca3e9..2188b4bd6e5 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig -@@ -609,6 +609,7 @@ config EFI_BOOTMGR +@@ -563,6 +563,7 @@ config EFI_BOOTMGR config EFI_HTTP_BOOT bool "EFI HTTP Boot support" + default y - depends on NET - depends on CMDLINE + depends on NET || NET_LWIP select CMD_NET + select CMD_DHCP diff --git a/lib/mbedtls/Kconfig b/lib/mbedtls/Kconfig index 789721ee6cd..7a241c2bc26 100644 --- a/lib/mbedtls/Kconfig @@ -56,27 +76,6 @@ index 789721ee6cd..7a241c2bc26 100644 select MBEDTLS_LIB_X509 endchoice -diff --git a/net/Kconfig b/net/Kconfig -index e712a0dd2ac..3158d37dff7 100644 ---- a/net/Kconfig -+++ b/net/Kconfig -@@ -16,7 +16,7 @@ if NET - - choice - prompt "Networking stack" -- default NET_LEGACY -+ default NET_LWIP - - config NET_LEGACY - bool "Legacy U-Boot networking stack" -@@ -27,6 +27,7 @@ config NET_LEGACY - - config NET_LWIP - bool "Use lwIP for networking stack" -+ default y - select NETDEVICES - help - Include networking support based on the lwIP (lightweight IP) -- -2.54.0 +2.51.0 diff --git a/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch index ac58bad..0a1727a 100644 --- a/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch +++ b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch @@ -1,6 +1,6 @@ -From 56a985cec8592a8de88e7f254df82f5d444a5ecc Mon Sep 17 00:00:00 2001 +From 121fd475757e183428ca78f43420c42b9973aa33 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Thu, 28 May 2026 22:08:07 +0100 +Date: Tue, 31 Dec 2024 14:11:12 +0000 Subject: [PATCH] initial find_fdt_location for finding the DT on disk The old distro boot looked for a DT on the first boot partition @@ -18,14 +18,14 @@ Signed-off-by: Peter Robinson --- cmd/bootmenu.c | 5 ++ include/efi_loader.h | 2 + - lib/efi_loader/efi_helper.c | 106 +++++++++++++++++++++++++++++++++++- - 3 files changed, 112 insertions(+), 1 deletion(-) + lib/efi_loader/efi_helper.c | 105 +++++++++++++++++++++++++++++++++++- + 4 files changed, 112 insertions(+), 1 deletion(-) diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c -index 528afd221d0..a10ea35a687 100644 +index b633aedf011..96a71a96820 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c -@@ -502,6 +502,11 @@ static void handle_uefi_bootnext(void) +@@ -461,6 +461,11 @@ static void handle_uefi_bootnext(void) u16 bootnext; efi_status_t ret; efi_uintn_t size; @@ -38,10 +38,10 @@ index 528afd221d0..a10ea35a687 100644 /* Initialize EFI drivers */ ret = efi_init_obj_list(); diff --git a/include/efi_loader.h b/include/efi_loader.h -index 3a4d502631c..b11f8a2cb42 100644 +index 39809eac1bc..511eba655e7 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h -@@ -574,6 +574,8 @@ struct efi_register_notify_event { +@@ -514,6 +514,8 @@ struct efi_register_notify_event { struct list_head handles; }; @@ -51,10 +51,10 @@ index 3a4d502631c..b11f8a2cb42 100644 int efi_init_early(void); /* Initialize efi execution environment */ diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c -index 44b806aadc4..61e982091b9 100644 +index bf96f61d3d0..3f496cc0dfb 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c -@@ -15,6 +15,7 @@ +@@ -12,6 +12,7 @@ #include #include #include @@ -62,7 +62,7 @@ index 44b806aadc4..61e982091b9 100644 #include #include #include -@@ -98,6 +99,99 @@ int efi_get_pxe_arch(void) +@@ -95,6 +96,99 @@ int efi_get_pxe_arch(void) return -EINVAL; } @@ -162,15 +162,14 @@ index 44b806aadc4..61e982091b9 100644 /** * efi_create_current_boot_var() - Return Boot#### name were #### is replaced by * the value of BootCurrent -@@ -558,11 +652,21 @@ efi_status_t efi_install_fdt(void *fdt) - const char *fdt_opt; - uintptr_t fdt_addr; - +@@ -548,11 +642,20 @@ efi_status_t efi_install_fdt(void *fdt) + /* Look for device tree that is already installed */ + if (efi_get_configuration_table(&efi_guid_fdt)) + return EFI_SUCCESS; + /* Check if there is device tree loaded from disk */ + fdt_opt = find_fdt_location(); + if (fdt_opt) -+ log_info("Found DTB on disk\n"); -+ ++ log_debug("Found DTB on disk\n"); /* Check if there is a hardware device tree */ - fdt_opt = env_get("fdt_addr"); + if (!fdt_opt) { @@ -181,10 +180,10 @@ index 44b806aadc4..61e982091b9 100644 /* Use our own device tree as fallback */ if (!fdt_opt) { fdt_opt = env_get("fdtcontroladdr"); -+ log_info("Using DT from U-Boot\n"); ++ log_debug("Using DT from U-Boot\n"); if (!fdt_opt) { log_err("need device tree\n"); return EFI_NOT_FOUND; -- -2.54.0 +2.47.1