From 197c94438094408cc7c4861bd83894448f1a7326 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 16 Oct 2025 23:13:21 +0100 Subject: [PATCH 01/38] Drop residual Rockchip firmware (saves ~150Mb) --- uboot-tools.spec | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 7f635e1..4aaac3a 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2025.10 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -234,6 +234,9 @@ do if [ -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot-sunxi-with-spl.bin ]; then rm -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot{,-dtb}.* fi + if [ -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot-rockchip.bin ]; then + rm -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot{,-dtb}.* + fi done %endif @@ -276,6 +279,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Thu Oct 16 2025 Peter Robinson - 1:2025.10-2 +- Drop residual Rockchip firmware (saves ~150Mb) + * Mon Oct 13 2025 Peter Robinson - 1:2025.10-1 - Update to 2025.10 GA (rhbz#2401964) - Fix booting when using FW device-tree (rhbz#2402498) From 797205ea12cdd8716166677512dbef9da6638338 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 24 Nov 2025 19:48:29 +0000 Subject: [PATCH 02/38] 2026.01 RC3 --- Initial-MNT-Reform2-support.patch | 155 ------------------------------ sources | 2 +- uboot-tools.spec | 10 +- 3 files changed, 7 insertions(+), 160 deletions(-) delete mode 100644 Initial-MNT-Reform2-support.patch diff --git a/Initial-MNT-Reform2-support.patch b/Initial-MNT-Reform2-support.patch deleted file mode 100644 index b8888da..0000000 --- a/Initial-MNT-Reform2-support.patch +++ /dev/null @@ -1,155 +0,0 @@ -From bcce96109c2fc3e8ed9e2ba12f1cbff43c0bd3c5 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Fri, 20 Jun 2025 17:45:02 +0100 -Subject: [PATCH 1/2] Initial MNT Reform2 support - ---- - arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi | 20 + - board/rockchip/evb_rk3588/MAINTAINERS | 6 + - configs/mnt-reform2-rk3588_defconfig | 93 ++++ - 5 files changed, 898 insertions(+) - create mode 100644 arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi - create mode 100644 configs/mnt-reform2-rk3588_defconfig - -diff --git a/arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi b/arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi -new file mode 100644 -index 00000000000..afd33dd3248 ---- /dev/null -+++ b/arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi -@@ -0,0 +1,20 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3588-u-boot.dtsi" -+ -+&fspim2_pins { -+ bootph-pre-ram; -+ bootph-some-ram; -+}; -+ -+&sdhci { -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+}; -+ -+&sfc { -+ flash@0 { -+ bootph-pre-ram; -+ bootph-some-ram; -+ }; -+}; -diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS -index 1232f05a387..24cf13c3c48 100644 ---- a/board/rockchip/evb_rk3588/MAINTAINERS -+++ b/board/rockchip/evb_rk3588/MAINTAINERS -@@ -29,6 +29,12 @@ F: configs/generic-rk3588_defconfig - F: arch/arm/dts/rk3588-generic.dts - F: arch/arm/dts/rk3588-generic-u-boot.dtsi - -+MNT-REFORM2-RK3588 -+M: Peter Robinson -+S: Maintained -+F: configs/mnt-reform2-rk3588_defconfig -+F: arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi -+ - ORANGEPI-5-RK3588 - M: Jonas Karlman - S: Maintained -diff --git a/configs/mnt-reform2-rk3588_defconfig b/configs/mnt-reform2-rk3588_defconfig -new file mode 100644 -index 00000000000..e12c48af70a ---- /dev/null -+++ b/configs/mnt-reform2-rk3588_defconfig -@@ -0,0 +1,93 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=24000000 -+CONFIG_SF_DEFAULT_MODE=0x2000 -+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-mnt-reform2" -+CONFIG_ROCKCHIP_RK3588=y -+CONFIG_ROCKCHIP_SPI_IMAGE=y -+CONFIG_SPL_SERIAL=y -+CONFIG_TARGET_EVB_RK3588=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_SF_DEFAULT_BUS=5 -+CONFIG_DEBUG_UART_BASE=0xFEB50000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI=y -+CONFIG_PCI=y -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_FIT_SIGNATURE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-mnt-reform2" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_SPI_LOAD=y -+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_DM_SEQ_ALIAS=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_HS400_ES_SUPPORT=y -+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y -+CONFIG_MMC_HS400_SUPPORT=y -+CONFIG_SPL_MMC_HS400_SUPPORT=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_SPI_FLASH_SFDP_SUPPORT=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_PHYLIB=y -+CONFIG_RTL8169=y -+CONFIG_NVME_PCI=y -+CONFIG_PCIE_DW_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_PHY_ROCKCHIP_USBDP=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_ROCKCHIP_SFC=y -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ERRNO_STR=y diff --git a/sources b/sources index 876b47d..12960ba 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2025.10.tar.bz2) = 01ac8b2b36bd73b7accc22afd20cf45d08ff8ece6a3d1c426ec90936d1767245add92572cc162500b2160bbc0e2ceed3e111a2a0dd35f8f3a86edbd4fc78753c +SHA512 (u-boot-2026.01-rc3.tar.bz2) = fb0edb63fc64d40a1fdf55bd44cac03d3fe575ac4729c8912fb4fa795c3a61f3bbb8f56711dbf316ec90c13871708706a190abc55324f4f31132ab5031e99331 diff --git a/uboot-tools.spec b/uboot-tools.spec index 4aaac3a..23ca147 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -#global candidate rc0 +%global candidate rc3 %if 0%{?rhel} %bcond_with toolsonly %else @@ -9,8 +9,8 @@ %global opensbi opensbi Name: uboot-tools -Version: 2025.10 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Version: 2026.01 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -42,7 +42,6 @@ Patch8: uefi-enable-https-boot-by-default.patch Patch10: USB-PD-TCPM-improvements.patch # Rockchips improvements Patch11: rockchip-Enable-preboot-start-for-pci-usb.patch -Patch13: Initial-MNT-Reform2-support.patch # Jetson fixes Patch14: p3450-fix-board.patch Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch @@ -279,6 +278,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Mon Nov 24 2025 Peter Robinson - 1:2026.01-0.1.rc3 +- Update to 2026.01 RC3 + * Thu Oct 16 2025 Peter Robinson - 1:2025.10-2 - Drop residual Rockchip firmware (saves ~150Mb) From 02745278999ca34178d1ee979df47919ce54477c Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 28 Nov 2025 13:38:19 +0000 Subject: [PATCH 03/38] Updates for RPi --- ...e-RaspBerry-Pi-5-support-part1-Fixes.patch | 557 ------------------ RPi-fixes.patch | 375 ++++++++++++ ...when-loading-kernel-with-non-boot-DT.patch | 161 ----- uboot-tools.spec | 7 +- 4 files changed, 380 insertions(+), 720 deletions(-) delete mode 100644 Improve-RaspBerry-Pi-5-support-part1-Fixes.patch create mode 100644 RPi-fixes.patch delete mode 100644 rpi-uart-clock-when-loading-kernel-with-non-boot-DT.patch diff --git a/Improve-RaspBerry-Pi-5-support-part1-Fixes.patch b/Improve-RaspBerry-Pi-5-support-part1-Fixes.patch deleted file mode 100644 index 0de9d91..0000000 --- a/Improve-RaspBerry-Pi-5-support-part1-Fixes.patch +++ /dev/null @@ -1,557 +0,0 @@ -From patchwork Fri Oct 10 16:17:21 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2148352 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - 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-List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -macb.c includes asm/arch/clk.h solely to declare get_macb_pclk_rate(). -That function is platform specific and only required if CONFIG_CLK -is not set. In case the machine does not provide it, compilation fails -even when the MACB pclk is detected via the CLK framework. - -Signed-off-by: Oleksii Moisieiev -Reviewed-by: Volodymyr Babchuk -Signed-off-by: Torsten Duwe ---- - drivers/net/macb.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/net/macb.c b/drivers/net/macb.c -index cbf5f605518..a54a268036d 100644 ---- a/drivers/net/macb.c -+++ b/drivers/net/macb.c -@@ -38,7 +38,9 @@ - #include - #include - #include -+#ifndef CONFIG_CLK - #include -+#endif - #include - - #include "macb.h" - -From patchwork Fri Oct 10 16:17:25 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2148353 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1)) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4cjsN11kswz1y1V - for ; Sat, 11 Oct 2025 03:17:37 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 283AF84051; - Fri, 10 Oct 2025 18:17:31 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 7C7A8843F5; Fri, 10 Oct 2025 18:17:29 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, - RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham - autolearn_force=no version=3.4.2 -Received: from verein.lst.de (verein.lst.de [213.95.11.211]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id B9A1C83FF9 - for ; Fri, 10 Oct 2025 18:17:27 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id 658FA227AAE; Fri, 10 Oct 2025 18:17:25 +0200 (CEST) -From: Torsten Duwe -To: Matthias Brugger , Simon Glass -Cc: Volodymyr Babchuk , - Oleksii Moisieiev , - Quentin Schulz , u-boot@lists.denx.de -Subject: [PATCH 2/4] pci-uclass: respect ofnode_read_pci_vendev retval -In-Reply-To: <20251010161442.410C4227AAE@verein.lst.de> -References: <20251010161442.410C4227AAE@verein.lst.de> -Message-Id: <20251010161725.658FA227AAE@verein.lst.de> -Date: Fri, 10 Oct 2025 18:17:25 +0200 (CEST) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -The vendor:device read in pci_uclass_child_post_bind() might fail, -which is currently ignored. In that case e.g. the RP1 on the RasPi5 -is erroneously being treated as a host bridge. - -Mark the device's PCI info as invalid in case of failure. - -Signed-off-by: Volodymyr Babchuk -Reviewed-by: Volodymyr Babchuk -Signed-off-by: Oleksii Moisieiev -Signed-off-by: Torsten Duwe ---- - drivers/pci/pci-uclass.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c -index c370f8c6400..4092e8ff5a9 100644 ---- a/drivers/pci/pci-uclass.c -+++ b/drivers/pci/pci-uclass.c -@@ -1200,6 +1200,7 @@ static int pci_uclass_post_probe(struct udevice *bus) - static int pci_uclass_child_post_bind(struct udevice *dev) - { - struct pci_child_plat *pplat; -+ int err; - - if (!dev_has_ofnode(dev)) - return 0; -@@ -1207,7 +1208,13 @@ static int pci_uclass_child_post_bind(struct udevice *dev) - pplat = dev_get_parent_plat(dev); - - /* Extract vendor id and device id if available */ -- ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device); -+ err = ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, -+ &pplat->device); -+ if (err) { -+ /* Mark PCI device structure as invalid */ -+ pplat->devfn = -1; -+ return 0; -+ } - - /* Extract the devfn from fdt_pci_addr */ - pplat->devfn = pci_get_devfn(dev); - -From patchwork Fri Oct 10 16:17:29 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2148354 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1)) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4cjsNB0gW1z1y1V - for ; Sat, 11 Oct 2025 03:17:46 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 79F208444B; - Fri, 10 Oct 2025 18:17:36 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 96BF884401; Fri, 10 Oct 2025 18:17:34 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, - PP_MIME_FAKE_ASCII_TEXT,RCVD_IN_DNSWL_BLOCKED, - RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 -Received: from verein.lst.de (verein.lst.de [213.95.11.211]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 509D784401 - for ; Fri, 10 Oct 2025 18:17:32 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id EDBF8227AAE; Fri, 10 Oct 2025 18:17:29 +0200 (CEST) -From: Torsten Duwe -To: Matthias Brugger , Simon Glass -Cc: Volodymyr Babchuk , - Oleksii Moisieiev , - Quentin Schulz , u-boot@lists.denx.de -Subject: [PATCH 3/4] Fix #cells lookup in of_get_dma_range -In-Reply-To: <20251010161442.410C4227AAE@verein.lst.de> -References: <20251010161442.410C4227AAE@verein.lst.de> -Message-Id: <20251010161729.EDBF8227AAE@verein.lst.de> -Date: Fri, 10 Oct 2025 18:17:29 +0200 (CEST) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -of_get_dma_range uses (of_bus *)->count_cells to look up the -#cells for addresses and sizes. It tries to do so for the current -device node and for the parent tree. count_cells defaults to -of_bus_default_count_cells, which _starts_ looking at the parent -node already, and then upwards. The correct way is to use -of_simple_*_cells for the current node, and count_cells(dev) for -the parent tree. - -Signed-off-by: Oleksii Moisieiev -Reviewed-by: Volodymyr Babchuk -Signed-off-by: Torsten Duwe ---- - -Here is the original, very detailed analysis and explanation -[edited] : - -According to the Section 2.3.9 of the Device Tree specification[0] -the format of the value of the dma-ranges property is an arbitrary -number of triplets of (child-bus-address, -parent-bus-address, length). -Where: -* The child-bus-address is a physical address within the child bus’ - address space. The number of cells to represent the address depends on - the bus and can be determined from the #address-cells of this node - (the node in which the dma-ranges property appears). -* The parent-bus-address is a physical address within the parent bus’ - address space. The number of cells to represent the parent address - is bus dependent and can be determined from the #address-cells - property of the node that defines the parent’s address space. -* The length specifies the size of the range in the child’s address - space. The number of cells to represent the size can be determined - from the #size-cells of this node (the node in which the dma-ranges - property appears) - -This description matches comments in the of_addr source code. But the -actual implementation does not match the specification. -'of_match_bus' returns address-cells and size-cells of the parent -device. That's why the following calls were used to receive addr_cells -and size_cells of the current device: -- of_simple_addr_cells -- of_simple_size_cells - -This fix was tested on RPI5 board with both device types: directly -connected (e.g Serial) and connected over PCIe (e.g ethernet). - -For example when dma_ranges are parsing the following device tree -structure: -/ { - pcie2: { - #address-cells = <3>; - #size-cells = <2>; - // 64GB system RAM space at PCIe 10_00000000 - dma-ranges = - <0x02000000 0x00 0x00000000 - 0x1f 0x00000000 - 0x00 0x00400000>, - <0x43000000 0x10 0x00000000 - 0x00 0x00000000 - 0x10 0x00000000>; - rp1: { - #address-cells = <2>; - #size-cells = <2>; - dma-ranges = - // inbound RP1 1x_xxxxxxxx -> PCIe 1x_xxxxxxxx - <0x10 0x00000000 - 0x43000000 0x10 0x00000000 - 0x10 0x00000000>, - - // inbound RP1 c0_40xxxxxx -> PCIe 00_00xxxxxx - <0xc0 0x40000000 - 0x02000000 0x0 0x00000000 - 0x0 0x00400000>, - - // inbound RP1 0x_xxxxxxxx -> PCIe 1x_xxxxxxxx - <0x00 0x00000000 - 0x02000000 0x10 0x00000000 - 0x10 0x00000000>; - }; - }; -}; - -So when we parse ranges on rp1, #address-cells of the rp1 node should -be taken into account. -In the provided example we have the following format: -pcie2: - #addres-cells = <0x3>; - #size-cells = <0x2>; - dma-ranges = < addr_hi addr_mid addr_lo - trans_addr_hi trans_addr_lo - size_hi size_lo>; - -rp1: - #addres-cells = <0x2>; - #size-cells = <0x2>; - dma-ranges = < addr_hi addr_lo - trans_addr_hi trans_addr_mid trans_addr_lo - size_hi size_lo>; - -of_get_dma_range searches for the first dev with dma_ranges -and then executes of_match_bus which follows by count_cells call -for both device and parent. - -count_cells returns #address-cells for the parent device to -the caller. -So in the provided example address cells should be 2 for rp1, -but we get 3 when using count_cells. -This breaks address translation and is fixed in the provided patch -by using the of_simple_addr_cells call, which will return correct -address-cells for the node. This matches the requirements of the -device-tree specification. - -[0] https://readthedocs.org/projects/devicetree-specification/downloads/pdf/latest/ - -Signed-off-by: Oleksii Moisieiev -Reviewed-by: Volodymyr Babchuk ---- - drivers/core/of_addr.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c -index 250dd175b55..823a4d70a6b 100644 ---- a/drivers/core/of_addr.c -+++ b/drivers/core/of_addr.c -@@ -374,16 +374,16 @@ int of_get_dma_range(const struct device_node *dev, phys_addr_t *cpu, - } - - /* Get the address sizes both for the bus and its parent */ -- bus_node = of_match_bus((struct device_node*)dev); -- bus_node->count_cells(dev, &na, &ns); -+ na = of_simple_addr_cells(dev); -+ ns = of_simple_size_cells(dev); - if (!OF_CHECK_COUNTS(na, ns)) { - printf("Bad cell count for %s\n", of_node_full_name(dev)); - ret = -EINVAL; - goto out_parent; - } - -- bus_node = of_match_bus(parent); -- bus_node->count_cells(parent, &pna, &pns); -+ bus_node = of_match_bus((struct device_node *)dev); -+ bus_node->count_cells(dev, &pna, &pns); - if (!OF_CHECK_COUNTS(pna, pns)) { - printf("Bad cell count for %s\n", of_node_full_name(parent)); - ret = -EINVAL; - -From patchwork Fri Oct 10 16:17:34 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2148355 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature ECDSA (secp384r1)) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4cjsNM6Lnmz1y1V - for ; Sat, 11 Oct 2025 03:17:55 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id BE4DF83966; - Fri, 10 Oct 2025 18:17:38 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 0E72584347; Fri, 10 Oct 2025 18:17:38 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, - RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham - autolearn_force=no version=3.4.2 -Received: from verein.lst.de (verein.lst.de [213.95.11.211]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 3E8BF836D2 - for ; Fri, 10 Oct 2025 18:17:36 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id 0A81B227AAF; Fri, 10 Oct 2025 18:17:34 +0200 (CEST) -From: Torsten Duwe -To: Matthias Brugger , Simon Glass -Cc: Volodymyr Babchuk , - Oleksii Moisieiev , - Quentin Schulz , u-boot@lists.denx.de -Subject: [PATCH 4/4] pcie_brcmstb: use bus_base for PCI config devices -In-Reply-To: <20251010161442.410C4227AAE@verein.lst.de> -References: <20251010161442.410C4227AAE@verein.lst.de> -Message-Id: <20251010161734.0A81B227AAF@verein.lst.de> -Date: Fri, 10 Oct 2025 18:17:34 +0200 (CEST) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -BRCM PCIe controller has different means of accessing to its own -config space and to device's config space. To support this quirk, -its driver uses simple heuristic: -when PCI subsystem probes Bus 0, the driver assumes -that the subsystem tries to accesses PCIe controller config space, -when PCI subsystem probes other busses, the driver uses mechanism -for device config space access. This heuristic works well when -there is only one PCIe controller in the system. -But U-Boot does not support concept of "PCI Segment", so when there -are more than one PCI controller: -- first one gets Bus address 0, -- second one - Bus address 2 and so on. -This breaks the brcm driver, because it tries to access second PCIe -controller config space as if it is device. To fix this, we introduce -additional property bus_base that holds a PCIe controller own Bus -address. -We use this property to calculate "real" Bus address for -underlying devices. -Please note that this fix may not support a case when we have -PCI-to-PCI bridges behind the second PCIe controller. - -Signed-off-by: Oleksii Moisieiev -Reviewed-by: Volodymyr Babchuk -Signed-off-by: Torsten Duwe ---- - drivers/pci/pcie_brcmstb.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index f089c48f028..ca5951974ce 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -61,6 +61,7 @@ struct brcm_pcie { - - int gen; - bool ssc; -+ uint16_t bus_base; - }; - - /** -@@ -134,6 +135,7 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, - * Busses 0 (host PCIe bridge) and 1 (its immediate child) - * are limited to a single device each - */ -+ pci_bus -= pcie->bus_base; - if (pci_bus < 2 && pci_dev > 0) - return -EINVAL; - -@@ -360,6 +362,8 @@ static int brcm_pcie_probe(struct udevice *dev) - u16 nlw, cls, lnksta; - u32 tmp; - -+ pcie->bus_base = hose->first_busno; -+ - /* - * Reset the bridge, assert the fundamental reset. Note for some SoCs, - * e.g. BCM7278, the fundamental reset should not be asserted here. diff --git a/RPi-fixes.patch b/RPi-fixes.patch new file mode 100644 index 0000000..b0d4367 --- /dev/null +++ b/RPi-fixes.patch @@ -0,0 +1,375 @@ +From 46e0ac55e56638d2543fc5a4c1ed28470095233e Mon Sep 17 00:00:00 2001 +From: Ilias Apalodimas +Date: Sat, 15 Nov 2025 09:33:29 +0200 +Subject: [PATCH 1/4] rpi: Fix compilation with larger configs + +Tom reports that adding more Kconfig options fails with +board/raspberrypi/rpi/lowlevel_init.o: in function `save_boot_params': +board/raspberrypi/rpi/lowlevel_init.S:20:(.text+0x0): +relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 +against symbol `fw_dtb_pointer' defined in .data section +in board/raspberrypi/rpi/rpi.o +make: *** [Makefile:2029: u-boot] Error 1 + +Since fw_dtb_pointer lives in .data it might end up above the ++-1MB that adr can reach. +So switch over to adrp+add which has a +-4gb reach. + +Reported-by: Tom Rini +Closes: https://source.denx.de/u-boot/custodians/u-boot-raspberrypi/-/issues/2 +Signed-off-by: Ilias Apalodimas +Reviewed-by: Peter Robinson +--- + board/raspberrypi/rpi/lowlevel_init.S | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/board/raspberrypi/rpi/lowlevel_init.S b/board/raspberrypi/rpi/lowlevel_init.S +index 8c39b3e12e8..30c0b0c27a8 100644 +--- a/board/raspberrypi/rpi/lowlevel_init.S ++++ b/board/raspberrypi/rpi/lowlevel_init.S +@@ -16,7 +16,8 @@ save_boot_params: + + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + #ifdef CONFIG_ARM64 +- adr x8, fw_dtb_pointer ++ adrp x8, fw_dtb_pointer ++ add x8, x8, #:lo12:fw_dtb_pointer + str x0, [x8] + #else + ldr r8, =fw_dtb_pointer +-- +2.52.0 + +From 2c39d975f87cfcce3805bff34918708bf7491b25 Mon Sep 17 00:00:00 2001 +From: Cibil Pankiras +Date: Fri, 14 Nov 2025 00:45:32 +0100 +Subject: [PATCH 2/4] pinctrl: bcm283x: Add GPIO pull-up/down control for + BCM2835 and BCM2711 + +This patch adds support for configuring GPIO pull-up and pull-down +resistors in the BCM283x pinctrl driver. It implements the brcm,pull +device tree property to control pin bias settings. + +The implementation follows the hardware-specific pull control +mechanisms: +- BCM2835: two-step GPPUD register sequence +- BCM2711: direct per-pin control registers + +This enables device tree configurations to specify pull-up, pull-down, +or no bias for individual GPIO pins. + +Tested on Raspberry Pi boards with both BCM2835 and BCM2711 SoCs. + +Signed-off-by: Cibil Pankiras +Reviewed-by: Matthias Brugger +--- + arch/arm/mach-bcm283x/include/mach/gpio.h | 10 ++ + drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 105 ++++++++++++++++++++- + 2 files changed, 112 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-bcm283x/include/mach/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h +index 4aeb48eeb20..c54414a012c 100644 +--- a/arch/arm/mach-bcm283x/include/mach/gpio.h ++++ b/arch/arm/mach-bcm283x/include/mach/gpio.h +@@ -26,6 +26,16 @@ + #define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10) + #define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3) + ++/* BCM2835 GPIO Pull-up/down register offsets */ ++#define BCM2835_GPPUD 37 ++#define BCM2835_GPPUDCLK0 38 ++ ++/* BCM2711 GPIO Pull-up/down control */ ++#define BCM2711_GPPUD_CNTRL_REG0 57 ++#define BCM2711_PUD_REG_OFFSET(gpio) ((gpio) / 16) ++#define BCM2711_PUD_REG_SHIFT(gpio) (((gpio) % 16) * 2) ++#define BCM2711_PUD_2711_MASK 0x3 ++ + struct bcm2835_gpio_regs { + u32 gpfsel[6]; + u32 reserved1; +diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +index cf9350c151e..4ecc8bac645 100644 +--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c ++++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +@@ -21,6 +21,8 @@ + #include + #include + #include ++#include ++#include + + struct bcm283x_pinctrl_priv { + u32 *base_reg; +@@ -54,7 +56,66 @@ static int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned int gpio) + } + + /* +- * bcm283x_pinctrl_set_state: configure pin functions. ++ * bcm2835_gpio_set_pull: Set GPIO pull-up/down resistor for BCM2835 ++ * @dev: the pinctrl device ++ * @gpio: the GPIO pin number ++ * @pull: pull setting (BCM2835_PUD_OFF, BCM2835_PUD_DOWN, BCM2835_PUD_UP) ++ */ ++static void bcm2835_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) ++{ ++ struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); ++ u32 bank = BCM2835_GPPUDCLK0 + BCM2835_GPIO_COMMON_BANK(gpio); ++ u32 bit = BCM2835_GPIO_COMMON_SHIFT(gpio); ++ ++ /* Set required control signal */ ++ writel(pull & 0x3, &priv->base_reg[BCM2835_GPPUD]); ++ udelay(1); ++ ++ /* Clock the control signal into the GPIO pads */ ++ writel(1 << bit, &priv->base_reg[bank]); ++ udelay(1); ++ ++ /* Remove the control signal and clock */ ++ writel(0, &priv->base_reg[BCM2835_GPPUD]); ++ writel(0, &priv->base_reg[bank]); ++} ++ ++/* ++ * bcm2711_gpio_set_pull: Set GPIO pull-up/down resistor for BCM2711 ++ * @dev: the pinctrl device ++ * @gpio: the GPIO pin number ++ * @pull: pull setting (BCM2835_PUD_OFF, BCM2835_PUD_DOWN, BCM2835_PUD_UP) ++ */ ++static void bcm2711_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) ++{ ++ struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); ++ u32 reg_offset; ++ u32 bit_shift; ++ u32 pull_bits; ++ ++ /* Findout which GPIO_PUP_PDN_CNTRL register to use */ ++ reg_offset = BCM2711_GPPUD_CNTRL_REG0 + BCM2711_PUD_REG_OFFSET(gpio); ++ ++ /* Findout the bit position */ ++ bit_shift = BCM2711_PUD_REG_SHIFT(gpio); ++ ++ /* Update the 2-bit field for this GPIO */ ++ pull_bits = pull & BCM2711_PUD_2711_MASK; ++ clrsetbits_le32(&priv->base_reg[reg_offset], ++ BCM2711_PUD_2711_MASK << bit_shift, ++ pull_bits << bit_shift); ++} ++ ++static void bcm283x_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) ++{ ++ if (device_is_compatible(dev, "brcm,bcm2835-gpio")) ++ bcm2835_gpio_set_pull(dev, gpio, pull); ++ else ++ bcm2711_gpio_set_pull(dev, gpio, pull); ++} ++ ++/* ++ * bcm283x_pinctrl_set_state: configure pin functions and pull states. + * @dev: the pinctrl device to be configured. + * @config: the state to be configured. + * @return: 0 in success +@@ -62,8 +123,10 @@ static int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned int gpio) + int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config) + { + u32 pin_arr[MAX_PINS_PER_BANK]; ++ u32 pull_arr[MAX_PINS_PER_BANK]; + int function; +- int i, len, pin_count = 0; ++ int i, len, pin_count = 0, pull_len = 0, pull_count = 0; ++ int pull_value; + + if (!dev_read_prop(config, "brcm,pins", &len) || !len || + len & 0x3 || dev_read_u32_array(config, "brcm,pins", pin_arr, +@@ -82,8 +145,44 @@ int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config) + return -EINVAL; + } + +- for (i = 0; i < pin_count; i++) ++ /* Check if brcm,pull property exists */ ++ if (dev_read_prop(config, "brcm,pull", &pull_len) && pull_len > 0) { ++ if (pull_len & 0x3) { ++ debug("Invalid pull array length for pinconfig %s (%d)\n", ++ config->name, pull_len); ++ return -EINVAL; ++ } ++ ++ pull_count = pull_len / sizeof(u32); ++ ++ if (pull_count != 1 && pull_count != pin_count) { ++ debug("Pull array count (%d) must be 1 or match pin count (%d) for pinconfig %s\n", ++ pull_count, pin_count, config->name); ++ return -EINVAL; ++ } ++ ++ if (dev_read_u32_array(config, "brcm,pull", pull_arr, pull_count)) { ++ debug("Failed reading pull array for pinconfig %s\n", config->name); ++ return -EINVAL; ++ } ++ ++ /* Validate pull values */ ++ for (i = 0; i < pull_count; i++) { ++ if (pull_arr[i] > 2) { ++ debug("Invalid pull value %d for pin %d in pinconfig %s\n", ++ pull_arr[i], pin_arr[i], config->name); ++ return -EINVAL; ++ } ++ } ++ } ++ ++ for (i = 0; i < pin_count; i++) { + bcm2835_gpio_set_func_id(dev, pin_arr[i], function); ++ if (pull_count > 0) { ++ pull_value = (pull_count == 1) ? pull_arr[0] : pull_arr[i]; ++ bcm283x_gpio_set_pull(dev, pin_arr[i], pull_value); ++ } ++ } + + return 0; + } +-- +2.52.0 + +From 15c719174cf30c4ef1c5a3638156db8c318fbd18 Mon Sep 17 00:00:00 2001 +From: Simon Glass +Date: Sat, 27 Sep 2025 05:30:15 -0600 +Subject: [PATCH 3/4] rpi: Use the U-Boot control FDT for fdt_addr + +The fdt_addr variable is used in extlinux as a fallback devicetree if +none is provided by the boot command. Otherwise the only use in U-Boot +seems to me efi_install_fdt() when the internal FDT is required. + +The existing mechanism uses the devicetree provided to U-Boot, but in +its original, unrelocated position. In my testing on an rpi_4, this ends +up at 2b35ef00 which is not a convenient place in memory, if the ramdisk +is large. + +U-Boot already deals with this sort of problem by relocating the FDT +to a safe address. + +So use the control-FDT address instead. + +Remove the existing comment, which is confusing, since the FDT is not +actually passed unmodified to the kernel: U-Boot adds various things +using its FDT-fixup mechanism. + +Note that board_get_usable_ram_top() reduces the RAM top for boards with +less RAM. This behaviour is left unchanged as there is no other +mechanism for U-Boot to handle this. + +Signed-off-by: Simon Glass +Reviewed-by: Christopher Obbard +Tested-by: Christopher Obbard # CM4 1G +--- + board/raspberrypi/rpi/rpi.c | 17 ++++++++++------- + 1 file changed, 10 insertions(+), 7 deletions(-) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index 1b0b664fa2b..6f96c1ebc96 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -3,6 +3,8 @@ + * (C) Copyright 2012-2016 Stephen Warren + */ + ++#define LOG_CATEGORY LOGC_BOARD ++ + #include + #include + #include +@@ -354,15 +356,13 @@ static void set_fdtfile(void) + } + + /* +- * If the firmware provided a valid FDT at boot time, let's expose it in +- * ${fdt_addr} so it may be passed unmodified to the kernel. ++ * Allow U-Boot to use its control FDT with extlinux if one is not provided. ++ * This will then go through the usual fixups that U-Boot does, before being ++ * handed off to Linux + */ + static void set_fdt_addr(void) + { +- if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) +- return; +- +- env_set_hex("fdt_addr", fw_dtb_pointer); ++ env_set_hex("fdt_addr", (ulong)gd->fdt_blob); + } + + /* +@@ -608,7 +608,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) + { + int node; + +- update_fdt_from_fw(blob, (void *)fw_dtb_pointer); ++ if (blob == gd->fdt_blob) ++ log_debug("Same FDT: nothing to do\n"); ++ else ++ update_fdt_from_fw(blob, (void *)gd->fdt_blob); + + if (CONFIG_IS_ENABLED(FDT_SIMPLEFB)) { + node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer"); +-- +2.52.0 + +From aa6ed1c970e3d6a7621d542e2c9317ab1ae865cc Mon Sep 17 00:00:00 2001 +From: Anders Roxell +Date: Tue, 25 Nov 2025 11:23:58 +0100 +Subject: [PATCH 4/4] rpi: Fix DRAM size reporting to show total RAM + +The VideoCore mailbox GET_ARM_MEMORY only reports the size of the +first accessible memory region (~947 MiB on RPi4 with 8GB), not the +total RAM. This causes U-Boot to display "DRAM: 947 MiB (total 7.9 GiB)" +instead of "DRAM: 7.9 GiB". + +On Raspberry Pi 4 with 8GB RAM, the memory is split across multiple +non-contiguous banks. The dram_init() function only sets gd->ram_size +to the first bank size reported by the VideoCore firmware, while +fdtdec_setup_memory_banksize() correctly populates all memory banks +from the device tree. + +Fix this by updating gd->ram_size after dram_init_banksize() has +populated all memory banks, so it reflects the actual total RAM +across all banks. + +Signed-off-by: Anders Roxell +--- + board/raspberrypi/rpi/rpi.c | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index 6f96c1ebc96..f9b643555dd 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -334,13 +334,27 @@ int dram_init(void) + #ifdef CONFIG_OF_BOARD + int dram_init_banksize(void) + { ++ phys_addr_t total_size = 0; ++ int i; + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + +- return fdtdec_setup_mem_size_base(); ++ ret = fdtdec_setup_mem_size_base(); ++ if (ret) ++ return ret; ++ ++ /* Update gd->ram_size to reflect total RAM across all banks */ ++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { ++ if (gd->bd->bi_dram[i].size == 0) ++ break; ++ total_size += gd->bd->bi_dram[i].size; ++ } ++ gd->ram_size = total_size; ++ ++ return 0; + } + #endif + +-- +2.52.0 + diff --git a/rpi-uart-clock-when-loading-kernel-with-non-boot-DT.patch b/rpi-uart-clock-when-loading-kernel-with-non-boot-DT.patch deleted file mode 100644 index ade9652..0000000 --- a/rpi-uart-clock-when-loading-kernel-with-non-boot-DT.patch +++ /dev/null @@ -1,161 +0,0 @@ -From patchwork Tue Apr 15 08:30:14 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Bruno Leite -X-Patchwork-Id: 2072903 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - dkim=pass (2048-bit key; - unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 - header.s=20230601 header.b=NLOXFHyi; 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- Tue, 15 Apr 2025 01:30:25 -0700 (PDT) -Received: from brule-Precision-3590.prevas.se ([81.216.59.226]) - by smtp.gmail.com with ESMTPSA id - 38308e7fff4ca-30f464cc0a2sm19679971fa.31.2025.04.15.01.30.23 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Tue, 15 Apr 2025 01:30:24 -0700 (PDT) -From: Bruno Leite -To: u-boot@lists.denx.de -Cc: pbrobinson@gmail.com, Matthias Brugger , - clast@prevas.dk, ravi@prevas.dk, Bruno Leite , - Fiona Klute , Francois Berder , - Ilias Apalodimas , - Martin Stolpe , - Patrice Chotard , - Rasmus Villemoes , - Simon Glass , Tom Rini -Subject: [PATCH 1/1] rpi: copy over uart clock-frequency in DT -Date: Tue, 15 Apr 2025 10:30:14 +0200 -Message-ID: <20250415083017.3523317-2-brunosampaioleite@gmail.com> -X-Mailer: git-send-email 2.45.2 -In-Reply-To: <20250415083017.3523317-1-brunosampaioleite@gmail.com> -References: <20250415083017.3523317-1-brunosampaioleite@gmail.com> -MIME-Version: 1.0 -X-Mailman-Approved-At: Tue, 15 Apr 2025 14:50:26 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Bruno Leite - -rpi5 firmware sets uart_clk clock-frequency in -the firmware and patches it to the DT, copy it -over when loading a new DT. - -Signed-off-by: Bruno Leite -Reviewed-by: Peter Robinson -Tested-by: Peter Robinson ---- - - board/raspberrypi/rpi/rpi.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index 70d3c35499b..5c84c324c71 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -602,6 +602,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) - - /* Bluetooth device address as provided by the firmware */ - copy_property(fdt, fw_fdt, "/soc/serial@7e201000/bluetooth", "local-bd-address"); -+ -+ /* copy uart clk as provided by the firmware */ -+ copy_property(fdt, fw_fdt, "/clocks/clk-uart", "clock-frequency"); - } - - int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/uboot-tools.spec b/uboot-tools.spec index 23ca147..181ab0b 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.01 -Release: 0.1%{?candidate:.%{candidate}}%{?dist} +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -48,7 +48,7 @@ Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch # Fix AllWinner Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi -Patch17: Improve-RaspBerry-Pi-5-support-part1-Fixes.patch +Patch17: RPi-fixes.patch BuildRequires: bc BuildRequires: bison @@ -278,6 +278,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Fri Nov 28 2025 Peter Robinson - 1:2026.01-0.2.rc3 +- Updates for RPi + * Mon Nov 24 2025 Peter Robinson - 1:2026.01-0.1.rc3 - Update to 2026.01 RC3 From 39834a463965473db4fb710749982d459b2f665d Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 8 Dec 2025 22:08:45 +0000 Subject: [PATCH 04/38] 2026.01 RC4 --- RPi-fixes.patch | 375 ----------------------------------------------- uboot-tools.spec | 9 +- 2 files changed, 5 insertions(+), 379 deletions(-) delete mode 100644 RPi-fixes.patch diff --git a/RPi-fixes.patch b/RPi-fixes.patch deleted file mode 100644 index b0d4367..0000000 --- a/RPi-fixes.patch +++ /dev/null @@ -1,375 +0,0 @@ -From 46e0ac55e56638d2543fc5a4c1ed28470095233e Mon Sep 17 00:00:00 2001 -From: Ilias Apalodimas -Date: Sat, 15 Nov 2025 09:33:29 +0200 -Subject: [PATCH 1/4] rpi: Fix compilation with larger configs - -Tom reports that adding more Kconfig options fails with -board/raspberrypi/rpi/lowlevel_init.o: in function `save_boot_params': -board/raspberrypi/rpi/lowlevel_init.S:20:(.text+0x0): -relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 -against symbol `fw_dtb_pointer' defined in .data section -in board/raspberrypi/rpi/rpi.o -make: *** [Makefile:2029: u-boot] Error 1 - -Since fw_dtb_pointer lives in .data it might end up above the -+-1MB that adr can reach. -So switch over to adrp+add which has a +-4gb reach. - -Reported-by: Tom Rini -Closes: https://source.denx.de/u-boot/custodians/u-boot-raspberrypi/-/issues/2 -Signed-off-by: Ilias Apalodimas -Reviewed-by: Peter Robinson ---- - board/raspberrypi/rpi/lowlevel_init.S | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/board/raspberrypi/rpi/lowlevel_init.S b/board/raspberrypi/rpi/lowlevel_init.S -index 8c39b3e12e8..30c0b0c27a8 100644 ---- a/board/raspberrypi/rpi/lowlevel_init.S -+++ b/board/raspberrypi/rpi/lowlevel_init.S -@@ -16,7 +16,8 @@ save_boot_params: - - /* The firmware provided ATAG/FDT address can be found in r2/x0 */ - #ifdef CONFIG_ARM64 -- adr x8, fw_dtb_pointer -+ adrp x8, fw_dtb_pointer -+ add x8, x8, #:lo12:fw_dtb_pointer - str x0, [x8] - #else - ldr r8, =fw_dtb_pointer --- -2.52.0 - -From 2c39d975f87cfcce3805bff34918708bf7491b25 Mon Sep 17 00:00:00 2001 -From: Cibil Pankiras -Date: Fri, 14 Nov 2025 00:45:32 +0100 -Subject: [PATCH 2/4] pinctrl: bcm283x: Add GPIO pull-up/down control for - BCM2835 and BCM2711 - -This patch adds support for configuring GPIO pull-up and pull-down -resistors in the BCM283x pinctrl driver. It implements the brcm,pull -device tree property to control pin bias settings. - -The implementation follows the hardware-specific pull control -mechanisms: -- BCM2835: two-step GPPUD register sequence -- BCM2711: direct per-pin control registers - -This enables device tree configurations to specify pull-up, pull-down, -or no bias for individual GPIO pins. - -Tested on Raspberry Pi boards with both BCM2835 and BCM2711 SoCs. - -Signed-off-by: Cibil Pankiras -Reviewed-by: Matthias Brugger ---- - arch/arm/mach-bcm283x/include/mach/gpio.h | 10 ++ - drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 105 ++++++++++++++++++++- - 2 files changed, 112 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-bcm283x/include/mach/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h -index 4aeb48eeb20..c54414a012c 100644 ---- a/arch/arm/mach-bcm283x/include/mach/gpio.h -+++ b/arch/arm/mach-bcm283x/include/mach/gpio.h -@@ -26,6 +26,16 @@ - #define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10) - #define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3) - -+/* BCM2835 GPIO Pull-up/down register offsets */ -+#define BCM2835_GPPUD 37 -+#define BCM2835_GPPUDCLK0 38 -+ -+/* BCM2711 GPIO Pull-up/down control */ -+#define BCM2711_GPPUD_CNTRL_REG0 57 -+#define BCM2711_PUD_REG_OFFSET(gpio) ((gpio) / 16) -+#define BCM2711_PUD_REG_SHIFT(gpio) (((gpio) % 16) * 2) -+#define BCM2711_PUD_2711_MASK 0x3 -+ - struct bcm2835_gpio_regs { - u32 gpfsel[6]; - u32 reserved1; -diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c -index cf9350c151e..4ecc8bac645 100644 ---- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c -+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c -@@ -21,6 +21,8 @@ - #include - #include - #include -+#include -+#include - - struct bcm283x_pinctrl_priv { - u32 *base_reg; -@@ -54,7 +56,66 @@ static int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned int gpio) - } - - /* -- * bcm283x_pinctrl_set_state: configure pin functions. -+ * bcm2835_gpio_set_pull: Set GPIO pull-up/down resistor for BCM2835 -+ * @dev: the pinctrl device -+ * @gpio: the GPIO pin number -+ * @pull: pull setting (BCM2835_PUD_OFF, BCM2835_PUD_DOWN, BCM2835_PUD_UP) -+ */ -+static void bcm2835_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) -+{ -+ struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); -+ u32 bank = BCM2835_GPPUDCLK0 + BCM2835_GPIO_COMMON_BANK(gpio); -+ u32 bit = BCM2835_GPIO_COMMON_SHIFT(gpio); -+ -+ /* Set required control signal */ -+ writel(pull & 0x3, &priv->base_reg[BCM2835_GPPUD]); -+ udelay(1); -+ -+ /* Clock the control signal into the GPIO pads */ -+ writel(1 << bit, &priv->base_reg[bank]); -+ udelay(1); -+ -+ /* Remove the control signal and clock */ -+ writel(0, &priv->base_reg[BCM2835_GPPUD]); -+ writel(0, &priv->base_reg[bank]); -+} -+ -+/* -+ * bcm2711_gpio_set_pull: Set GPIO pull-up/down resistor for BCM2711 -+ * @dev: the pinctrl device -+ * @gpio: the GPIO pin number -+ * @pull: pull setting (BCM2835_PUD_OFF, BCM2835_PUD_DOWN, BCM2835_PUD_UP) -+ */ -+static void bcm2711_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) -+{ -+ struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); -+ u32 reg_offset; -+ u32 bit_shift; -+ u32 pull_bits; -+ -+ /* Findout which GPIO_PUP_PDN_CNTRL register to use */ -+ reg_offset = BCM2711_GPPUD_CNTRL_REG0 + BCM2711_PUD_REG_OFFSET(gpio); -+ -+ /* Findout the bit position */ -+ bit_shift = BCM2711_PUD_REG_SHIFT(gpio); -+ -+ /* Update the 2-bit field for this GPIO */ -+ pull_bits = pull & BCM2711_PUD_2711_MASK; -+ clrsetbits_le32(&priv->base_reg[reg_offset], -+ BCM2711_PUD_2711_MASK << bit_shift, -+ pull_bits << bit_shift); -+} -+ -+static void bcm283x_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) -+{ -+ if (device_is_compatible(dev, "brcm,bcm2835-gpio")) -+ bcm2835_gpio_set_pull(dev, gpio, pull); -+ else -+ bcm2711_gpio_set_pull(dev, gpio, pull); -+} -+ -+/* -+ * bcm283x_pinctrl_set_state: configure pin functions and pull states. - * @dev: the pinctrl device to be configured. - * @config: the state to be configured. - * @return: 0 in success -@@ -62,8 +123,10 @@ static int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned int gpio) - int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config) - { - u32 pin_arr[MAX_PINS_PER_BANK]; -+ u32 pull_arr[MAX_PINS_PER_BANK]; - int function; -- int i, len, pin_count = 0; -+ int i, len, pin_count = 0, pull_len = 0, pull_count = 0; -+ int pull_value; - - if (!dev_read_prop(config, "brcm,pins", &len) || !len || - len & 0x3 || dev_read_u32_array(config, "brcm,pins", pin_arr, -@@ -82,8 +145,44 @@ int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config) - return -EINVAL; - } - -- for (i = 0; i < pin_count; i++) -+ /* Check if brcm,pull property exists */ -+ if (dev_read_prop(config, "brcm,pull", &pull_len) && pull_len > 0) { -+ if (pull_len & 0x3) { -+ debug("Invalid pull array length for pinconfig %s (%d)\n", -+ config->name, pull_len); -+ return -EINVAL; -+ } -+ -+ pull_count = pull_len / sizeof(u32); -+ -+ if (pull_count != 1 && pull_count != pin_count) { -+ debug("Pull array count (%d) must be 1 or match pin count (%d) for pinconfig %s\n", -+ pull_count, pin_count, config->name); -+ return -EINVAL; -+ } -+ -+ if (dev_read_u32_array(config, "brcm,pull", pull_arr, pull_count)) { -+ debug("Failed reading pull array for pinconfig %s\n", config->name); -+ return -EINVAL; -+ } -+ -+ /* Validate pull values */ -+ for (i = 0; i < pull_count; i++) { -+ if (pull_arr[i] > 2) { -+ debug("Invalid pull value %d for pin %d in pinconfig %s\n", -+ pull_arr[i], pin_arr[i], config->name); -+ return -EINVAL; -+ } -+ } -+ } -+ -+ for (i = 0; i < pin_count; i++) { - bcm2835_gpio_set_func_id(dev, pin_arr[i], function); -+ if (pull_count > 0) { -+ pull_value = (pull_count == 1) ? pull_arr[0] : pull_arr[i]; -+ bcm283x_gpio_set_pull(dev, pin_arr[i], pull_value); -+ } -+ } - - return 0; - } --- -2.52.0 - -From 15c719174cf30c4ef1c5a3638156db8c318fbd18 Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Sat, 27 Sep 2025 05:30:15 -0600 -Subject: [PATCH 3/4] rpi: Use the U-Boot control FDT for fdt_addr - -The fdt_addr variable is used in extlinux as a fallback devicetree if -none is provided by the boot command. Otherwise the only use in U-Boot -seems to me efi_install_fdt() when the internal FDT is required. - -The existing mechanism uses the devicetree provided to U-Boot, but in -its original, unrelocated position. In my testing on an rpi_4, this ends -up at 2b35ef00 which is not a convenient place in memory, if the ramdisk -is large. - -U-Boot already deals with this sort of problem by relocating the FDT -to a safe address. - -So use the control-FDT address instead. - -Remove the existing comment, which is confusing, since the FDT is not -actually passed unmodified to the kernel: U-Boot adds various things -using its FDT-fixup mechanism. - -Note that board_get_usable_ram_top() reduces the RAM top for boards with -less RAM. This behaviour is left unchanged as there is no other -mechanism for U-Boot to handle this. - -Signed-off-by: Simon Glass -Reviewed-by: Christopher Obbard -Tested-by: Christopher Obbard # CM4 1G ---- - board/raspberrypi/rpi/rpi.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index 1b0b664fa2b..6f96c1ebc96 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -3,6 +3,8 @@ - * (C) Copyright 2012-2016 Stephen Warren - */ - -+#define LOG_CATEGORY LOGC_BOARD -+ - #include - #include - #include -@@ -354,15 +356,13 @@ static void set_fdtfile(void) - } - - /* -- * If the firmware provided a valid FDT at boot time, let's expose it in -- * ${fdt_addr} so it may be passed unmodified to the kernel. -+ * Allow U-Boot to use its control FDT with extlinux if one is not provided. -+ * This will then go through the usual fixups that U-Boot does, before being -+ * handed off to Linux - */ - static void set_fdt_addr(void) - { -- if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) -- return; -- -- env_set_hex("fdt_addr", fw_dtb_pointer); -+ env_set_hex("fdt_addr", (ulong)gd->fdt_blob); - } - - /* -@@ -608,7 +608,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) - { - int node; - -- update_fdt_from_fw(blob, (void *)fw_dtb_pointer); -+ if (blob == gd->fdt_blob) -+ log_debug("Same FDT: nothing to do\n"); -+ else -+ update_fdt_from_fw(blob, (void *)gd->fdt_blob); - - if (CONFIG_IS_ENABLED(FDT_SIMPLEFB)) { - node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer"); --- -2.52.0 - -From aa6ed1c970e3d6a7621d542e2c9317ab1ae865cc Mon Sep 17 00:00:00 2001 -From: Anders Roxell -Date: Tue, 25 Nov 2025 11:23:58 +0100 -Subject: [PATCH 4/4] rpi: Fix DRAM size reporting to show total RAM - -The VideoCore mailbox GET_ARM_MEMORY only reports the size of the -first accessible memory region (~947 MiB on RPi4 with 8GB), not the -total RAM. This causes U-Boot to display "DRAM: 947 MiB (total 7.9 GiB)" -instead of "DRAM: 7.9 GiB". - -On Raspberry Pi 4 with 8GB RAM, the memory is split across multiple -non-contiguous banks. The dram_init() function only sets gd->ram_size -to the first bank size reported by the VideoCore firmware, while -fdtdec_setup_memory_banksize() correctly populates all memory banks -from the device tree. - -Fix this by updating gd->ram_size after dram_init_banksize() has -populated all memory banks, so it reflects the actual total RAM -across all banks. - -Signed-off-by: Anders Roxell ---- - board/raspberrypi/rpi/rpi.c | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index 6f96c1ebc96..f9b643555dd 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -334,13 +334,27 @@ int dram_init(void) - #ifdef CONFIG_OF_BOARD - int dram_init_banksize(void) - { -+ phys_addr_t total_size = 0; -+ int i; - int ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - return ret; - -- return fdtdec_setup_mem_size_base(); -+ ret = fdtdec_setup_mem_size_base(); -+ if (ret) -+ return ret; -+ -+ /* Update gd->ram_size to reflect total RAM across all banks */ -+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { -+ if (gd->bd->bi_dram[i].size == 0) -+ break; -+ total_size += gd->bd->bi_dram[i].size; -+ } -+ gd->ram_size = total_size; -+ -+ return 0; - } - #endif - --- -2.52.0 - diff --git a/uboot-tools.spec b/uboot-tools.spec index 181ab0b..68c1959 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc3 +%global candidate rc4 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.01 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.3%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -47,8 +47,6 @@ Patch14: p3450-fix-board.patch Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch # Fix AllWinner Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch -# RPi -Patch17: RPi-fixes.patch BuildRequires: bc BuildRequires: bison @@ -278,6 +276,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Mon Dec 08 2025 Peter Robinson - 1:2026.01-0.3.rc4 +- Update to 2026.01 RC4 + * Fri Nov 28 2025 Peter Robinson - 1:2026.01-0.2.rc3 - Updates for RPi From ddba19de1422e7cfac4b6bbe144a6518a962b31c Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 8 Dec 2025 22:15:05 +0000 Subject: [PATCH 05/38] Upload rc4 source --- sources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sources b/sources index 12960ba..3a952f7 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.01-rc3.tar.bz2) = fb0edb63fc64d40a1fdf55bd44cac03d3fe575ac4729c8912fb4fa795c3a61f3bbb8f56711dbf316ec90c13871708706a190abc55324f4f31132ab5031e99331 +SHA512 (u-boot-2026.01-rc4.tar.bz2) = 8a00f172cac19d4a820898ed09edbf58b60fe500ad3178e11d9c47db6103961ea5c50184f0ee6af0bd82d7a0bd000a17ec7ef5170b073b0601689f3e857eeeba From 2424465fce73467f576fea0c97494c4792e15d8e Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 29 Dec 2025 03:52:29 +0000 Subject: [PATCH 06/38] 2026.01 RC5 --- sources | 2 +- uboot-tools.spec | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/sources b/sources index 3a952f7..2006c45 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.01-rc4.tar.bz2) = 8a00f172cac19d4a820898ed09edbf58b60fe500ad3178e11d9c47db6103961ea5c50184f0ee6af0bd82d7a0bd000a17ec7ef5170b073b0601689f3e857eeeba +SHA512 (u-boot-2026.01-rc5.tar.bz2) = eb5f9b08310b1da2dd90dfdef9342d6833b90874fa19f64246262d1f9edc1da56ee8020614ad05e462dddde5ab3926e8cd4cf1af39669425ad21e17e34e88369 diff --git a/uboot-tools.spec b/uboot-tools.spec index 68c1959..5d36947 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc4 +%global candidate rc5 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.01 -Release: 0.3%{?candidate:.%{candidate}}%{?dist} +Release: 0.4%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -276,6 +276,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Mon Dec 29 2025 Peter Robinson - 1:2026.01-0.4.rc5 +- Update to 2026.01 RC5 + * Mon Dec 08 2025 Peter Robinson - 1:2026.01-0.3.rc4 - Update to 2026.01 RC4 From b2a3bbf32c8b28d742de19699cbd8be460ad4b0f Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 7 Jan 2026 00:24:41 +0000 Subject: [PATCH 07/38] 2026.01 GA --- ...nanopi-r5-Drop-duplicated-extra-sdhc.patch | 39 +++++++++++++++++++ ...6x-Stop-overriding-sdhci-mmc-aliases.patch | 33 ++++++++++++++++ sources | 2 +- uboot-tools.spec | 9 ++++- 4 files changed, 80 insertions(+), 3 deletions(-) create mode 100644 rockchip-rk3568-nanopi-r5-Drop-duplicated-extra-sdhc.patch create mode 100644 rockchip-rk356x-Stop-overriding-sdhci-mmc-aliases.patch diff --git a/rockchip-rk3568-nanopi-r5-Drop-duplicated-extra-sdhc.patch b/rockchip-rk3568-nanopi-r5-Drop-duplicated-extra-sdhc.patch new file mode 100644 index 0000000..bef5a9e --- /dev/null +++ b/rockchip-rk3568-nanopi-r5-Drop-duplicated-extra-sdhc.patch @@ -0,0 +1,39 @@ +From aef38432fbc93621b434836b95b10c28aa880e84 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 9 Dec 2025 20:51:06 +0000 +Subject: [PATCH 1/2] rockchip: rk3568-nanopi-r5: Drop duplicated/extra sdhci + +The pinctrl settings are now upstream, with the upstream +voltage supplies, and the HS200 mode is confirmed to work +fine but the HS400 mode had reported issues so let's just +consume what the upstream DT has now as it's all known good. + +Reported-by: Dusty Mabe +Tested-by: Dusty Mabe +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +index 64c43374c04..7e24be1a5e7 100644 +--- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi ++++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +@@ -12,14 +12,6 @@ + /delete-property/ vpcie3v3-supply; + }; + +-&sdhci { +- cap-mmc-highspeed; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +-}; +- + &vcc5v0_usb_host { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; +-- +2.52.0 + diff --git a/rockchip-rk356x-Stop-overriding-sdhci-mmc-aliases.patch b/rockchip-rk356x-Stop-overriding-sdhci-mmc-aliases.patch new file mode 100644 index 0000000..c67e4af --- /dev/null +++ b/rockchip-rk356x-Stop-overriding-sdhci-mmc-aliases.patch @@ -0,0 +1,33 @@ +From 29efc0396809384cf37bfcfb01c62e63216fa998 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 9 Dec 2025 21:13:46 +0000 +Subject: [PATCH 2/2] rockchip: rk356x: Stop overriding sdhci/mmc aliases + +Upstream device tree has rules where the aliases are board +specific settings, no SoC settings. Looking at upstream +rk356x boards there's a lot of variation in the setting of +mmc0/mmc1 based on the device so we should not be overriding +this here and now we sync to upstream we should just consume +those settings, to do otherwise confuses users. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk356x-u-boot.dtsi | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi +index 738b9673d35..f25c7970208 100644 +--- a/arch/arm/dts/rk356x-u-boot.dtsi ++++ b/arch/arm/dts/rk356x-u-boot.dtsi +@@ -7,8 +7,6 @@ + + / { + aliases { +- mmc0 = &sdhci; +- mmc1 = &sdmmc0; + spi4 = &sfc; + }; + +-- +2.52.0 + diff --git a/sources b/sources index 2006c45..9356a13 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.01-rc5.tar.bz2) = eb5f9b08310b1da2dd90dfdef9342d6833b90874fa19f64246262d1f9edc1da56ee8020614ad05e462dddde5ab3926e8cd4cf1af39669425ad21e17e34e88369 +SHA512 (u-boot-2026.01.tar.bz2) = b1f988a497c77da60faf89ed33034e9ae58c4cd7f208e5ce451f1372e13540a66289bee4f08ca2f68f105d73f1ceae058b1f713db549edbcc885d9c66bdc4f8b diff --git a/uboot-tools.spec b/uboot-tools.spec index 5d36947..914f2ca 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc5 +#global candidate rc0 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.01 -Release: 0.4%{?candidate:.%{candidate}}%{?dist} +Release: 1%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -42,6 +42,8 @@ Patch8: uefi-enable-https-boot-by-default.patch Patch10: USB-PD-TCPM-improvements.patch # Rockchips improvements Patch11: rockchip-Enable-preboot-start-for-pci-usb.patch +Patch12: rockchip-rk3568-nanopi-r5-Drop-duplicated-extra-sdhc.patch +Patch13: rockchip-rk356x-Stop-overriding-sdhci-mmc-aliases.patch # Jetson fixes Patch14: p3450-fix-board.patch Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch @@ -276,6 +278,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Jan 06 2026 Peter Robinson - 1:2026.01-1 +- Update to 2026.01 GA + * Mon Dec 29 2025 Peter Robinson - 1:2026.01-0.4.rc5 - Update to 2026.01 RC5 From fff441a730b7521d1355af5d04d9dbdbd9532de0 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 7 Jan 2026 05:30:06 +0000 Subject: [PATCH 08/38] Drop Jetson Nano for the momment, size too big --- aarch64-boards | 1 - 1 file changed, 1 deletion(-) diff --git a/aarch64-boards b/aarch64-boards index cc2542d..42f30df 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -67,7 +67,6 @@ orangepi_zero_plus2 p212 p2371-2180 p2771-0000-500 -p3450-0000 pine64-lts pine64_plus pinebook From 3a3ec8a0bf20fb26f883a13470cd7a4953db6c3a Mon Sep 17 00:00:00 2001 From: Fedora Release Engineering Date: Sat, 17 Jan 2026 19:31:26 +0000 Subject: [PATCH 09/38] Rebuilt for https://fedoraproject.org/wiki/Fedora_44_Mass_Rebuild --- uboot-tools.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 914f2ca..b4c20fd 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.01 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -278,6 +278,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Sat Jan 17 2026 Fedora Release Engineering - 1:2026.01-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_44_Mass_Rebuild + * Tue Jan 06 2026 Peter Robinson - 1:2026.01-1 - Update to 2026.01 GA From d7f2a6c29a09be8d2cb95472731f306f5d031055 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 29 Sep 2025 10:56:52 +0200 Subject: [PATCH 10/38] Add a uboot-images-x86_64 sub-package U-Boot has QEMU configurations for different architectures, and existing uboot-images-{aarch,riscv}64 sub-packages already ship binaries for them. But there isn't one for x86_64, let's add a new uboot-images-x86_64 that contain an image that can be used to test U-Boot on this arch using QEMU. --- uboot-tools.spec | 36 ++++++++++++++++++++++++++++++++++-- x86_64-boards | 1 + 2 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 x86_64-boards diff --git a/uboot-tools.spec b/uboot-tools.spec index b4c20fd..45d276c 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -20,6 +20,7 @@ ExcludeArch: s390x Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: aarch64-boards Source2: riscv64-boards +Source3: x86_64-boards # Fedora patches to enable/disable features Patch1: disable-VBE-by-default.patch @@ -102,12 +103,21 @@ BuildArch: noarch %description -n uboot-images-riscv64 U-Boot firmware binaries for riscv64 boards %endif + +%ifarch x86_64 +%package -n uboot-images-x86_64 +Summary: U-Boot firmware images for x86_64 boards +BuildArch: noarch + +%description -n uboot-images-x86_64 +U-Boot firmware binaries for x86_64 boards +%endif %endif %prep %autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} -cp %SOURCE1 %SOURCE2 . +cp %SOURCE1 %SOURCE2 %SOURCE3 . %build mkdir builds @@ -121,7 +131,7 @@ mkdir builds export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin %endif -%ifarch aarch64 riscv64 +%ifarch aarch64 riscv64 x86_64 for board in $(cat %{_arch}-boards) do echo "Building board: $board" @@ -226,6 +236,18 @@ do done %endif +%ifarch x86_64 +for board in $(ls builds) +do + for file in u-boot.rom + do + if [ -f builds/$(echo $board)/$(echo $file) ]; then + install -pD -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/$(echo $file) + fi + done +done +%endif + # Bit of a hack to remove binaries we don't use as they're large for board in $(ls builds) do @@ -275,9 +297,19 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %dir %{_datadir}/uboot/ %{_datadir}/uboot/* %endif + +%ifarch x86_64 +%files -n uboot-images-x86_64 +%license Licenses/* +%dir %{_datadir}/uboot/ +%{_datadir}/uboot/* +%endif %endif %changelog +* Mon Jan 19 2026 Javier Martinez Canillas - 1:2026.01-3 +- Add a uboot-images-x86_64 subpackage + * Sat Jan 17 2026 Fedora Release Engineering - 1:2026.01-2 - Rebuilt for https://fedoraproject.org/wiki/Fedora_44_Mass_Rebuild diff --git a/x86_64-boards b/x86_64-boards new file mode 100644 index 0000000..dec8df3 --- /dev/null +++ b/x86_64-boards @@ -0,0 +1 @@ +qemu-x86_64 From 4238dd5a89785bd4518ff75b4f7daa9361878186 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 20 Jan 2026 06:27:30 +0000 Subject: [PATCH 11/38] Bump release --- uboot-tools.spec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 45d276c..4fff891 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.01 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Release: 3%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. From f12491dc88bfcc1641e53d1aeb3a456d91347f25 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 27 Jan 2026 16:21:03 +0000 Subject: [PATCH 12/38] 2026.04 RC1 --- aarch64-boards | 2 +- sources | 2 +- uboot-tools.spec | 9 ++++++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/aarch64-boards b/aarch64-boards index 42f30df..366d0c8 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -80,7 +80,7 @@ puma-rk3399 qcm6490 qcom qcom_qcs8300 -qcs9100 +qcom_qcs9100 qemu_arm64 qemu_arm64_lwip roc-cc-rk3328 diff --git a/sources b/sources index 9356a13..281f8ac 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.01.tar.bz2) = b1f988a497c77da60faf89ed33034e9ae58c4cd7f208e5ce451f1372e13540a66289bee4f08ca2f68f105d73f1ceae058b1f713db549edbcc885d9c66bdc4f8b +SHA512 (u-boot-2026.04-rc1.tar.bz2) = 4011cd8aecd91f981d26218f3d568f5d2b3f7d8c639a0fa61a56f5e40e21376bc73c8bfd5757a08150d58913f038bd36f9769726f8cfdd9490d280b56762eab5 diff --git a/uboot-tools.spec b/uboot-tools.spec index 4fff891..7d7a1bf 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -#global candidate rc0 +%global candidate rc1 %if 0%{?rhel} %bcond_with toolsonly %else @@ -9,8 +9,8 @@ %global opensbi opensbi Name: uboot-tools -Version: 2026.01 -Release: 3%{?candidate:.%{candidate}}%{?dist} +Version: 2026.04 +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -307,6 +307,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Jan 27 2026 Peter Robinson - 1:2026.04-0.2.rc1 +- Update to 2026.04 RC1 + * Mon Jan 19 2026 Javier Martinez Canillas - 1:2026.01-3 - Add a uboot-images-x86_64 subpackage From bb3fd2de74f44b635351b3d0cd291ee092a2257b Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 9 Feb 2026 17:38:30 +0000 Subject: [PATCH 13/38] Updates for Raspberry Pi --- ...Video-Core-logs-DT-parameter-through.patch | 31 ++++ ...ll-state-register-values-for-BCM2711.patch | 173 ++++++++++++++++++ uboot-tools.spec | 3 + 3 files changed, 207 insertions(+) create mode 100644 rpi-pass-the-Video-Core-logs-DT-parameter-through.patch create mode 100644 rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch diff --git a/rpi-pass-the-Video-Core-logs-DT-parameter-through.patch b/rpi-pass-the-Video-Core-logs-DT-parameter-through.patch new file mode 100644 index 0000000..a080d1b --- /dev/null +++ b/rpi-pass-the-Video-Core-logs-DT-parameter-through.patch @@ -0,0 +1,31 @@ +From 667e6169e50233060343d081942fc3025196a7dd Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Mon, 9 Feb 2026 11:01:17 +0000 +Subject: [PATCH] rpi: pass the Video Core logs DT parameter through + +Pass the VC logs DT parameter through to the kernel +device tree. This is used by the vclog tool and is +a useful debugging tool. + +Signed-off-by: Peter Robinson +--- + board/raspberrypi/rpi/rpi.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index f9b643555dd..7256d66a9a6 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -608,6 +608,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) + /* warnings from the firmware (if any) */ + copy_property(fdt, fw_fdt, "/chosen", "user-warnings"); + ++ /* firmware logs - used by the vclog utility */ ++ copy_property(fdt, fw_fdt, "/chosen", "log"); ++ + /* address of the PHY device as provided by the firmware */ + copy_property(fdt, fw_fdt, "ethernet0/mdio@e14/ethernet-phy@1", "reg"); + +-- +2.53.0 + diff --git a/rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch b/rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch new file mode 100644 index 0000000..a14462a --- /dev/null +++ b/rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch @@ -0,0 +1,173 @@ +From patchwork Fri Feb 6 10:47:00 2026 +Content-Type: text/plain; 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+ Fri, 06 Feb 2026 02:47:08 -0800 (PST) +Received: from cibil-Precision-5570.. + ([2a02:3033:280:4628:c815:77f9:1225:71ed]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48320728774sm40932795e9.14.2026.02.06.02.47.07 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Fri, 06 Feb 2026 02:47:08 -0800 (PST) +From: Cibil Pankiras +To: u-boot@lists.denx.de +Cc: Matthias Brugger , + Peter Robinson , Tom Rini +Subject: [PATCH v2] pinctrl: bcm283x: Fix GPIO pull state register values for + BCM2711 +Date: Fri, 6 Feb 2026 11:47:00 +0100 +Message-ID: <20260206104701.34358-1-cibil.pankiras@egym.com> +X-Mailer: git-send-email 2.43.0 +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +BCM2711 has different pull-up/down register values compared to BCM2835 + +- BCM2835: NONE=0, DOWN=1, UP=2 +- BCM2711: NONE=0, UP=1, DOWN=2 + +This patch fixes the pull state register values for BCM2711. + +Fixes: 2c39d975f87c ("pinctrl: bcm283x: Add GPIO pull-up/down control for BCM2835 and BCM2711") +Signed-off-by: Cibil Pankiras +--- +Changes in v2: +- Moved pull value swap logic to bcm2711_gpio_set_pull() +- Updated the function header comment for bcm2711_gpio_set_pull() +--- + drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +index 4ecc8bac645a..90eee88eb137 100644 +--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c ++++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +@@ -30,6 +30,11 @@ struct bcm283x_pinctrl_priv { + + #define MAX_PINS_PER_BANK 16 + ++/* pull states for BCM2711 */ ++#define BCM2711_PULL_NONE 0 ++#define BCM2711_PULL_UP 1 ++#define BCM2711_PULL_DOWN 2 ++ + static void bcm2835_gpio_set_func_id(struct udevice *dev, unsigned int gpio, + int func) + { +@@ -93,6 +98,17 @@ static void bcm2711_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pu + u32 bit_shift; + u32 pull_bits; + ++ if (!device_is_compatible(dev, "brcm,bcm2711-gpio")) ++ return; ++ ++ /* BCM2711's pull values differ from BCM2835 */ ++ if (pull == BCM2835_PUD_UP) ++ pull = BCM2711_PULL_UP; ++ else if (pull == BCM2835_PUD_DOWN) ++ pull = BCM2711_PULL_DOWN; ++ else ++ pull = BCM2711_PULL_NONE; ++ + /* Findout which GPIO_PUP_PDN_CNTRL register to use */ + reg_offset = BCM2711_GPPUD_CNTRL_REG0 + BCM2711_PUD_REG_OFFSET(gpio); + diff --git a/uboot-tools.spec b/uboot-tools.spec index 7d7a1bf..48c8cbf 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -50,6 +50,9 @@ Patch14: p3450-fix-board.patch Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch # Fix AllWinner Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch +# RPi +Patch17: rpi-pass-the-Video-Core-logs-DT-parameter-through.patch +Patch18: rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch BuildRequires: bc BuildRequires: bison From 4f7be5372722dcf37e860ceeddaed0c74d36c953 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 9 Feb 2026 23:02:50 +0000 Subject: [PATCH 14/38] Update to 2026.04 RC2 Signed-off-by: Peter Robinson --- sources | 2 +- uboot-tools.spec | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/sources b/sources index 281f8ac..ffd26be 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.04-rc1.tar.bz2) = 4011cd8aecd91f981d26218f3d568f5d2b3f7d8c639a0fa61a56f5e40e21376bc73c8bfd5757a08150d58913f038bd36f9769726f8cfdd9490d280b56762eab5 +SHA512 (u-boot-2026.04-rc2.tar.bz2) = 9e88a2bfabcb50b3d8a1c3edf30c087c5ce5853c49bf27b2c6b57ca11f89aa061ad2fa803d8a684a38fe761d7bba6aec23c44115553cb9ce234da4041a38fdcf diff --git a/uboot-tools.spec b/uboot-tools.spec index 48c8cbf..7fa8294 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc1 +%global candidate rc2 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.3%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -310,6 +310,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Mon Feb 09 2026 Peter Robinson - 1:2026.04-0.3.rc2 +- Update to 2026.04 RC2 + * Tue Jan 27 2026 Peter Robinson - 1:2026.04-0.2.rc1 - Update to 2026.04 RC1 From 28466513619100e212423c81790c79089d3986fa Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 17 Feb 2026 15:16:26 +0000 Subject: [PATCH 15/38] Add initial bcm2712d0 identification --- board-raspberry-add-FDT-for-bcm2712d0.patch | 574 ++++++++++++++++++++ uboot-tools.spec | 6 +- 2 files changed, 579 insertions(+), 1 deletion(-) create mode 100644 board-raspberry-add-FDT-for-bcm2712d0.patch diff --git a/board-raspberry-add-FDT-for-bcm2712d0.patch b/board-raspberry-add-FDT-for-bcm2712d0.patch new file mode 100644 index 0000000..884911e --- /dev/null +++ b/board-raspberry-add-FDT-for-bcm2712d0.patch @@ -0,0 +1,574 @@ +From patchwork Mon Feb 16 18:44:51 2026 +Content-Type: text/plain; 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+ Mon, 16 Feb 2026 10:45:14 -0800 (PST) +Received: from desktop.home (83.23.200.152.ipv4.supernova.orange.pl. + [83.23.200.152]) by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-4835dd0e327sm449404165e9.14.2026.02.16.10.45.13 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Mon, 16 Feb 2026 10:45:14 -0800 (PST) +From: =?utf-8?q?Filip_Kokosi=C5=84ski?= +To: u-boot@lists.denx.de +Cc: mbrugger@suse.com, pbrobinson@gmail.com, + =?utf-8?q?Filip_Kokosi=C5=84ski?= +Subject: [PATCH 1/2] board/raspberrypi: add multi-FDT support +Date: Mon, 16 Feb 2026 19:44:51 +0100 +Message-ID: <20260216184452.18732-2-filip.kokosinski@gmail.com> +X-Mailer: git-send-email 2.51.2 +In-Reply-To: <20260216184452.18732-1-filip.kokosinski@gmail.com> +References: <20260216184452.18732-1-filip.kokosinski@gmail.com> +MIME-Version: 1.0 +X-Mailman-Approved-At: Mon, 16 Feb 2026 20:51:34 +0100 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +This patch adds support for multiple FDT files per board model. This is +done by adding the FDTFILES macro, which initializes two rpi_model +struct members: fdtfiles and fdtcount. + +The new-style revision codes designate LSB bits as board revision; this +value is used to choose between provided FDTs. The first element of the +fdtfiles list is used should no revision match. + +Signed-off-by: Filip Kokosiński +--- + board/raspberrypi/rpi/rpi.c | 93 +++++++++++++++++++++---------------- + 1 file changed, 52 insertions(+), 41 deletions(-) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index f9b643555dd..1b404b448f3 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -94,120 +94,125 @@ struct efi_capsule_update_info update_info = { + */ + struct rpi_model { + const char *name; +- const char *fdtfile; ++ const char * const *fdtfiles; ++ size_t fdtcount; + bool has_onboard_eth; + }; + ++#define FDTFILES(...) \ ++ (const char *[]){ __VA_ARGS__ }, \ ++ sizeof((const char *[]){ __VA_ARGS__ }) / sizeof(const char *) ++ + static const struct rpi_model rpi_model_unknown = { + "Unknown model", +- DTB_DIR "bcm283x-rpi-other.dtb", ++ FDTFILES(DTB_DIR "bcm283x-rpi-other.dtb"), + false, + }; + + static const struct rpi_model rpi_models_new_scheme[] = { + [0x0] = { + "Model A", +- DTB_DIR "bcm2835-rpi-a.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), + false, + }, + [0x1] = { + "Model B", +- DTB_DIR "bcm2835-rpi-b.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b.dtb"), + true, + }, + [0x2] = { + "Model A+", +- DTB_DIR "bcm2835-rpi-a-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-a-plus.dtb"), + false, + }, + [0x3] = { + "Model B+", +- DTB_DIR "bcm2835-rpi-b-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-plus.dtb"), + true, + }, + [0x4] = { + "2 Model B", +- DTB_DIR "bcm2836-rpi-2-b.dtb", ++ FDTFILES(DTB_DIR "bcm2836-rpi-2-b.dtb"), + true, + }, + [0x6] = { + "Compute Module", +- DTB_DIR "bcm2835-rpi-cm.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-cm.dtb"), + false, + }, + [0x8] = { + "3 Model B", +- DTB_DIR "bcm2837-rpi-3-b.dtb", ++ FDTFILES(DTB_DIR "bcm2837-rpi-3-b.dtb"), + true, + }, + [0x9] = { + "Zero", +- DTB_DIR "bcm2835-rpi-zero.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-zero.dtb"), + false, + }, + [0xA] = { + "Compute Module 3", +- DTB_DIR "bcm2837-rpi-cm3.dtb", ++ FDTFILES(DTB_DIR "bcm2837-rpi-cm3.dtb"), + false, + }, + [0xC] = { + "Zero W", +- DTB_DIR "bcm2835-rpi-zero-w.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-zero-w.dtb"), + false, + }, + [0xD] = { + "3 Model B+", +- DTB_DIR "bcm2837-rpi-3-b-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2837-rpi-3-b-plus.dtb"), + true, + }, + [0xE] = { + "3 Model A+", +- DTB_DIR "bcm2837-rpi-3-a-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2837-rpi-3-a-plus.dtb"), + false, + }, + [0x10] = { + "Compute Module 3+", +- DTB_DIR "bcm2837-rpi-cm3.dtb", ++ FDTFILES(DTB_DIR "bcm2837-rpi-cm3.dtb"), + false, + }, + [0x11] = { + "4 Model B", +- DTB_DIR "bcm2711-rpi-4-b.dtb", ++ FDTFILES(DTB_DIR "bcm2711-rpi-4-b.dtb"), + true, + }, + [0x12] = { + "Zero 2 W", +- DTB_DIR "bcm2837-rpi-zero-2-w.dtb", ++ FDTFILES(DTB_DIR "bcm2837-rpi-zero-2-w.dtb"), + false, + }, + [0x13] = { + "400", +- DTB_DIR "bcm2711-rpi-400.dtb", ++ FDTFILES(DTB_DIR "bcm2711-rpi-400.dtb"), + true, + }, + [0x14] = { + "Compute Module 4", +- DTB_DIR "bcm2711-rpi-cm4.dtb", ++ FDTFILES(DTB_DIR "bcm2711-rpi-cm4.dtb"), + true, + }, + [0x17] = { + "5 Model B", +- DTB_DIR "bcm2712-rpi-5-b.dtb", ++ FDTFILES(DTB_DIR "bcm2712-rpi-5-b.dtb"), + true, + }, + [0x18] = { + "Compute Module 5", +- DTB_DIR "bcm2712-rpi-cm5-cm5io.dtb", ++ FDTFILES(DTB_DIR "bcm2712-rpi-cm5-cm5io.dtb"), + true, + }, + [0x19] = { + "500", +- DTB_DIR "bcm2712-rpi-500.dtb", ++ FDTFILES(DTB_DIR "bcm2712-rpi-500.dtb"), + true, + }, + [0x1A] = { + "Compute Module 5 Lite", +- DTB_DIR "bcm2712-rpi-cm5l-cm5io.dtb", ++ FDTFILES(DTB_DIR "bcm2712-rpi-cm5l-cm5io.dtb"), + true, + }, + }; +@@ -215,87 +220,87 @@ static const struct rpi_model rpi_models_new_scheme[] = { + static const struct rpi_model rpi_models_old_scheme[] = { + [0x2] = { + "Model B", +- DTB_DIR "bcm2835-rpi-b.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b.dtb"), + true, + }, + [0x3] = { + "Model B", +- DTB_DIR "bcm2835-rpi-b.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b.dtb"), + true, + }, + [0x4] = { + "Model B rev2", +- DTB_DIR "bcm2835-rpi-b-rev2.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), + true, + }, + [0x5] = { + "Model B rev2", +- DTB_DIR "bcm2835-rpi-b-rev2.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), + true, + }, + [0x6] = { + "Model B rev2", +- DTB_DIR "bcm2835-rpi-b-rev2.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), + true, + }, + [0x7] = { + "Model A", +- DTB_DIR "bcm2835-rpi-a.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), + false, + }, + [0x8] = { + "Model A", +- DTB_DIR "bcm2835-rpi-a.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), + false, + }, + [0x9] = { + "Model A", +- DTB_DIR "bcm2835-rpi-a.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), + false, + }, + [0xd] = { + "Model B rev2", +- DTB_DIR "bcm2835-rpi-b-rev2.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), + true, + }, + [0xe] = { + "Model B rev2", +- DTB_DIR "bcm2835-rpi-b-rev2.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), + true, + }, + [0xf] = { + "Model B rev2", +- DTB_DIR "bcm2835-rpi-b-rev2.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), + true, + }, + [0x10] = { + "Model B+", +- DTB_DIR "bcm2835-rpi-b-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-plus.dtb"), + true, + }, + [0x11] = { + "Compute Module", +- DTB_DIR "bcm2835-rpi-cm.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-cm.dtb"), + false, + }, + [0x12] = { + "Model A+", +- DTB_DIR "bcm2835-rpi-a-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-a-plus.dtb"), + false, + }, + [0x13] = { + "Model B+", +- DTB_DIR "bcm2835-rpi-b-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-b-plus.dtb"), + true, + }, + [0x14] = { + "Compute Module", +- DTB_DIR "bcm2835-rpi-cm.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-cm.dtb"), + false, + }, + [0x15] = { + "Model A+", +- DTB_DIR "bcm2835-rpi-a-plus.dtb", ++ FDTFILES(DTB_DIR "bcm2835-rpi-a-plus.dtb"), + false, + }, + }; +@@ -361,11 +366,17 @@ int dram_init_banksize(void) + static void set_fdtfile(void) + { + const char *fdtfile; ++ int rev = revision & 0x0f; + + if (env_get("fdtfile")) + return; + +- fdtfile = model->fdtfile; ++ /* set the first entry as default */ ++ fdtfile = model->fdtfiles[0]; ++ ++ if (rev < model->fdtcount) ++ fdtfile = model->fdtfiles[rev]; ++ + env_set("fdtfile", fdtfile); + } + + +From patchwork Mon Feb 16 18:44:52 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?q?Filip_Kokosi=C5=84ski?= + +X-Patchwork-Id: 2196988 +X-Patchwork-Delegate: pbrobinson@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 + header.s=20230601 header.b=dGBP4JQ4; + dkim-atps=neutral +Authentication-Results: legolas.ozlabs.org; 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+ Mon, 16 Feb 2026 10:45:15 -0800 (PST) +Received: from desktop.home (83.23.200.152.ipv4.supernova.orange.pl. + [83.23.200.152]) by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-4835dd0e327sm449404165e9.14.2026.02.16.10.45.15 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Mon, 16 Feb 2026 10:45:15 -0800 (PST) +From: =?utf-8?q?Filip_Kokosi=C5=84ski?= +To: u-boot@lists.denx.de +Cc: mbrugger@suse.com, pbrobinson@gmail.com, + =?utf-8?q?Filip_Kokosi=C5=84ski?= +Subject: [PATCH 2/2] board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi + 5 +Date: Mon, 16 Feb 2026 19:44:52 +0100 +Message-ID: <20260216184452.18732-3-filip.kokosinski@gmail.com> +X-Mailer: git-send-email 2.51.2 +In-Reply-To: <20260216184452.18732-1-filip.kokosinski@gmail.com> +References: <20260216184452.18732-1-filip.kokosinski@gmail.com> +MIME-Version: 1.0 +X-Mailman-Approved-At: Mon, 16 Feb 2026 20:51:34 +0100 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +This commit adds an FDT entry for the d0 stepping of the BCM2712 SoC. +This entry is used by the v1.1 revision of the board +(revision & 0x0f == 1). + +Signed-off-by: Filip Kokosiński +--- + board/raspberrypi/rpi/rpi.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index 1b404b448f3..3d61d08f3a4 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -197,7 +197,10 @@ static const struct rpi_model rpi_models_new_scheme[] = { + }, + [0x17] = { + "5 Model B", +- FDTFILES(DTB_DIR "bcm2712-rpi-5-b.dtb"), ++ FDTFILES( ++ [0] = DTB_DIR "bcm2712-rpi-5-b.dtb", ++ [1] = DTB_DIR "bcm2712d0-rpi-5-b.dtb" ++ ), + true, + }, + [0x18] = { diff --git a/uboot-tools.spec b/uboot-tools.spec index 7fa8294..b707995 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.3%{?candidate:.%{candidate}}%{?dist} +Release: 0.4%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -53,6 +53,7 @@ Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi Patch17: rpi-pass-the-Video-Core-logs-DT-parameter-through.patch Patch18: rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch +Patch19: board-raspberry-add-FDT-for-bcm2712d0.patch BuildRequires: bc BuildRequires: bison @@ -310,6 +311,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Feb 17 2026 Peter Robinson - 1:2026.04-0.4.rc2 +- Add initial bcm2712d0 identification + * Mon Feb 09 2026 Peter Robinson - 1:2026.04-0.3.rc2 - Update to 2026.04 RC2 From dc88389af876cb9f5756245aa07e475e775efe70 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 19 Feb 2026 15:08:53 +0000 Subject: [PATCH 16/38] add optee-os-firmware-armv8 BR --- uboot-tools.spec | 1 + 1 file changed, 1 insertion(+) diff --git a/uboot-tools.spec b/uboot-tools.spec index b707995..76e1b0b 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -75,6 +75,7 @@ BuildRequires: swig %if %{with toolsonly} %ifarch aarch64 BuildRequires: arm-trusted-firmware-armv8 +BuildRequires: optee-os-firmware-armv8 BuildRequires: crust-firmware BuildRequires: python3-pyelftools BuildRequires: xxd From af27a7ebf86c700dcba2504d855932ee98c04b70 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 27 Feb 2026 19:42:51 +0000 Subject: [PATCH 17/38] 2026.04 RC3, bcm2712 PCIe support, efi part info proto --- ARM-RPi5-Enable-PCIe.patch | 1852 +++++++++++++++++ ...TITION_INFO_PROTOCOL-support-for-MBR.patch | 1527 ++++++++++++++ sources | 2 +- uboot-tools.spec | 9 +- 4 files changed, 3387 insertions(+), 3 deletions(-) create mode 100644 ARM-RPi5-Enable-PCIe.patch create mode 100644 efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch new file mode 100644 index 0000000..dbde8f7 --- /dev/null +++ b/ARM-RPi5-Enable-PCIe.patch @@ -0,0 +1,1852 @@ +From patchwork Fri Feb 27 15:23:26 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202409 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsY408lKz1xy2 + for ; Sat, 28 Feb 2026 02:23:35 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 15CF383EB3; + Fri, 27 Feb 2026 16:23:33 +0100 (CET) +Authentication-Results: phobos.denx.de; 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Fri, 27 Feb 2026 16:23:26 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152326.EAEE468B05@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:26 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Add a mapping region for the PCIe bus address spaces to the BCM2712 +memory controller setup. Generously merging the PCIe address spaces +works sufficiently well for a boot loader. + +Signed-off-by: Torsten Duwe +--- + arch/arm/mach-bcm283x/init.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 7a1de22e0ae..7a2faaa4de6 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -18,7 +18,7 @@ + #ifdef CONFIG_ARM64 + #include + +-#define MEM_MAP_MAX_ENTRIES (4) ++#define MEM_MAP_MAX_ENTRIES (5) + + static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { + { +@@ -83,6 +83,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ /* Whole PCIe section */ ++ .virt = 0x1800000000UL, ++ .phys = 0x1800000000UL, ++ .size = 0x0800000000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* SoC bus */ + .virt = 0x107c000000UL, + +From patchwork Fri Feb 27 15:23:29 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202410 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYB682xz1xy2 + for ; Sat, 28 Feb 2026 02:23:42 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 5E6F583E88; + Fri, 27 Feb 2026 16:23:34 +0100 (CET) +Authentication-Results: phobos.denx.de; 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Fri, 27 Feb 2026 16:23:29 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 2/9] pci: brcmstb: Fix PCIe bus numbers +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152329.7C72C68BFE@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:29 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Andrea della Porta + +The linux kernel assigns a new domain for every Root Complex where bus +numbering starts from 0 for each domain. U-Boot does not have domains +and uses a flattened bus numbering scheme instead. This means that any +device or bridge on the second enumerated RC will receive a bus number +equal to the last assigned one +1. This bus number contributes to the +address written into the index register, which will select the +configuration space to be read. Compensate for this contribution by +subtracting the base bus number. + +Signed-off-by: Andrea della Porta +Signed-off-by: Torsten Duwe +--- + drivers/pci/pcie_brcmstb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index f089c48f028..47c0802df23 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -125,7 +125,7 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, + uint offset, void **paddress) + { + struct brcm_pcie *pcie = dev_get_priv(dev); +- unsigned int pci_bus = PCI_BUS(bdf); ++ unsigned int pci_bus = PCI_BUS(bdf) - dev_seq(dev); + unsigned int pci_dev = PCI_DEV(bdf); + unsigned int pci_func = PCI_FUNC(bdf); + int idx; + +From patchwork Fri Feb 27 15:23:31 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202411 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYM0tXtz1xy2 + for ; Sat, 28 Feb 2026 02:23:51 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 98AF483E96; + Fri, 27 Feb 2026 16:23:36 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id C1F7983EF9; Fri, 27 Feb 2026 16:23:34 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, + RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no + autolearn_force=no version=3.4.2 +Received: from verein.lst.de (verein.lst.de [213.95.11.211]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by phobos.denx.de (Postfix) with ESMTPS id AAFE683E76 + for ; Fri, 27 Feb 2026 16:23:32 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id 9A6CD68C7B; Fri, 27 Feb 2026 16:23:31 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 3/9] pci: brcmstb: Support different variants using a cfg + struct +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152331.9A6CD68C7B@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:31 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +The Linux kernel driver already had support for multiple hardware +variants when the bcm2712 was added (see e.g. linux commit +10dbedad3c818 which is the last in a longer set of changes). This +patch brings in this required infrastructure and adds a +differentiation between 2711 and 2712 register layouts on top. +It also accounts for the bcm2712 reset logic quirk that the software +init bit must not remain set, albeit the reset control location is +only corrected in patch#6 of this series. + +Signed-off-by: Torsten Duwe +--- + .../mach-bcm283x/include/mach/acpi/bcm2711.h | 6 +- + drivers/pci/pcie_brcmstb.c | 122 ++++++++++++++++-- + 2 files changed, 114 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +index a86875b1833..6eb5389b858 100644 +--- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h ++++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +@@ -70,6 +70,7 @@ + #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 + #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c + #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f ++#define PCIE_MISC_PCIE_CTRL 0x4064 + #define PCIE_MISC_PCIE_STATUS 0x4068 + #define STATUS_PCIE_PORT_MASK 0x80 + #define STATUS_PCIE_PORT_SHIFT 7 +@@ -107,7 +108,10 @@ + #define PCIE_MSI_INTR2_MASK_SET 0x4510 + + #define PCIE_RGR1_SW_INIT_1 0x9210 +-#define PCIE_EXT_CFG_INDEX 0x9000 ++#define RGR1_SW_INIT_1_PERST_MASK 0x1 ++#define RGR1_SW_INIT_1_PERSTB_MASK 0x4 ++#define RGR1_SW_INIT_1_INIT_MASK 0x2 ++ + /* A small window pointing at the ECAM of the device selected by CFG_INDEX */ + #define PCIE_EXT_CFG_DATA 0x8000 + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 47c0802df23..261f8790528 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -49,6 +49,28 @@ + #define SSC_STATUS_PLL_LOCK_MASK 0x800 + #define SSC_STATUS_PLL_LOCK_SHIFT 11 + ++enum { ++ RGR1_SW_INIT_1, ++ EXT_CFG_INDEX, ++ EXT_CFG_DATA, ++ PCIE_HARD_DEBUG, ++}; ++ ++enum brcm_pcie_type { ++ BCM2711, ++ BCM2712 ++}; ++ ++struct brcm_pcie; ++ ++struct brcm_pcie_cfg_data { ++ const int *offsets; ++ const enum brcm_pcie_type type; ++ void (*perst_set)(struct brcm_pcie *pcie, u32 val); ++ void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); ++ bool (*rc_mode)(struct brcm_pcie *pcie); ++}; ++ + /** + * struct brcm_pcie - the PCIe controller state + * @base: Base address of memory mapped IO registers of the controller +@@ -61,6 +83,7 @@ struct brcm_pcie { + + int gen; + bool ssc; ++ const struct brcm_pcie_cfg_data *pcie_cfg; + }; + + /** +@@ -104,6 +127,36 @@ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) + return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; + } + ++static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) ++{ ++ if (val) ++ setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_PERST_MASK); ++ else ++ clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_PERST_MASK); ++} ++ ++static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) ++{ ++ u32 tmp; ++ ++ /* Perst bit has moved and assert value is 0 */ ++ tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); ++ u32p_replace_bits(&tmp, !val, RGR1_SW_INIT_1_PERSTB_MASK); ++ writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); ++} ++ ++static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) ++{ ++ if (val) ++ setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_INIT_MASK); ++ else ++ clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ RGR1_SW_INIT_1_INIT_MASK); ++} ++ + /** + * brcm_pcie_link_up() - Check whether the PCIe link is up + * @pcie: Pointer to the PCIe controller state +@@ -150,8 +203,8 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, + /* For devices, write to the config space index register */ + idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0); + +- writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); +- *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; ++ writel(idx, pcie->base + pcie->pcie_cfg->offsets[EXT_CFG_INDEX]); ++ *paddress = pcie->base + pcie->pcie_cfg->offsets[EXT_CFG_DATA] + offset; + + return 0; + } +@@ -365,8 +418,9 @@ static int brcm_pcie_probe(struct udevice *dev) + * e.g. BCM7278, the fundamental reset should not be asserted here. + * This will need to be changed when support for other SoCs is added. + */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, +- PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK); ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 1); ++ if (pcie->pcie_cfg->type != BCM2712) ++ pcie->pcie_cfg->perst_set(pcie, 1); + /* + * The delay is a safety precaution to preclude the reset signal + * from looking like a glitch. +@@ -374,9 +428,9 @@ static int brcm_pcie_probe(struct udevice *dev) + udelay(100); + + /* Take the bridge out of reset */ +- clrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 0); + +- clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], + PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); + + /* Wait for SerDes to be stable */ +@@ -426,8 +480,7 @@ static int brcm_pcie_probe(struct udevice *dev) + brcm_pcie_set_gen(pcie, pcie->gen); + + /* Unassert the fundamental reset */ +- clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, +- PCIE_RGR1_SW_INIT_1_PERST_MASK); ++ pcie->pcie_cfg->perst_set(pcie, 0); + + /* + * Wait for 100ms after PERST# deassertion; see PCIe CEM specification +@@ -446,7 +499,7 @@ static int brcm_pcie_probe(struct udevice *dev) + return -EINVAL; + } + +- if (!brcm_pcie_rc_mode(pcie)) { ++ if (!pcie->pcie_cfg->rc_mode(pcie)) { + printf("PCIe misconfigured; is in EP mode\n"); + return -EINVAL; + } +@@ -514,14 +567,25 @@ static int brcm_pcie_remove(struct udevice *dev) + void __iomem *base = pcie->base; + + /* Assert fundamental reset */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK); ++ setbits_le32(base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], ++ PCIE_RGR1_SW_INIT_1_PERST_MASK); + + /* Turn off SerDes */ +- setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ setbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], + PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); + + /* Shutdown bridge */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 1); ++ ++ /* ++ * For the controllers that are utilizing reset for bridge Sw init, ++ * such as BCM2712, reset should be deasserted after assertion. ++ * Leaving it in asserted state may lead to unexpected hangs in ++ * the Linux Kernel driver because it do not perform reset initialization ++ * and start accessing device memory. ++ */ ++ if (pcie->pcie_cfg->type == BCM2712) ++ pcie->pcie_cfg->bridge_sw_init_set(pcie, 0); + + return 0; + } +@@ -546,6 +610,7 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) + else + pcie->gen = max_link_speed; + ++ pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); + return 0; + } + +@@ -554,8 +619,39 @@ static const struct dm_pci_ops brcm_pcie_ops = { + .write_config = brcm_pcie_write_config, + }; + ++static const int pcie_offsets[] = { ++ [RGR1_SW_INIT_1] = 0x9210, ++ [EXT_CFG_INDEX] = 0x9000, ++ [EXT_CFG_DATA] = 0x8000, ++ [PCIE_HARD_DEBUG] = 0x4204, ++}; ++ ++static const struct brcm_pcie_cfg_data bcm2711_cfg = { ++ .offsets = pcie_offsets, ++ .type = BCM2711, ++ .perst_set = brcm_pcie_perst_set_generic, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++ .rc_mode = brcm_pcie_rc_mode, ++}; ++ ++static const int pcie_offsets_bcm2712[] = { ++ [RGR1_SW_INIT_1] = 0x0, ++ [EXT_CFG_INDEX] = 0x9000, ++ [EXT_CFG_DATA] = 0x8000, ++ [PCIE_HARD_DEBUG] = 0x4304, ++}; ++ ++static const struct brcm_pcie_cfg_data bcm2712_cfg = { ++ .offsets = pcie_offsets_bcm2712, ++ .type = BCM2712, ++ .perst_set = brcm_pcie_perst_set_2712, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++ .rc_mode = brcm_pcie_rc_mode, ++}; ++ + static const struct udevice_id brcm_pcie_ids[] = { +- { .compatible = "brcm,bcm2711-pcie" }, ++ { .compatible = "brcm,bcm2711-pcie", .data = (ulong)&bcm2711_cfg }, ++ { .compatible = "brcm,bcm2712-pcie", .data = (ulong)&bcm2712_cfg }, + { } + }; + + +From patchwork Fri Feb 27 15:23:34 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202412 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYX5WvXz1xy2 + for ; Sat, 28 Feb 2026 02:24:00 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id D5E9983F14; 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spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id 4A0BE68D07; Fri, 27 Feb 2026 16:23:34 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 4/9] pci: brcmstb: Add RPi5 reset facilities +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152334.4A0BE68D07@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:34 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +A driver for Broadcom reset controllers ported from +linux/drivers/reset/reset-brcmstb.c to U-Boot. + +Signed-off-by: Torsten Duwe +--- + configs/rpi_arm64_defconfig | 1 + + drivers/reset/Kconfig | 7 +++ + drivers/reset/Makefile | 1 + + drivers/reset/reset-brcmstb.c | 97 +++++++++++++++++++++++++++++++++++ + 4 files changed, 106 insertions(+) + create mode 100644 drivers/reset/reset-brcmstb.c + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 69e8e72c5d7..153d7ed301e 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -44,6 +44,7 @@ CONFIG_BCMGENET=y + CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set ++CONFIG_RESET_BRCMSTB=y + CONFIG_DM_RNG=y + CONFIG_RNG_IPROC200=y + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 2fd91d6299c..46ffc103320 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -64,6 +64,13 @@ config RESET_BCM6345 + help + Support reset controller on BCM6345. + ++config RESET_BRCMSTB ++ bool "Generic Reset controller driver for Broadcom" ++ help ++ This enables reset controller for Broadcom devices. ++ If you wish to use reset resources managed by the Broadcom ++ Reset Controller, say Y here. Otherwise, say N. ++ + config RESET_UNIPHIER + bool "Reset controller driver for UniPhier SoCs" + depends on ARCH_UNIPHIER +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index ee5b009d134..ebf3d7425a4 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o + obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o + obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o + obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o ++obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o + obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o + obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o + obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c +new file mode 100644 +index 00000000000..7861f7c9baf +--- /dev/null ++++ b/drivers/reset/reset-brcmstb.c +@@ -0,0 +1,97 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB generic reset controller ++ * ++ * Copyright (C) 2024 EPAM Systems ++ * ++ * Moved from linux kernel: ++ * Author: Florian Fainelli ++ * Copyright (C) 2018 Broadcom ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct brcmstb_reset { ++ void __iomem *base; ++}; ++ ++#define SW_INIT_SET 0x00 ++#define SW_INIT_CLEAR 0x04 ++#define SW_INIT_STATUS 0x08 ++ ++#define SW_INIT_BIT(id) BIT((id) & 0x1f) ++#define SW_INIT_BANK(id) ((id) >> 5) ++ ++#define usleep_range(a, b) udelay((b)) ++ ++/* A full bank contains extra registers that we are not utilizing but still ++ * qualify as a single bank. ++ */ ++#define SW_INIT_BANK_SIZE 0x18 ++ ++static int brcmstb_reset_assert(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset *priv = dev_get_priv(rst->dev); ++ ++ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_SET); ++ return 0; ++} ++ ++static int brcmstb_reset_deassert(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset *priv = dev_get_priv(rst->dev); ++ ++ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_CLEAR); ++ /* Maximum reset delay after de-asserting a line and seeing block ++ * operation is typically 14us for the worst case, build some slack ++ * here. ++ */ ++ usleep_range(100, 200); ++ return 0; ++} ++ ++static int brcmstb_reset_status(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset *priv = dev_get_priv(rst->dev); ++ ++ return readl_relaxed(priv->base + off + SW_INIT_STATUS) & ++ SW_INIT_BIT(rst->id); ++} ++ ++struct reset_ops brcmstb_reset_reset_ops = { ++ .rst_assert = brcmstb_reset_assert, ++ .rst_deassert = brcmstb_reset_deassert, ++ .rst_status = brcmstb_reset_status}; ++ ++static int brcmstb_reset_probe(struct udevice *dev) ++{ ++ struct brcmstb_reset *priv = dev_get_priv(dev); ++ ++ priv->base = dev_remap_addr(dev); ++ if (!priv->base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct udevice_id brcmstb_reset_ids[] = { ++ {.compatible = "brcm,brcmstb-reset"}, {/* sentinel */}}; ++ ++U_BOOT_DRIVER(brcmstb_reset) = { ++ .name = "brcmstb-reset", ++ .id = UCLASS_RESET, ++ .of_match = brcmstb_reset_ids, ++ .ops = &brcmstb_reset_reset_ops, ++ .probe = brcmstb_reset_probe, ++ .priv_auto = sizeof(struct brcmstb_reset), ++}; + +From patchwork Fri Feb 27 15:23:36 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202413 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYk0pstz1xy2 + for ; Sat, 28 Feb 2026 02:24:10 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 327F183E8E; + Fri, 27 Feb 2026 16:23:41 +0100 (CET) +Authentication-Results: phobos.denx.de; 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Fri, 27 Feb 2026 16:23:36 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 5/9] pci: brcmstb: Add RPi5 rescal reset facilities +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152336.C7C2E68D0A@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:36 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +A driver for Broadcom rescal reset controllers ported from +linux/drivers/reset/reset-brcmstb-rescal.c to U-Boot. + +Signed-off-by: Torsten Duwe +--- + configs/rpi_arm64_defconfig | 1 + + drivers/reset/Kconfig | 7 ++ + drivers/reset/Makefile | 1 + + drivers/reset/reset-brcmstb-rescal.c | 103 +++++++++++++++++++++++++++ + 4 files changed, 112 insertions(+) + create mode 100644 drivers/reset/reset-brcmstb-rescal.c + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 153d7ed301e..38af5029403 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -45,6 +45,7 @@ CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_RESET_BRCMSTB=y ++CONFIG_RESET_BRCMSTB_RESCAL=y + CONFIG_DM_RNG=y + CONFIG_RNG_IPROC200=y + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 46ffc103320..b7d2d4b18d5 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -71,6 +71,13 @@ config RESET_BRCMSTB + If you wish to use reset resources managed by the Broadcom + Reset Controller, say Y here. Otherwise, say N. + ++config RESET_BRCMSTB_RESCAL ++ bool "Generic Rescal Reset controller driver for Broadcom" ++ help ++ Support rescal reset controller on Broadcom. ++ If you wish to use reset resources managed by the Broadcom ++ Reset Controller, say Y here. Otherwise, say N. ++ + config RESET_UNIPHIER + bool "Reset controller driver for UniPhier SoCs" + depends on ARCH_UNIPHIER +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index ebf3d7425a4..c7a9da3268d 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o + obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o + obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o + obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o ++obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o + obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o + obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o + obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c +new file mode 100644 +index 00000000000..fc8fcfa8b3f +--- /dev/null ++++ b/drivers/reset/reset-brcmstb-rescal.c +@@ -0,0 +1,103 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB generic reset controller ++ * ++ * Copyright (C) 2024 EPAM Systems ++ * Moved from linux kernel: ++ * Copyright (C) 2018-2020 Broadcom ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BRCM_RESCAL_START 0x0 ++#define BRCM_RESCAL_START_BIT BIT(0) ++#define BRCM_RESCAL_CTRL 0x4 ++#define BRCM_RESCAL_STATUS 0x8 ++#define BRCM_RESCAL_STATUS_BIT BIT(0) ++ ++struct brcm_rescal_reset { ++ void __iomem *base; ++}; ++ ++/* Also doubles a deassert */ ++static int brcm_rescal_reset_set(struct reset_ctl *rst) ++{ ++ struct brcm_rescal_reset *data = dev_get_priv(rst->dev); ++ void __iomem *base = data->base; ++ u32 reg; ++ int ret; ++ ++ reg = readl(base + BRCM_RESCAL_START); ++ writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); ++ reg = readl(base + BRCM_RESCAL_START); ++ if (!(reg & BRCM_RESCAL_START_BIT)) { ++ dev_err(rst->dev, "failed to start SATA/PCIe rescal\n"); ++ return -EIO; ++ } ++ ++ ret = readl_poll_timeout(base + BRCM_RESCAL_STATUS, reg, ++ (reg & BRCM_RESCAL_STATUS_BIT), 100); ++ if (ret) { ++ dev_err(rst->dev, "time out on SATA/PCIe rescal\n"); ++ return ret; ++ } ++ ++ reg = readl(base + BRCM_RESCAL_START); ++ writel(reg & ~BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); ++ ++ dev_dbg(rst->dev, "SATA/PCIe rescal success\n"); ++ return 0; ++} ++ ++/* A dummy function - deassert/reset does all the work */ ++static int brcm_rescal_reset_assert(struct reset_ctl *rst) ++{ ++ return 0; ++} ++ ++static int brcm_rescal_reset_xlate(struct reset_ctl *reset_ctl, ++ struct ofnode_phandle_args *args) ++{ ++ /* This is needed if #reset-cells == 0. */ ++ return 0; ++} ++ ++static const struct reset_ops brcm_rescal_reset_ops = { ++ .rst_deassert = brcm_rescal_reset_set, ++ .rst_assert = brcm_rescal_reset_assert, ++ .of_xlate = brcm_rescal_reset_xlate, ++}; ++ ++static int brcm_rescal_reset_probe(struct udevice *dev) ++{ ++ struct brcm_rescal_reset *data = dev_get_priv(dev); ++ ++ data->base = dev_remap_addr(dev); ++ if (!data->base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct udevice_id brcm_rescal_reset_of_match[] = { ++ {.compatible = "brcm,bcm7216-pcie-sata-rescal"}, ++ {}, ++}; ++ ++U_BOOT_DRIVER(brcmstb_reset_rescal) = { ++ .name = "brcmstb-reset-rescal", ++ .id = UCLASS_RESET, ++ .of_match = brcm_rescal_reset_of_match, ++ .ops = &brcm_rescal_reset_ops, ++ .probe = brcm_rescal_reset_probe, ++ .priv_auto = sizeof(struct brcm_rescal_reset), ++}; + +From patchwork Fri Feb 27 15:23:41 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202414 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYt68Kqz1xy2 + for ; Sat, 28 Feb 2026 02:24:18 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 720AC83F37; + Fri, 27 Feb 2026 16:23:46 +0100 (CET) +Authentication-Results: phobos.denx.de; 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Fri, 27 Feb 2026 16:23:41 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 6/9] pci: brcmstb: Get and use bridge and rescal reset + properties +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152341.3B6C468D13@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:41 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Check whether the device tree has nodes for the two reset controls and use +them if so. + +Signed-off-by: Torsten Duwe +--- + drivers/pci/pcie_brcmstb.c | 51 +++++++++++++++++++++++++++++++++++++- + 1 file changed, 50 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 261f8790528..1f97cda5cc7 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + /* PCIe parameters */ + #define BRCM_NUM_PCIE_OUT_WINS 4 +@@ -83,6 +84,8 @@ struct brcm_pcie { + + int gen; + bool ssc; ++ struct reset_ctl rescal; ++ struct reset_ctl bridge_reset; + const struct brcm_pcie_cfg_data *pcie_cfg; + }; + +@@ -147,6 +150,34 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); + } + ++static void brcm_pcie_get_resets_dt(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ int ret; ++ ++ ret = reset_get_by_name(dev, "rescal", &pcie->rescal); ++ if (ret) { ++ printf("Unable to get rescal reset\n"); ++ return; ++ } ++ ++ ret = reset_get_by_name(dev, "bridge", &pcie->bridge_reset); ++ if (ret) { ++ printf("Unable to get bridge reset\n"); ++ return; ++ } ++} ++ ++static void brcm_pcie_do_reset(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ int ret; ++ ++ ret = reset_deassert(&pcie->rescal); ++ if (ret) ++ printf("failed to deassert 'rescal'\n"); ++} ++ + static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) + { + if (val) +@@ -157,6 +188,14 @@ static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val + RGR1_SW_INIT_1_INIT_MASK); + } + ++static void brcm_pcie_bridge_sw_init_set_2712(struct brcm_pcie *pcie, u32 val) ++{ ++ if (val) ++ reset_assert(&pcie->bridge_reset); ++ else ++ reset_deassert(&pcie->bridge_reset); ++} ++ + /** + * brcm_pcie_link_up() - Check whether the PCIe link is up + * @pcie: Pointer to the PCIe controller state +@@ -413,6 +452,12 @@ static int brcm_pcie_probe(struct udevice *dev) + u16 nlw, cls, lnksta; + u32 tmp; + ++ /* ++ * Ensure rescal reset for BCM2712 is really disabled. ++ */ ++ if (pcie->pcie_cfg->type == BCM2712) ++ brcm_pcie_do_reset(dev); ++ + /* + * Reset the bridge, assert the fundamental reset. Note for some SoCs, + * e.g. BCM7278, the fundamental reset should not be asserted here. +@@ -611,6 +656,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) + pcie->gen = max_link_speed; + + pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); ++ ++ if (pcie->pcie_cfg->type == BCM2712) ++ brcm_pcie_get_resets_dt(dev); ++ + return 0; + } + +@@ -645,7 +694,7 @@ static const struct brcm_pcie_cfg_data bcm2712_cfg = { + .offsets = pcie_offsets_bcm2712, + .type = BCM2712, + .perst_set = brcm_pcie_perst_set_2712, +- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_2712, + .rc_mode = brcm_pcie_rc_mode, + }; + + +From patchwork Fri Feb 27 15:23:44 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202415 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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+- else if (log2_in >= 16 && log2_in <= 37) +- /* Covers 64KB to 32GB, (inclusive) */ ++ else if (log2_in >= 16 && log2_in <= 36) ++ /* Covers 64KB to 64GB, (inclusive) */ + return log2_in - 15; + + /* Something is awry so disable */ + +From patchwork Fri Feb 27 15:23:48 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202416 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsZG0Fbrz1xy2 + for ; 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Fri, 27 Feb 2026 16:23:49 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id BFF2568BFE; Fri, 27 Feb 2026 16:23:48 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 8/9] pci: brcmstb: rework iBAR handling +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152348.BFF2568BFE@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:48 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Rework the setup of inbound PCIe windows: use the convenience functions +from Linux kernel commit ae6476c6de187 to calculate the BAR offsets and +factor out the setup code into a separate function. + +The Linux kernel first allocates and populates an array of inbound_win[] +and sets the BARs from it later, while U-Boot does it all on the fly, +in one go, so the code is not 1:1 comparable. + +Signed-off-by: Torsten Duwe +--- + drivers/pci/pcie_brcmstb.c | 107 ++++++++++++++++++++++++++++++------- + 1 file changed, 88 insertions(+), 19 deletions(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 8a25fb04563..e5c848c9e8e 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -50,6 +50,29 @@ + #define SSC_STATUS_PLL_LOCK_MASK 0x800 + #define SSC_STATUS_PLL_LOCK_SHIFT 11 + ++#define PCIE_RC_PL_PHY_CTL_15 0x184c ++#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 ++#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff ++ ++#define PCIE_MISC_UBUS_CTRL 0x40a4 ++#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK BIT(13) ++#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK BIT(19) ++#define PCIE_MISC_AXI_READ_ERROR_DATA 0x4170 ++#define PCIE_MISC_UBUS_TIMEOUT 0x40A8 ++#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c ++#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 ++#define PCIE_MISC_RC_BAR4_CONFIG_HI 0x40d8 ++#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK 0xff ++#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI 0x4110 ++#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE 0x1 ++#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK 0xfffff000 ++#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO 0x410c ++ ++#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac ++#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP 0x40b4 ++#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0) ++#define MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 ++ + enum { + RGR1_SW_INIT_1, + EXT_CFG_INDEX, +@@ -437,17 +460,75 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); + } + ++static u32 brcm_bar_reg_offset(int bar) ++{ ++ if (bar <= 3) ++ return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); ++ else ++ return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); ++} ++ ++static u32 brcm_ubus_reg_offset(int bar) ++{ ++ if (bar <= 3) ++ return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); ++ else ++ return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4); ++} ++ ++static void brcm_pcie_set_inbound_windows(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ void __iomem *base = pcie->base; ++ int i, ibar_no, ret; ++ u32 tmp; ++ ++ ibar_no = 0; ++ /* pre-2712 chips leave the first entry empty */ ++ if (pcie->pcie_cfg->type != BCM2712) ++ ibar_no++; ++ ++ /* program inbound windows from OF property "dma-regions" */ ++ for (i = 0; i < 7; i++, ibar_no++) { ++ u64 bar_cpu, bar_size, bar_pci; ++ struct pci_region region; ++ int ubus_bar_offset, rc_bar_offset; ++ ++ ret = pci_get_dma_regions(dev, ®ion, i); ++ if (ret) /* no region #i? Then we're done. */ ++ break; ++ ubus_bar_offset = brcm_ubus_reg_offset(ibar_no + 1); ++ rc_bar_offset = brcm_bar_reg_offset(ibar_no + 1); ++ ++ bar_pci = region.bus_start; ++ bar_cpu = region.phys_start; ++ bar_size = region.size; ++ ++ tmp = lower_32_bits(bar_pci); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); ++ ++ tmp = lower_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; ++ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; ++ writel(tmp, base + ubus_bar_offset); ++ ++ tmp = upper_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; ++ writel(tmp, base + ubus_bar_offset + 4); ++ } ++} ++ + static int brcm_pcie_probe(struct udevice *dev) + { + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + struct brcm_pcie *pcie = dev_get_priv(dev); + void __iomem *base = pcie->base; +- struct pci_region region; + bool ssc_good = false; + int num_out_wins = 0; +- u64 rc_bar2_offset, rc_bar2_size; +- unsigned int scb_size_val; + int i, ret; + u16 nlw, cls, lnksta; + u32 tmp; +@@ -488,23 +569,9 @@ static int brcm_pcie_probe(struct udevice *dev) + MISC_CTRL_CFG_READ_UR_MODE_MASK | + MISC_CTRL_MAX_BURST_SIZE_128); + +- pci_get_dma_regions(dev, ®ion, 0); +- rc_bar2_offset = region.bus_start - region.phys_start; +- rc_bar2_size = 1ULL << fls64(region.size - 1); +- +- tmp = lower_32_bits(rc_bar2_offset); +- u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), +- RC_BAR2_CONFIG_LO_SIZE_MASK); +- writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); +- writel(upper_32_bits(rc_bar2_offset), +- base + PCIE_MISC_RC_BAR2_CONFIG_HI); +- +- scb_size_val = rc_bar2_size ? +- ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ +- ++ /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); +- u32p_replace_bits(&tmp, scb_size_val, +- MISC_CTRL_SCB0_SIZE_MASK); ++ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + /* Disable the PCIe->GISB memory window (RC_BAR1) */ +@@ -521,6 +588,8 @@ static int brcm_pcie_probe(struct udevice *dev) + /* Clear any interrupts we find on boot */ + writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); + ++ brcm_pcie_set_inbound_windows(dev); ++ + if (pcie->gen) + brcm_pcie_set_gen(pcie, pcie->gen); + + +From patchwork Fri Feb 27 15:23:52 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2202417 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsZR5GzHz1xy2 + for ; Sat, 28 Feb 2026 02:24:47 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 2D46783EDF; + Fri, 27 Feb 2026 16:23:57 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id 5671E83F63; Fri, 27 Feb 2026 16:23:56 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, + RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no + autolearn_force=no version=3.4.2 +Received: from verein.lst.de (verein.lst.de [213.95.11.211]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by phobos.denx.de (Postfix) with ESMTPS id 300CA83F56 + for ; Fri, 27 Feb 2026 16:23:54 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id F152968D16; Fri, 27 Feb 2026 16:23:52 +0100 (CET) +In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> +References: <20260227152046.42DE068B05@verein.lst.de> +From: Torsten Duwe +Subject: [PATCH 9/9] pci: brcmstb: Adapt to AXI bridge +To: Peter Robinson , + Matthias Brugger +Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= + =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= + =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= + =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= + =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= + =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= + =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= + =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= + =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= + =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= + =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= + =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= + =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= + =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= + =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= + =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= + =?unknown-8bit?q?=40lists=2Edenx=2Ede?= +Message-Id: <20260227152352.F152968D16@verein.lst.de> +Date: Fri, 27 Feb 2026 16:23:52 +0100 (CET) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +Fix-ups for the BCM root complex when it is located behind an AXI +bridge and clocked with 54MHz. Some are from kernel commit +377bced88c326, some where picked by Oleksii off a now-stale older +branch. All reworked for the simpler setup code in U-Boot. + +Signed-off-by: Torsten Duwe +--- + .../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 + + drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++- + 2 files changed, 64 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +index 6eb5389b858..869482eaffe 100644 +--- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h ++++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +@@ -54,6 +54,7 @@ + #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 + #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 + #define MISC_CTRL_MAX_BURST_SIZE_128 0x0 ++#define MISC_CTRL_MAX_BURST_SIZE_128_2712 0x100000 + #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 + + #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index e5c848c9e8e..bd1dd17e690 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -521,6 +521,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) + } + } + ++static void brcm_pcie_munge_pll(struct brcm_pcie *pcie) ++{ ++ u32 tmp; ++ int ret, i; ++ u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; ++ u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; ++ ++ ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, ++ 0x1600); ++ for (i = 0; i < ARRAY_SIZE(regs); i++) { ++ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); ++ debug("PCIE MDIO pre_refclk 0x%02x = 0x%04x\n", ++ regs[i], tmp); ++ } ++ for (i = 0; i < ARRAY_SIZE(regs); i++) { ++ brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); ++ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); ++ debug("PCIE MDIO post_refclk 0x%02x = 0x%04x\n", ++ regs[i], tmp); ++ } ++ ++ udelay(200); ++} ++ + static int brcm_pcie_probe(struct udevice *dev) + { + struct udevice *ctlr = pci_get_controller(dev); +@@ -562,18 +586,56 @@ static int brcm_pcie_probe(struct udevice *dev) + /* Wait for SerDes to be stable */ + udelay(100); + ++ if (pcie->pcie_cfg->type == BCM2712) { ++ /* Allow a 54MHz (xosc) refclk source */ ++ brcm_pcie_munge_pll(pcie); ++ /* Fix for L1SS errata */ ++ tmp = readl(base + PCIE_RC_PL_PHY_CTL_15); ++ tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; ++ /* PM clock period is 18.52ns (round down) */ ++ tmp |= 0x12; ++ writel(tmp, base + PCIE_RC_PL_PHY_CTL_15); ++ } ++ ++ tmp = (pcie->pcie_cfg->type == BCM2712) ? ++ MISC_CTRL_MAX_BURST_SIZE_128_2712 : ++ MISC_CTRL_MAX_BURST_SIZE_128; + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, + MISC_CTRL_MAX_BURST_SIZE_MASK, + MISC_CTRL_SCB_ACCESS_EN_MASK | + MISC_CTRL_CFG_READ_UR_MODE_MASK | +- MISC_CTRL_MAX_BURST_SIZE_128); ++ MISC_CTRL_PCIE_RCB_MPS_MODE_MASK | ++ tmp); + + /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); + u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + ++ if (pcie->pcie_cfg->type == BCM2712) { ++ /* Suppress AXI error responses and return 1s for read failures */ ++ tmp = readl(base + PCIE_MISC_UBUS_CTRL); ++ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK); ++ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK); ++ writel(tmp, base + PCIE_MISC_UBUS_CTRL); ++ writel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA); ++ ++ /* ++ * Adjust timeouts. The UBUS timeout also affects CRS ++ * completion retries, as the request will get terminated if ++ * either timeout expires, so both have to be a large value ++ * (in clocks of 750MHz). ++ * Set UBUS timeout to 250ms, then set RC config retry timeout ++ * to be ~240ms. ++ * ++ * Setting CRSVis=1 will stop the core from blocking on a CRS ++ * response, but does require the device to be well-behaved... ++ */ ++ writel(0xB2D0000, base + PCIE_MISC_UBUS_TIMEOUT); ++ writel(0xABA0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT); ++ } ++ + /* Disable the PCIe->GISB memory window (RC_BAR1) */ + clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, + RC_BAR1_CONFIG_LO_SIZE_MASK); diff --git a/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch b/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch new file mode 100644 index 0000000..f48690e --- /dev/null +++ b/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch @@ -0,0 +1,1527 @@ +From patchwork Thu Feb 12 20:44:55 2026 +Content-Type: text/plain; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + ffacd0b85a97d-43796ac82f7sm466079f8f.28.2026.02.12.12.45.15 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:15 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 1/7] disk: part_dos: Move header to the main include + directory +Date: Thu, 12 Feb 2026 21:44:55 +0100 +Message-ID: <20260212204511.619392-2-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: IPRNvMIm13yQ-FtMhxNzZkK7Dpa5P_eKViUiJ6XWg7c_1770929117 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +There are two different struct definitions for MBR partition table +entries: one in part_dos.h and a nearly identical one in part_efi.h. + +To enable future consolidation of these two structures, move part_dos.h +to the main include directory. This makes it accessible from other parts +of the codebase, such as part_efi.h, and is the first step toward removing +the redundant definition. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Tom Rini +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_dos.c | 2 +- + {disk => include}/part_dos.h | 0 + 2 files changed, 1 insertion(+), 1 deletion(-) + rename {disk => include}/part_dos.h (100%) + +diff --git a/disk/part_dos.c b/disk/part_dos.c +index 18dd35c9b98e..2545cc6bf5d2 100644 +--- a/disk/part_dos.c ++++ b/disk/part_dos.c +@@ -19,7 +19,7 @@ + #include + #include + #include +-#include "part_dos.h" ++#include + #include + + #define DOS_PART_DEFAULT_SECTOR 512 +diff --git a/disk/part_dos.h b/include/part_dos.h +similarity index 100% +rename from disk/part_dos.h +rename to include/part_dos.h + +From patchwork Thu Feb 12 20:44:56 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196075 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48371a298ebsm1026155e9.13.2026.02.12.12.45.17 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:17 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 2/7] disk: part_dos: Align dos_partition_t with struct + partition +Date: Thu, 12 Feb 2026 21:44:56 +0100 +Message-ID: <20260212204511.619392-3-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: fPt7jBSAujrv4TDFANb7Za8r3XesZKgoNdRV6-QyxLM_1770929120 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The dos_partition_t struct defined in part_dos.h is nearly identical to +the struct partition defined in part_efi.h. They differ primarily in how +define their starting sector and number of sectors fields. + +The former uses unsigned char arrays while the latter uses __le32 types. +Using __le32 is preferable, as it removes the ambiguity and potential +misuse of a raw byte array. This also aligns the structure with how the +Linux kernel defines it nowadays, which is the original source of it. + +To prepare for future consolidation where one of the data structures can +be removed, this change aligns both definitions and updates all accessors +for dos_partition_t. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Tom Rini +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_dos.c | 16 ++++++++-------- + include/part_dos.h | 6 +++--- + 2 files changed, 11 insertions(+), 11 deletions(-) + +diff --git a/disk/part_dos.c b/disk/part_dos.c +index 2545cc6bf5d2..60c3d6773696 100644 +--- a/disk/part_dos.c ++++ b/disk/part_dos.c +@@ -49,8 +49,8 @@ static int get_bootable(dos_partition_t *p) + static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector, + int part_num, unsigned int disksig) + { +- lbaint_t lba_start = ext_part_sector + get_unaligned_le32(p->start4); +- lbaint_t lba_size = get_unaligned_le32(p->size4); ++ lbaint_t lba_start = ext_part_sector + get_unaligned_le32(&p->start_sect); ++ lbaint_t lba_size = get_unaligned_le32(&p->nr_sects); + + printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength + "u\t%08x-%02x\t%02x%s%s\n", +@@ -185,7 +185,7 @@ static void print_partition_extended(struct blk_desc *desc, + for (i = 0; i < 4; i++, pt++) { + if (is_extended (pt->sys_ind)) { + lbaint_t lba_start +- = get_unaligned_le32 (pt->start4) + relative; ++ = get_unaligned_le32 (&pt->start_sect) + relative; + + print_partition_extended(desc, lba_start, + !ext_part_sector ? lba_start : +@@ -252,8 +252,8 @@ static int part_get_info_extended(struct blk_desc *desc, + else + info->blksz = DOS_PART_DEFAULT_SECTOR; + info->start = (lbaint_t)(ext_part_sector + +- get_unaligned_le32(pt->start4)); +- info->size = (lbaint_t)get_unaligned_le32(pt->size4); ++ get_unaligned_le32(&pt->start_sect)); ++ info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); + part_set_generic_name(desc, part_num, + (char *)info->name); + /* sprintf(info->type, "%d, pt->sys_ind); */ +@@ -281,7 +281,7 @@ static int part_get_info_extended(struct blk_desc *desc, + for (i = 0; i < 4; i++, pt++) { + if (is_extended (pt->sys_ind)) { + lbaint_t lba_start +- = get_unaligned_le32 (pt->start4) + relative; ++ = get_unaligned_le32 (&pt->start_sect) + relative; + + return part_get_info_extended(desc, lba_start, + ext_part_sector == 0 ? lba_start : relative, +@@ -356,8 +356,8 @@ static void mbr_fill_pt_entry(dos_partition_t *pt, lbaint_t start, + pt->sys_ind = sys_ind; + lba_to_chs(start, &pt->cyl, &pt->head, &pt->sector); + lba_to_chs(start + size - 1, &pt->end_cyl, &pt->end_head, &pt->end_sector); +- put_unaligned_le32(relative, &pt->start4); +- put_unaligned_le32(size, &pt->size4); ++ put_unaligned_le32(relative, &pt->start_sect); ++ put_unaligned_le32(size, &pt->nr_sects); + } + + int write_mbr_partitions(struct blk_desc *dev, +diff --git a/include/part_dos.h b/include/part_dos.h +index 505582242281..92956d530637 100644 +--- a/include/part_dos.h ++++ b/include/part_dos.h +@@ -30,8 +30,8 @@ typedef struct dos_partition { + unsigned char end_head; /* end head */ + unsigned char end_sector; /* end sector */ + unsigned char end_cyl; /* end cylinder */ +- unsigned char start4[4]; /* starting sector counting from 0 */ +- unsigned char size4[4]; /* nr of sectors in partition */ +-} dos_partition_t; ++ __le32 start_sect; /* starting sector counting from 0 */ ++ __le32 nr_sects; /* nr of sectors in partition */ ++} __packed dos_partition_t; + + #endif /* _DISK_PART_DOS_H */ + +From patchwork Thu Feb 12 20:44:57 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196076 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (1024-bit key; + unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 + header.s=mimecast20190719 header.b=BA1s+RGr; + dkim-atps=neutral +Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48370a3ecadsm3205185e9.3.2026.02.12.12.45.19 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:20 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 3/7] disk: part_efi: Remove redundant struct partition + definition +Date: Thu, 12 Feb 2026 21:44:57 +0100 +Message-ID: <20260212204511.619392-4-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: waoFTyp5Nb4lUw3OUZ2FyujC5g1lrXxsAubBNTuInkI_1770929122 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +Now that dos_partition_t and struct partition are identical, the duplicated +data structure definition in the part_efi.h header can just be removed. + +This results in a single, shared definition for MBR partition table +entries, instead of having the same definition in two different places. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Tom Rini +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_efi.c | 4 ++-- + include/part_efi.h | 19 +++---------------- + 2 files changed, 5 insertions(+), 18 deletions(-) + +diff --git a/disk/part_efi.c b/disk/part_efi.c +index fb1ed534f861..d8b17ec2e91a 100644 +--- a/disk/part_efi.c ++++ b/disk/part_efi.c +@@ -51,7 +51,7 @@ static inline u32 efi_crc32(const void *buf, u32 len) + * Private function prototypes + */ + +-static int pmbr_part_valid(struct partition *part); ++static int pmbr_part_valid(dos_partition_t *part); + static int is_pmbr_valid(legacy_mbr * mbr); + static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head, + gpt_entry **pgpt_pte); +@@ -990,7 +990,7 @@ int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf) + * + * Returns: 1 if EFI GPT partition type is found. + */ +-static int pmbr_part_valid(struct partition *part) ++static int pmbr_part_valid(dos_partition_t *part) + { + if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && + get_unaligned_le32(&part->start_sect) == 1UL) { +diff --git a/include/part_efi.h b/include/part_efi.h +index fb402df6f13e..2cea50880465 100644 +--- a/include/part_efi.h ++++ b/include/part_efi.h +@@ -18,6 +18,7 @@ + #define _DISK_PART_EFI_H + + #include ++#include + + #define MSDOS_MBR_SIGNATURE 0xAA55 + #define MSDOS_MBR_BOOT_CODE_SIZE 440 +@@ -77,20 +78,6 @@ + /* linux/include/efi.h */ + typedef u16 efi_char16_t; + +-/* based on linux/include/genhd.h */ +-struct partition { +- u8 boot_ind; /* 0x80 - active */ +- u8 head; /* starting head */ +- u8 sector; /* starting sector */ +- u8 cyl; /* starting cylinder */ +- u8 sys_ind; /* What partition type */ +- u8 end_head; /* end head */ +- u8 end_sector; /* end sector */ +- u8 end_cyl; /* end cylinder */ +- __le32 start_sect; /* starting sector counting from 0 */ +- __le32 nr_sects; /* nr of sectors in partition */ +-} __packed; +- + /* based on linux/fs/partitions/efi.h */ + typedef struct _gpt_header { + __le64 signature; +@@ -134,7 +121,7 @@ typedef struct _legacy_mbr { + u8 boot_code[MSDOS_MBR_BOOT_CODE_SIZE]; + __le32 unique_mbr_signature; + __le16 unknown; +- struct partition partition_record[4]; ++ dos_partition_t partition_record[4]; + __le16 signature; + } __packed legacy_mbr; + +@@ -153,7 +140,7 @@ struct efi_partition_info { + u8 system; + u8 reserved[7]; + union { +- struct partition mbr; ++ dos_partition_t mbr; + gpt_entry gpt; + } info; + } __packed; + +From patchwork Thu Feb 12 20:44:58 2026 +Content-Type: text/plain; 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+ } + +-/* Print a partition that is relative to its Extended partition table ++/** ++ * part_get_info_extended() - get partition info for a DOS partition ++ * ++ * @desc: Block device descriptor ++ * @ext_part_sector: Partition table sector ++ * @relative: Relative offset for the partition ++ * @part_num: Current partition number ++ * @which_part: Target partition number ++ * @info: Returns a pointer to the partition info ++ * @disksig: Disk signature ++ * ++ * Return: 0 on success, negative on error + */ + static int part_get_info_extended(struct blk_desc *desc, + lbaint_t ext_part_sector, lbaint_t relative, + +From patchwork Thu Feb 12 20:44:59 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196079 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-4835dcfaae1sm112461635e9.10.2026.02.12.12.45.24 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:24 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas , + Casey Connolly , + Jan Kiszka , Javier Tia , + Rasmus Villemoes , + Varadarajan Narayanan +Subject: [PATCH v2 5/7] disk: part_dos: Refactor to allow retrieving raw MBR + partition data +Date: Thu, 12 Feb 2026 21:44:59 +0100 +Message-ID: <20260212204511.619392-6-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: Zs6NXSgdnPvAWNkwYY8acCGlkSTO_JLJJjyY6Cc_c5o_1770929127 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +Refactor the part_get_info_extended() helper function (which already +recursively traverses DOS partitions) to optionally return the raw MBR +partition structure (dos_partition_t). + +This allows other subsystems, such as EFI, to retrieve the partition +details in the legacy MBR format. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_dos.c | 66 ++++++++++++++++++++++++++++++------------------- + include/part.h | 14 +++++++++++ + 2 files changed, 55 insertions(+), 25 deletions(-) + +diff --git a/disk/part_dos.c b/disk/part_dos.c +index a69ad8962106..4e1d01b2f21e 100644 +--- a/disk/part_dos.c ++++ b/disk/part_dos.c +@@ -204,7 +204,8 @@ static void print_partition_extended(struct blk_desc *desc, + * @relative: Relative offset for the partition + * @part_num: Current partition number + * @which_part: Target partition number +- * @info: Returns a pointer to the partition info ++ * @info: Returns partition information (optional) ++ * @mbr: Returns MBR partition entry (optional) + * @disksig: Disk signature + * + * Return: 0 on success, negative on error +@@ -212,7 +213,9 @@ static void print_partition_extended(struct blk_desc *desc, + static int part_get_info_extended(struct blk_desc *desc, + lbaint_t ext_part_sector, lbaint_t relative, + int part_num, int which_part, +- struct disk_partition *info, uint disksig) ++ struct disk_partition *info, ++ dos_partition_t *mbr, ++ uint disksig) + { + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz); + struct disk_partition wdinfo = { 0 }; +@@ -243,9 +246,11 @@ static int part_get_info_extended(struct blk_desc *desc, + if (CONFIG_IS_ENABLED(PARTITION_UUIDS) && !ext_part_sector) + disksig = get_unaligned_le32(&buffer[DOS_PART_DISKSIG_OFFSET]); + +- ret = part_get_info_whole_disk(desc, &wdinfo); +- if (ret) +- return ret; ++ if (info) { ++ ret = part_get_info_whole_disk(desc, &wdinfo); ++ if (ret) ++ return ret; ++ } + + /* Print all primary/logical partitions */ + pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); +@@ -258,25 +263,29 @@ static int part_get_info_extended(struct blk_desc *desc, + (pt->sys_ind != 0) && + (part_num == which_part) && + (ext_part_sector == 0 || is_extended(pt->sys_ind) == 0)) { +- if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) +- info->blksz = wdinfo.blksz; +- else +- info->blksz = DOS_PART_DEFAULT_SECTOR; +- info->start = (lbaint_t)(ext_part_sector + +- get_unaligned_le32(&pt->start_sect)); +- info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); +- part_set_generic_name(desc, part_num, +- (char *)info->name); +- /* sprintf(info->type, "%d, pt->sys_ind); */ +- strcpy((char *)info->type, "U-Boot"); +- info->bootable = get_bootable(pt); +- if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { +- char str[12]; +- +- sprintf(str, "%08x-%02x", disksig, part_num); +- disk_partition_set_uuid(info, str); ++ if (info) { ++ if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) ++ info->blksz = wdinfo.blksz; ++ else ++ info->blksz = DOS_PART_DEFAULT_SECTOR; ++ info->start = (lbaint_t)(ext_part_sector + ++ get_unaligned_le32(&pt->start_sect)); ++ info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); ++ part_set_generic_name(desc, part_num, ++ (char *)info->name); ++ /* sprintf(info->type, "%d, pt->sys_ind); */ ++ strcpy((char *)info->type, "U-Boot"); ++ info->bootable = get_bootable(pt); ++ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { ++ char str[12]; ++ ++ sprintf(str, "%08x-%02x", disksig, part_num); ++ disk_partition_set_uuid(info, str); ++ } ++ info->sys_ind = pt->sys_ind; + } +- info->sys_ind = pt->sys_ind; ++ if (mbr) ++ memcpy(mbr, pt, sizeof(*mbr)); + return 0; + } + +@@ -296,7 +305,8 @@ static int part_get_info_extended(struct blk_desc *desc, + + return part_get_info_extended(desc, lba_start, + ext_part_sector == 0 ? lba_start : relative, +- part_num, which_part, info, disksig); ++ part_num, which_part, info, ++ mbr, disksig); + } + } + +@@ -328,7 +338,13 @@ static void __maybe_unused part_print_dos(struct blk_desc *desc) + static int __maybe_unused part_get_info_dos(struct blk_desc *desc, int part, + struct disk_partition *info) + { +- return part_get_info_extended(desc, 0, 0, 1, part, info, 0); ++ return part_get_info_extended(desc, 0, 0, 1, part, info, NULL, 0); ++} ++ ++int __maybe_unused part_get_mbr(struct blk_desc *desc, int part, ++ dos_partition_t *mbr) ++{ ++ return part_get_info_extended(desc, 0, 0, 1, part, NULL, mbr, 0); + } + + int is_valid_dos_buf(void *buf) +diff --git a/include/part.h b/include/part.h +index daebbbc2e68f..aed089d00f64 100644 +--- a/include/part.h ++++ b/include/part.h +@@ -704,6 +704,20 @@ int write_mbr_partitions(struct blk_desc *dev, + int layout_mbr_partitions(struct disk_partition *p, int count, + lbaint_t total_sectors); + ++/** ++ * part_get_mbr() - get the MBR partition record of a partition ++ * ++ * This function reads the MBR partition record for a given block ++ * device and partition number. ++ * ++ * @desc: block device descriptor ++ * @part: partition number for which to return the partition record ++ * @mbr: MBR partition record ++ * ++ * Return: 0 on success, otherwise error ++ */ ++int part_get_mbr(struct blk_desc *desc, int part, dos_partition_t *mbr); ++ + #endif + + #if CONFIG_IS_ENABLED(PARTITIONS) + +From patchwork Thu Feb 12 20:45:00 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Javier Martinez Canillas +X-Patchwork-Id: 2196081 +X-Patchwork-Delegate: xypron.glpk@gmx.de +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (1024-bit key; + unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 + header.s=mimecast20190719 header.b=CXh1R16n; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48371a49dc7sm790085e9.31.2026.02.12.12.45.27 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:27 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas , + Maks Mishin , Simon Glass +Subject: [PATCH v2 6/7] efi_loader: disk: Extend EFI_PARTITION_INFO_PROTOCOL + to support MBR +Date: Thu, 12 Feb 2026 21:45:00 +0100 +Message-ID: <20260212204511.619392-7-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: We4wNEbtQuTUTq6Fkgi3HWr3Fx0Twiws4fhF79FLAjg_1770929129 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The EFI_PARTITION_INFO_PROTOCOL provides detailed information about +partitions. The UEFI specification mentions that both GPT and MBR +partition schemes are supported, but the U-Boot implementation only +supports the former. + +This can cause compatibility issues for platforms whose boot ROM only +supports MBR. This change adds support for MBR partition tables to +the protocol, making U-Boot compatible with systems that require a +legacy MBR table. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + lib/efi_loader/efi_disk.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c +index 130c4db9606f..f8a57539ec61 100644 +--- a/lib/efi_loader/efi_disk.c ++++ b/lib/efi_loader/efi_disk.c +@@ -475,9 +475,12 @@ static efi_status_t efi_disk_add_dev( + #if CONFIG_IS_ENABLED(DOS_PARTITION) + case PART_TYPE_DOS: + info->type = PARTITION_TYPE_MBR; +- +- /* TODO: implement support for MBR partition types */ +- log_debug("EFI_PARTITION_INFO_PROTOCOL doesn't support MBR\n"); ++ ret = part_get_mbr(desc, part, &info->info.mbr); ++ if (ret) { ++ log_debug("get MBR for part %d failed %ld\n", ++ part, ret); ++ goto error; ++ } + break; + #endif + default: + +From patchwork Thu Feb 12 20:45:01 2026 +Content-Type: text/plain; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48370ac3564sm6753225e9.5.2026.02.12.12.45.29 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 12 Feb 2026 12:45:29 -0800 (PST) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: Heinrich Schuchardt , eballetb@redhat.com, + Ilias Apalodimas , + Tom Rini , + Javier Martinez Canillas +Subject: [PATCH v2 7/7] efi_selftest: Enhance MBR test for + PARTITION_INFO_PROTOCOL +Date: Thu, 12 Feb 2026 21:45:01 +0100 +Message-ID: <20260212204511.619392-8-javierm@redhat.com> +X-Mailer: git-send-email 2.53.0 +In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> +References: <20260212204511.619392-1-javierm@redhat.com> +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: yunYq1YIsh16Z4DQJL5hOi7pdkGhTA9a43HFld0F1eg_1770929132 +X-Mimecast-Originator: redhat.com +content-type: text/plain; charset="US-ASCII"; x-default=true +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The EFI_PARTITION_INFO_PROTOCOL test was added before the protocol fully +supported MBR partitions. As a result, it lacked specific checks for the +content of the raw MBR partition record. + +Now that MBR support has been implemented, enhance the selftest to provide +coverage for the MBR entries too. + +This verifies that the protocol correctly reads and exposes MBR partition +records and prevents this functionality to regress due future changes. + +Signed-off-by: Javier Martinez Canillas +Acked-by: Ilias Apalodimas +Reviewed-by: Heinrich Schuchardt +--- + +(no changes since v1) + + lib/efi_selftest/efi_selftest_block_device.c | 26 ++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c +index f145e58a267a..9c4be834eebb 100644 +--- a/lib/efi_selftest/efi_selftest_block_device.c ++++ b/lib/efi_selftest/efi_selftest_block_device.c +@@ -19,6 +19,7 @@ + #include "efi_selftest_disk_image.h" + #include + #include ++#include + + /* Block size of compressed disk image */ + #define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8 +@@ -319,6 +320,25 @@ static int execute(void) + u64 pos; + char block_io_aligned[1 << LB_BLOCK_SIZE] __aligned(1 << LB_BLOCK_SIZE); + ++ /* ++ * The test disk image is defined in efi_selftest_disk_image.h, ++ * it contains a single FAT12 partition of 127 sectors size. ++ */ ++ static const dos_partition_t mbr_expected = { ++ .boot_ind = 0x00, ++ .head = 0x00, ++ .sector = 0x02, ++ .cyl = 0x00, ++ .sys_ind = 0x01, /* FAT12 */ ++ .end_head = 0x02, ++ .end_sector = 0x02, ++ .end_cyl = 0x00, ++ /* LBA 1 */ ++ .start_sect = cpu_to_le32(1), ++ /* Size 127 sectors (0x7f) */ ++ .nr_sects = cpu_to_le32(127), ++ }; ++ + /* Connect controller to virtual disk */ + ret = boottime->connect_controller(disk_handle, NULL, NULL, 1); + if (ret != EFI_SUCCESS) { +@@ -405,6 +425,12 @@ static int execute(void) + return EFI_ST_FAILURE; + } + ++ /* Compare the obtained MBR with the expected one for the test partition */ ++ if (memcmp(&part_info->info.mbr, &mbr_expected, sizeof(mbr_expected))) { ++ efi_st_error("MBR partition record mismatch\n"); ++ return EFI_ST_FAILURE; ++ } ++ + /* Open the simple file system protocol */ + ret = boottime->open_protocol(handle_partition, + &guid_simple_file_system_protocol, diff --git a/sources b/sources index ffd26be..5bfc2b2 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.04-rc2.tar.bz2) = 9e88a2bfabcb50b3d8a1c3edf30c087c5ce5853c49bf27b2c6b57ca11f89aa061ad2fa803d8a684a38fe761d7bba6aec23c44115553cb9ce234da4041a38fdcf +SHA512 (u-boot-2026.04-rc3.tar.bz2) = a3a529fedaa517948eeb310ad1bf06a60126942d9b54826fbb56860d20ef1cd899bba3a2f1a9aa6c49ff30666893ec565b462e4f0904463b62537fd09400f0a3 diff --git a/uboot-tools.spec b/uboot-tools.spec index 76e1b0b..17f1a88 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc2 +%global candidate rc3 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.4%{?candidate:.%{candidate}}%{?dist} +Release: 0.5%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -37,6 +37,7 @@ Patch6: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch Patch7: uefi-enable-SetVariableRT-with-volotile-storage.patch # Enable UEFI HTTPS boot for all Fedora firmware Patch8: uefi-enable-https-boot-by-default.patch +Patch9: efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch # Device improvments # USB-PD improvements @@ -54,6 +55,7 @@ Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch Patch17: rpi-pass-the-Video-Core-logs-DT-parameter-through.patch Patch18: rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch Patch19: board-raspberry-add-FDT-for-bcm2712d0.patch +Patch20: ARM-RPi5-Enable-PCIe.patch BuildRequires: bc BuildRequires: bison @@ -312,6 +314,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Fri Feb 27 2026 Peter Robinson - 1:2026.04-0.5.rc3 +- Update to 2026.04 RC3 + * Tue Feb 17 2026 Peter Robinson - 1:2026.04-0.4.rc2 - Add initial bcm2712d0 identification From 131e791158744f48c5f537048dabfdbf52677bed Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 28 Feb 2026 07:03:59 +0000 Subject: [PATCH 18/38] Enable nvme on rpi --- ARM-RPi5-Enable-PCIe.patch | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch index dbde8f7..66396f2 100644 --- a/ARM-RPi5-Enable-PCIe.patch +++ b/ARM-RPi5-Enable-PCIe.patch @@ -1850,3 +1850,28 @@ index e5c848c9e8e..bd1dd17e690 100644 /* Disable the PCIe->GISB memory window (RC_BAR1) */ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, RC_BAR1_CONFIG_LO_SIZE_MASK); +From a39bdc51e25e5f7a701cb6ca4bdc40e8724d9509 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 27 Feb 2026 20:08:21 +0000 +Subject: [PATCH] rpi arm64: enable nvme + +Signed-off-by: Peter Robinson +--- + configs/rpi_arm64_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 38af5029403..a7ffc2368f6 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -42,6 +42,7 @@ CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_MMC_SDHCI_BCMSTB=y + CONFIG_BCMGENET=y + CONFIG_PCI_BRCMSTB=y ++CONFIG_NVME_PCI=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_RESET_BRCMSTB=y +-- +2.53.0 + From e0289997ba5e5a372f9ccac7bd8851e26c082c9a Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 10 Mar 2026 15:10:12 +0000 Subject: [PATCH 19/38] 2026.04 RC4 --- sources | 2 +- uboot-tools.spec | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/sources b/sources index 5bfc2b2..d715641 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.04-rc3.tar.bz2) = a3a529fedaa517948eeb310ad1bf06a60126942d9b54826fbb56860d20ef1cd899bba3a2f1a9aa6c49ff30666893ec565b462e4f0904463b62537fd09400f0a3 +SHA512 (u-boot-2026.04-rc4.tar.bz2) = 101f477c4a01880b9f83ff202796aee4074c6ca84b7911d22aff8bd53aa33c3ee168dfe61687c8a077f9c61b6526e16eaf6f31bf027b3abf348df0ecb7bf5bdd diff --git a/uboot-tools.spec b/uboot-tools.spec index 17f1a88..1151d16 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc3 +%global candidate rc4 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.5%{?candidate:.%{candidate}}%{?dist} +Release: 0.6%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -314,6 +314,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Mar 10 2026 Peter Robinson - 1:2026.04-0.6.rc4 +- Update to 2026.04 RC4 + * Fri Feb 27 2026 Peter Robinson - 1:2026.04-0.5.rc3 - Update to 2026.04 RC3 From 9f32546ebcd909541faccb01845e79744c89ae5e Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 14 Mar 2026 13:20:53 +0000 Subject: [PATCH 20/38] Fixes for RPi5 --- 0001-Add-bcm2712-compat.patch | 24 ++++++++++++++ ...e-naming-for-bcm2712-SoC-RevD-naming.patch | 32 +++++++++++++++++++ uboot-tools.spec | 7 +++- 3 files changed, 62 insertions(+), 1 deletion(-) create mode 100644 0001-Add-bcm2712-compat.patch create mode 100644 0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch diff --git a/0001-Add-bcm2712-compat.patch b/0001-Add-bcm2712-compat.patch new file mode 100644 index 0000000..1e497b8 --- /dev/null +++ b/0001-Add-bcm2712-compat.patch @@ -0,0 +1,24 @@ +From 83612ecf30e9192247ad8c2f67f585360f5ea68b Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 11 Mar 2026 14:27:21 +0000 +Subject: [PATCH] Add bcm2712 compat + +--- + drivers/video/bcm2835.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c +index 0c81e606622..0e0cc1979eb 100644 +--- a/drivers/video/bcm2835.c ++++ b/drivers/video/bcm2835.c +@@ -66,6 +66,7 @@ static int bcm2835_video_probe(struct udevice *dev) + static const struct udevice_id bcm2835_video_ids[] = { + { .compatible = "brcm,bcm2835-hdmi" }, + { .compatible = "brcm,bcm2711-hdmi0" }, ++ { .compatible = "brcm,bcm2712-hdmi0" }, + { .compatible = "brcm,bcm2708-fb" }, + #if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB) + { .compatible = "simple-framebuffer" }, +-- +2.53.0 + diff --git a/0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch b/0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch new file mode 100644 index 0000000..9d96b73 --- /dev/null +++ b/0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch @@ -0,0 +1,32 @@ +From 87d5e067b7d28fcfe806a751451f007fe2f0eba9 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 13 Mar 2026 17:02:45 +0000 +Subject: [PATCH] rpi: Update the naming for bcm2712 SoC RevD naming + +The downstream Raspberry Pi uses two namings for the revD +SoC device trees, both bcm2712d0-rpi-5-b and bcm2712-d-rpi-5-b +but it seems upstream has settled on just the later, so lets +use that as it's the name that maps both upstream and downstream. + +Fixes: c15a7919725 ("board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi 5") +Signed-off-by: Peter Robinson +--- + board/raspberrypi/rpi/rpi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index 7f69e5b6163..b0a1484c0fa 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -199,7 +199,7 @@ static const struct rpi_model rpi_models_new_scheme[] = { + "5 Model B", + FDTFILES( + [0] = DTB_DIR "bcm2712-rpi-5-b.dtb", +- [1] = DTB_DIR "bcm2712d0-rpi-5-b.dtb" ++ [1] = DTB_DIR "bcm2712-d-rpi-5-b.dtb" + ), + true, + }, +-- +2.53.0 + diff --git a/uboot-tools.spec b/uboot-tools.spec index 1151d16..f3ce72b 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.6%{?candidate:.%{candidate}}%{?dist} +Release: 0.7%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -56,6 +56,8 @@ Patch17: rpi-pass-the-Video-Core-logs-DT-parameter-through.patch Patch18: rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch Patch19: board-raspberry-add-FDT-for-bcm2712d0.patch Patch20: ARM-RPi5-Enable-PCIe.patch +Patch21: 0001-Add-bcm2712-compat.patch +Patch22: 0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch BuildRequires: bc BuildRequires: bison @@ -314,6 +316,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Sat Mar 14 2026 Peter Robinson - 1:2026.04-0.7.rc4 +- Raspberry Pi fixes + * Tue Mar 10 2026 Peter Robinson - 1:2026.04-0.6.rc4 - Update to 2026.04 RC4 From 28ef4157f4bb50bf51c80e63f8e2bdcbce47cbbf Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 24 Mar 2026 17:37:52 +0000 Subject: [PATCH 21/38] 2026.04 RC5 --- board-raspberry-add-FDT-for-bcm2712d0.patch | 574 ------------------ ...Video-Core-logs-DT-parameter-through.patch | 31 - ...ll-state-register-values-for-BCM2711.patch | 173 ------ sources | 2 +- uboot-tools.spec | 10 +- 5 files changed, 6 insertions(+), 784 deletions(-) delete mode 100644 board-raspberry-add-FDT-for-bcm2712d0.patch delete mode 100644 rpi-pass-the-Video-Core-logs-DT-parameter-through.patch delete mode 100644 rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch diff --git a/board-raspberry-add-FDT-for-bcm2712d0.patch b/board-raspberry-add-FDT-for-bcm2712d0.patch deleted file mode 100644 index 884911e..0000000 --- a/board-raspberry-add-FDT-for-bcm2712d0.patch +++ /dev/null @@ -1,574 +0,0 @@ -From patchwork Mon Feb 16 18:44:51 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: =?utf-8?q?Filip_Kokosi=C5=84ski?= - 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=?utf-8?q?Filip_Kokosi=C5=84ski?= -Subject: [PATCH 1/2] board/raspberrypi: add multi-FDT support -Date: Mon, 16 Feb 2026 19:44:51 +0100 -Message-ID: <20260216184452.18732-2-filip.kokosinski@gmail.com> -X-Mailer: git-send-email 2.51.2 -In-Reply-To: <20260216184452.18732-1-filip.kokosinski@gmail.com> -References: <20260216184452.18732-1-filip.kokosinski@gmail.com> -MIME-Version: 1.0 -X-Mailman-Approved-At: Mon, 16 Feb 2026 20:51:34 +0100 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -This patch adds support for multiple FDT files per board model. This is -done by adding the FDTFILES macro, which initializes two rpi_model -struct members: fdtfiles and fdtcount. - -The new-style revision codes designate LSB bits as board revision; this -value is used to choose between provided FDTs. The first element of the -fdtfiles list is used should no revision match. - -Signed-off-by: Filip Kokosiński ---- - board/raspberrypi/rpi/rpi.c | 93 +++++++++++++++++++++---------------- - 1 file changed, 52 insertions(+), 41 deletions(-) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index f9b643555dd..1b404b448f3 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -94,120 +94,125 @@ struct efi_capsule_update_info update_info = { - */ - struct rpi_model { - const char *name; -- const char *fdtfile; -+ const char * const *fdtfiles; -+ size_t fdtcount; - bool has_onboard_eth; - }; - -+#define FDTFILES(...) \ -+ (const char *[]){ __VA_ARGS__ }, \ -+ sizeof((const char *[]){ __VA_ARGS__ }) / sizeof(const char *) -+ - static const struct rpi_model rpi_model_unknown = { - "Unknown model", -- DTB_DIR "bcm283x-rpi-other.dtb", -+ FDTFILES(DTB_DIR "bcm283x-rpi-other.dtb"), - false, - }; - - static const struct rpi_model rpi_models_new_scheme[] = { - [0x0] = { - "Model A", -- DTB_DIR "bcm2835-rpi-a.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), - false, - }, - [0x1] = { - "Model B", -- DTB_DIR "bcm2835-rpi-b.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b.dtb"), - true, - }, - [0x2] = { - "Model A+", -- DTB_DIR "bcm2835-rpi-a-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-a-plus.dtb"), - false, - }, - [0x3] = { - "Model B+", -- DTB_DIR "bcm2835-rpi-b-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-plus.dtb"), - true, - }, - [0x4] = { - "2 Model B", -- DTB_DIR "bcm2836-rpi-2-b.dtb", -+ FDTFILES(DTB_DIR "bcm2836-rpi-2-b.dtb"), - true, - }, - [0x6] = { - "Compute Module", -- DTB_DIR "bcm2835-rpi-cm.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-cm.dtb"), - false, - }, - [0x8] = { - "3 Model B", -- DTB_DIR "bcm2837-rpi-3-b.dtb", -+ FDTFILES(DTB_DIR "bcm2837-rpi-3-b.dtb"), - true, - }, - [0x9] = { - "Zero", -- DTB_DIR "bcm2835-rpi-zero.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-zero.dtb"), - false, - }, - [0xA] = { - "Compute Module 3", -- DTB_DIR "bcm2837-rpi-cm3.dtb", -+ FDTFILES(DTB_DIR "bcm2837-rpi-cm3.dtb"), - false, - }, - [0xC] = { - "Zero W", -- DTB_DIR "bcm2835-rpi-zero-w.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-zero-w.dtb"), - false, - }, - [0xD] = { - "3 Model B+", -- DTB_DIR "bcm2837-rpi-3-b-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2837-rpi-3-b-plus.dtb"), - true, - }, - [0xE] = { - "3 Model A+", -- DTB_DIR "bcm2837-rpi-3-a-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2837-rpi-3-a-plus.dtb"), - false, - }, - [0x10] = { - "Compute Module 3+", -- DTB_DIR "bcm2837-rpi-cm3.dtb", -+ FDTFILES(DTB_DIR "bcm2837-rpi-cm3.dtb"), - false, - }, - [0x11] = { - "4 Model B", -- DTB_DIR "bcm2711-rpi-4-b.dtb", -+ FDTFILES(DTB_DIR "bcm2711-rpi-4-b.dtb"), - true, - }, - [0x12] = { - "Zero 2 W", -- DTB_DIR "bcm2837-rpi-zero-2-w.dtb", -+ FDTFILES(DTB_DIR "bcm2837-rpi-zero-2-w.dtb"), - false, - }, - [0x13] = { - "400", -- DTB_DIR "bcm2711-rpi-400.dtb", -+ FDTFILES(DTB_DIR "bcm2711-rpi-400.dtb"), - true, - }, - [0x14] = { - "Compute Module 4", -- DTB_DIR "bcm2711-rpi-cm4.dtb", -+ FDTFILES(DTB_DIR "bcm2711-rpi-cm4.dtb"), - true, - }, - [0x17] = { - "5 Model B", -- DTB_DIR "bcm2712-rpi-5-b.dtb", -+ FDTFILES(DTB_DIR "bcm2712-rpi-5-b.dtb"), - true, - }, - [0x18] = { - "Compute Module 5", -- DTB_DIR "bcm2712-rpi-cm5-cm5io.dtb", -+ FDTFILES(DTB_DIR "bcm2712-rpi-cm5-cm5io.dtb"), - true, - }, - [0x19] = { - "500", -- DTB_DIR "bcm2712-rpi-500.dtb", -+ FDTFILES(DTB_DIR "bcm2712-rpi-500.dtb"), - true, - }, - [0x1A] = { - "Compute Module 5 Lite", -- DTB_DIR "bcm2712-rpi-cm5l-cm5io.dtb", -+ FDTFILES(DTB_DIR "bcm2712-rpi-cm5l-cm5io.dtb"), - true, - }, - }; -@@ -215,87 +220,87 @@ static const struct rpi_model rpi_models_new_scheme[] = { - static const struct rpi_model rpi_models_old_scheme[] = { - [0x2] = { - "Model B", -- DTB_DIR "bcm2835-rpi-b.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b.dtb"), - true, - }, - [0x3] = { - "Model B", -- DTB_DIR "bcm2835-rpi-b.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b.dtb"), - true, - }, - [0x4] = { - "Model B rev2", -- DTB_DIR "bcm2835-rpi-b-rev2.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), - true, - }, - [0x5] = { - "Model B rev2", -- DTB_DIR "bcm2835-rpi-b-rev2.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), - true, - }, - [0x6] = { - "Model B rev2", -- DTB_DIR "bcm2835-rpi-b-rev2.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), - true, - }, - [0x7] = { - "Model A", -- DTB_DIR "bcm2835-rpi-a.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), - false, - }, - [0x8] = { - "Model A", -- DTB_DIR "bcm2835-rpi-a.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), - false, - }, - [0x9] = { - "Model A", -- DTB_DIR "bcm2835-rpi-a.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-a.dtb"), - false, - }, - [0xd] = { - "Model B rev2", -- DTB_DIR "bcm2835-rpi-b-rev2.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), - true, - }, - [0xe] = { - "Model B rev2", -- DTB_DIR "bcm2835-rpi-b-rev2.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), - true, - }, - [0xf] = { - "Model B rev2", -- DTB_DIR "bcm2835-rpi-b-rev2.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-rev2.dtb"), - true, - }, - [0x10] = { - "Model B+", -- DTB_DIR "bcm2835-rpi-b-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-plus.dtb"), - true, - }, - [0x11] = { - "Compute Module", -- DTB_DIR "bcm2835-rpi-cm.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-cm.dtb"), - false, - }, - [0x12] = { - "Model A+", -- DTB_DIR "bcm2835-rpi-a-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-a-plus.dtb"), - false, - }, - [0x13] = { - "Model B+", -- DTB_DIR "bcm2835-rpi-b-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-b-plus.dtb"), - true, - }, - [0x14] = { - "Compute Module", -- DTB_DIR "bcm2835-rpi-cm.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-cm.dtb"), - false, - }, - [0x15] = { - "Model A+", -- DTB_DIR "bcm2835-rpi-a-plus.dtb", -+ FDTFILES(DTB_DIR "bcm2835-rpi-a-plus.dtb"), - false, - }, - }; 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- Mon, 16 Feb 2026 10:45:15 -0800 (PST) -Received: from desktop.home (83.23.200.152.ipv4.supernova.orange.pl. - [83.23.200.152]) by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-4835dd0e327sm449404165e9.14.2026.02.16.10.45.15 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Mon, 16 Feb 2026 10:45:15 -0800 (PST) -From: =?utf-8?q?Filip_Kokosi=C5=84ski?= -To: u-boot@lists.denx.de -Cc: mbrugger@suse.com, pbrobinson@gmail.com, - =?utf-8?q?Filip_Kokosi=C5=84ski?= -Subject: [PATCH 2/2] board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi - 5 -Date: Mon, 16 Feb 2026 19:44:52 +0100 -Message-ID: <20260216184452.18732-3-filip.kokosinski@gmail.com> -X-Mailer: git-send-email 2.51.2 -In-Reply-To: <20260216184452.18732-1-filip.kokosinski@gmail.com> -References: <20260216184452.18732-1-filip.kokosinski@gmail.com> -MIME-Version: 1.0 -X-Mailman-Approved-At: Mon, 16 Feb 2026 20:51:34 +0100 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -This commit adds an FDT entry for the d0 stepping of the BCM2712 SoC. -This entry is used by the v1.1 revision of the board -(revision & 0x0f == 1). - -Signed-off-by: Filip Kokosiński ---- - board/raspberrypi/rpi/rpi.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index 1b404b448f3..3d61d08f3a4 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -197,7 +197,10 @@ static const struct rpi_model rpi_models_new_scheme[] = { - }, - [0x17] = { - "5 Model B", -- FDTFILES(DTB_DIR "bcm2712-rpi-5-b.dtb"), -+ FDTFILES( -+ [0] = DTB_DIR "bcm2712-rpi-5-b.dtb", -+ [1] = DTB_DIR "bcm2712d0-rpi-5-b.dtb" -+ ), - true, - }, - [0x18] = { diff --git a/rpi-pass-the-Video-Core-logs-DT-parameter-through.patch b/rpi-pass-the-Video-Core-logs-DT-parameter-through.patch deleted file mode 100644 index a080d1b..0000000 --- a/rpi-pass-the-Video-Core-logs-DT-parameter-through.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 667e6169e50233060343d081942fc3025196a7dd Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 9 Feb 2026 11:01:17 +0000 -Subject: [PATCH] rpi: pass the Video Core logs DT parameter through - -Pass the VC logs DT parameter through to the kernel -device tree. This is used by the vclog tool and is -a useful debugging tool. - -Signed-off-by: Peter Robinson ---- - board/raspberrypi/rpi/rpi.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index f9b643555dd..7256d66a9a6 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -608,6 +608,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) - /* warnings from the firmware (if any) */ - copy_property(fdt, fw_fdt, "/chosen", "user-warnings"); - -+ /* firmware logs - used by the vclog utility */ -+ copy_property(fdt, fw_fdt, "/chosen", "log"); -+ - /* address of the PHY device as provided by the firmware */ - copy_property(fdt, fw_fdt, "ethernet0/mdio@e14/ethernet-phy@1", "reg"); - --- -2.53.0 - diff --git a/rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch b/rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch deleted file mode 100644 index a14462a..0000000 --- a/rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch +++ /dev/null @@ -1,173 +0,0 @@ -From patchwork Fri Feb 6 10:47:00 2026 -Content-Type: text/plain; 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- Fri, 06 Feb 2026 02:47:08 -0800 (PST) -Received: from cibil-Precision-5570.. - ([2a02:3033:280:4628:c815:77f9:1225:71ed]) - by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-48320728774sm40932795e9.14.2026.02.06.02.47.07 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Fri, 06 Feb 2026 02:47:08 -0800 (PST) -From: Cibil Pankiras -To: u-boot@lists.denx.de -Cc: Matthias Brugger , - Peter Robinson , Tom Rini -Subject: [PATCH v2] pinctrl: bcm283x: Fix GPIO pull state register values for - BCM2711 -Date: Fri, 6 Feb 2026 11:47:00 +0100 -Message-ID: <20260206104701.34358-1-cibil.pankiras@egym.com> -X-Mailer: git-send-email 2.43.0 -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -BCM2711 has different pull-up/down register values compared to BCM2835 - -- BCM2835: NONE=0, DOWN=1, UP=2 -- BCM2711: NONE=0, UP=1, DOWN=2 - -This patch fixes the pull state register values for BCM2711. - -Fixes: 2c39d975f87c ("pinctrl: bcm283x: Add GPIO pull-up/down control for BCM2835 and BCM2711") -Signed-off-by: Cibil Pankiras ---- -Changes in v2: -- Moved pull value swap logic to bcm2711_gpio_set_pull() -- Updated the function header comment for bcm2711_gpio_set_pull() ---- - drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c -index 4ecc8bac645a..90eee88eb137 100644 ---- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c -+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c -@@ -30,6 +30,11 @@ struct bcm283x_pinctrl_priv { - - #define MAX_PINS_PER_BANK 16 - -+/* pull states for BCM2711 */ -+#define BCM2711_PULL_NONE 0 -+#define BCM2711_PULL_UP 1 -+#define BCM2711_PULL_DOWN 2 -+ - static void bcm2835_gpio_set_func_id(struct udevice *dev, unsigned int gpio, - int func) - { -@@ -93,6 +98,17 @@ static void bcm2711_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pu - u32 bit_shift; - u32 pull_bits; - -+ if (!device_is_compatible(dev, "brcm,bcm2711-gpio")) -+ return; -+ -+ /* BCM2711's pull values differ from BCM2835 */ -+ if (pull == BCM2835_PUD_UP) -+ pull = BCM2711_PULL_UP; -+ else if (pull == BCM2835_PUD_DOWN) -+ pull = BCM2711_PULL_DOWN; -+ else -+ pull = BCM2711_PULL_NONE; -+ - /* Findout which GPIO_PUP_PDN_CNTRL register to use */ - reg_offset = BCM2711_GPPUD_CNTRL_REG0 + BCM2711_PUD_REG_OFFSET(gpio); - diff --git a/sources b/sources index d715641..53946e4 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.04-rc4.tar.bz2) = 101f477c4a01880b9f83ff202796aee4074c6ca84b7911d22aff8bd53aa33c3ee168dfe61687c8a077f9c61b6526e16eaf6f31bf027b3abf348df0ecb7bf5bdd +SHA512 (u-boot-2026.04-rc5.tar.bz2) = b7df1080d7cd280cd1aacb86b20f3e799d6f6a86d6cbce4e757eaaf9698a8c148cb35250b91e7196a78e7c8c65545e6c7954ac375cee786690fa1db634956ed2 diff --git a/uboot-tools.spec b/uboot-tools.spec index f3ce72b..f927995 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc4 +%global candidate rc5 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.7%{?candidate:.%{candidate}}%{?dist} +Release: 0.8%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -52,9 +52,6 @@ Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch # Fix AllWinner Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi -Patch17: rpi-pass-the-Video-Core-logs-DT-parameter-through.patch -Patch18: rpi-pinctrl-bcm283x-Fix-GPIO-pull-state-register-values-for-BCM2711.patch -Patch19: board-raspberry-add-FDT-for-bcm2712d0.patch Patch20: ARM-RPi5-Enable-PCIe.patch Patch21: 0001-Add-bcm2712-compat.patch Patch22: 0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch @@ -316,6 +313,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Mar 24 2026 Peter Robinson - 1:2026.04-0.8.rc5 +- Update to 2026.04 RC5 + * Sat Mar 14 2026 Peter Robinson - 1:2026.04-0.7.rc4 - Raspberry Pi fixes From 85a93b85c79342d1da5a633895c2ac1985e3a3b2 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 29 Mar 2026 20:49:58 +0100 Subject: [PATCH 22/38] Enable NVME booting on RPi5 --- ARM-RPi5-Enable-PCIe.patch | 172 ++++++++++++++++++++++++++++++++++--- uboot-tools.spec | 5 +- 2 files changed, 165 insertions(+), 12 deletions(-) diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch index 66396f2..68a3274 100644 --- a/ARM-RPi5-Enable-PCIe.patch +++ b/ARM-RPi5-Enable-PCIe.patch @@ -1850,28 +1850,178 @@ index e5c848c9e8e..bd1dd17e690 100644 /* Disable the PCIe->GISB memory window (RC_BAR1) */ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, RC_BAR1_CONFIG_LO_SIZE_MASK); -From a39bdc51e25e5f7a701cb6ca4bdc40e8724d9509 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Fri, 27 Feb 2026 20:08:21 +0000 -Subject: [PATCH] rpi arm64: enable nvme +From 9e0fc68de1424b3db495f8a661d578435c4137c1 Mon Sep 17 00:00:00 2001 +From: Torsten Duwe +Date: Mon, 2 Mar 2026 13:59:40 +0100 +Subject: [PATCH] Fix NVMe for non-zero bus offsets -Signed-off-by: Peter Robinson +Hi all, + +working on the RPi5 I found that the U-Boot NVMe code is lacking a significant +feature. The NVMe protocol heavily relies on device access into main memory, +in the medieval times of computing this was called "bus master DMA". The NVMe +device must generate memory addresses and read or write contents there. The +current U-Boot code does in no way account for PCIe bridges in the path that +add an offset to such "inbound accesses". Consequently, U-Boot can only boot +from NVMe on platforms where this address offset is zero. +(These are surprisingly many!) + +This proposed patch uses the already existent dev_phys_to_bus(), which can +dig up the correct offset from associated DT nodes and subtract it. I have +no strong opinion on the macro naming, and whether it should silently pull +in the "dev" from the outer scope or have it better passed explicitly. + +Signed-off-by: Torsten Duwe --- - configs/rpi_arm64_defconfig | 1 + - 1 file changed, 1 insertion(+) + drivers/nvme/nvme.c | 29 ++++++++++++++++------------- + 1 file changed, 16 insertions(+), 13 deletions(-) +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 2b14437f69c..039fbe0bc75 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -27,6 +28,8 @@ + #define IO_TIMEOUT 30 + #define MAX_PRP_POOL 512 + ++#define BUS_ADDR(a) dev_phys_to_bus(dev->udev, (a)) ++ + static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) + { + int timeout; +@@ -91,12 +94,12 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + i = 0; + while (nprps) { + if ((i == (prps_per_page - 1)) && nprps > 1) { +- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + +- page_size); ++ *(prp_pool + i) = cpu_to_le64(BUS_ADDR((ulong)prp_pool + ++ page_size)); + i = 0; + prp_pool += page_size; + } +- *(prp_pool + i++) = cpu_to_le64(dma_addr); ++ *(prp_pool + i++) = cpu_to_le64(BUS_ADDR(dma_addr)); + dma_addr += page_size; + nprps--; + } +@@ -393,8 +396,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) + dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; + + writel(aqa, &dev->bar->aqa); +- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); +- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); ++ nvme_writeq(BUS_ADDR((ulong)nvmeq->sq_cmds), &dev->bar->asq); ++ nvme_writeq(BUS_ADDR((ulong)nvmeq->cqes), &dev->bar->acq); + + result = nvme_enable_ctrl(dev); + if (result) +@@ -420,7 +423,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_cq.opcode = nvme_admin_create_cq; +- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); ++ c.create_cq.prp1 = cpu_to_le64(BUS_ADDR((ulong)nvmeq->cqes)); + c.create_cq.cqid = cpu_to_le16(qid); + c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_cq.cq_flags = cpu_to_le16(flags); +@@ -437,7 +440,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_sq.opcode = nvme_admin_create_sq; +- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); ++ c.create_sq.prp1 = cpu_to_le64(BUS_ADDR((ulong)nvmeq->sq_cmds)); + c.create_sq.sqid = cpu_to_le16(qid); + c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_sq.sq_flags = cpu_to_le16(flags); +@@ -458,14 +461,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.identify.opcode = nvme_admin_identify; + c.identify.nsid = cpu_to_le32(nsid); +- c.identify.prp1 = cpu_to_le64(dma_addr); ++ c.identify.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); + + length -= (page_size - offset); + if (length <= 0) { + c.identify.prp2 = 0; + } else { + dma_addr += (page_size - offset); +- c.identify.prp2 = cpu_to_le64(dma_addr); ++ c.identify.prp2 = cpu_to_le64(BUS_ADDR(dma_addr)); + } + + c.identify.cns = cpu_to_le32(cns); +@@ -490,7 +493,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_get_features; + c.features.nsid = cpu_to_le32(nsid); +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + + ret = nvme_submit_admin_cmd(dev, &c, result); +@@ -516,7 +519,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, + + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_set_features; +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + c.features.dword11 = cpu_to_le32(dword11); + +@@ -785,8 +788,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + c.rw.slba = cpu_to_le64(slba); + slba += lbas; + c.rw.length = cpu_to_le16(lbas - 1); +- c.rw.prp1 = cpu_to_le64(temp_buffer); +- c.rw.prp2 = cpu_to_le64(prp2); ++ c.rw.prp1 = cpu_to_le64(BUS_ADDR(temp_buffer)); ++ c.rw.prp2 = cpu_to_le64(BUS_ADDR(prp2)); + status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], + &c, NULL, IO_TIMEOUT); + if (status) +-- +2.53.0 + +From 253adf9d1bbf0a166f63b30f6ce38cac69239a34 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sun, 29 Mar 2026 20:28:41 +0100 +Subject: [PATCH] rpi: enable nvme + +Signed-off-by: Peter Robinson +--- + configs/rpi_arm64_defconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 38af5029403..a7ffc2368f6 100644 +index 38af5029403..ed4ae6ff522 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig -@@ -42,6 +42,7 @@ CONFIG_MMC_SDHCI_BCM2835=y +@@ -15,7 +15,7 @@ CONFIG_BOOTSTD_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_FDT_SIMPLEFB=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="pci enum; usb start;" ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_SYS_PBSIZE=1049 + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -41,6 +41,7 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y CONFIG_MMC_SDHCI_BCMSTB=y CONFIG_BCMGENET=y ++CONFIG_NVME_PCI=y CONFIG_PCI_BRCMSTB=y -+CONFIG_NVME_PCI=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set - CONFIG_RESET_BRCMSTB=y -- 2.53.0 diff --git a/uboot-tools.spec b/uboot-tools.spec index f927995..da4e15d 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.8%{?candidate:.%{candidate}}%{?dist} +Release: 0.9%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -313,6 +313,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Sun Mar 29 2026 Peter Robinson - 1:2026.04-0.9.rc5 +- Enable NVME booting on RPi5 + * Tue Mar 24 2026 Peter Robinson - 1:2026.04-0.8.rc5 - Update to 2026.04 RC5 From 3dacc0c2c7dab987193445cf49996ffcf0882e74 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 7 Apr 2026 11:09:25 +0100 Subject: [PATCH 23/38] 2026.04 GA --- ...e-naming-for-bcm2712-SoC-RevD-naming.patch | 32 ------------------- sources | 2 +- uboot-tools.spec | 8 +++-- 3 files changed, 6 insertions(+), 36 deletions(-) delete mode 100644 0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch diff --git a/0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch b/0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch deleted file mode 100644 index 9d96b73..0000000 --- a/0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 87d5e067b7d28fcfe806a751451f007fe2f0eba9 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Fri, 13 Mar 2026 17:02:45 +0000 -Subject: [PATCH] rpi: Update the naming for bcm2712 SoC RevD naming - -The downstream Raspberry Pi uses two namings for the revD -SoC device trees, both bcm2712d0-rpi-5-b and bcm2712-d-rpi-5-b -but it seems upstream has settled on just the later, so lets -use that as it's the name that maps both upstream and downstream. - -Fixes: c15a7919725 ("board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi 5") -Signed-off-by: Peter Robinson ---- - board/raspberrypi/rpi/rpi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index 7f69e5b6163..b0a1484c0fa 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -199,7 +199,7 @@ static const struct rpi_model rpi_models_new_scheme[] = { - "5 Model B", - FDTFILES( - [0] = DTB_DIR "bcm2712-rpi-5-b.dtb", -- [1] = DTB_DIR "bcm2712d0-rpi-5-b.dtb" -+ [1] = DTB_DIR "bcm2712-d-rpi-5-b.dtb" - ), - true, - }, --- -2.53.0 - diff --git a/sources b/sources index 53946e4..d751131 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.04-rc5.tar.bz2) = b7df1080d7cd280cd1aacb86b20f3e799d6f6a86d6cbce4e757eaaf9698a8c148cb35250b91e7196a78e7c8c65545e6c7954ac375cee786690fa1db634956ed2 +SHA512 (u-boot-2026.04.tar.bz2) = c5fca2abc533759985dfcc6d071d154007535787b0bbd569b61bda1fe2f3a31fba08481c8caf18cf5f2bc79609f50dee504977a8b65e8c4cc21f277268232e03 diff --git a/uboot-tools.spec b/uboot-tools.spec index da4e15d..6f1d767 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc5 +#global candidate rc0 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 0.9%{?candidate:.%{candidate}}%{?dist} +Release: 1%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -54,7 +54,6 @@ Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi Patch20: ARM-RPi5-Enable-PCIe.patch Patch21: 0001-Add-bcm2712-compat.patch -Patch22: 0001-rpi-Update-the-naming-for-bcm2712-SoC-RevD-naming.patch BuildRequires: bc BuildRequires: bison @@ -313,6 +312,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Apr 07 2026 Peter Robinson - 1:2026.04-1 +- Update to 2026.04 GA + * Sun Mar 29 2026 Peter Robinson - 1:2026.04-0.9.rc5 - Enable NVME booting on RPi5 From ae35a50b2f9b3c381d68f870284b353d8c2afded Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 12 Apr 2026 17:39:36 +0100 Subject: [PATCH 24/38] Rasberry Pi 4/5 fixes --- ARM-RPi-PCIe-fixes.patch | 172 ++++++++++++++++++ ...rrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch | 32 ++++ uboot-tools.spec | 8 +- 3 files changed, 211 insertions(+), 1 deletion(-) create mode 100644 ARM-RPi-PCIe-fixes.patch create mode 100644 raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch diff --git a/ARM-RPi-PCIe-fixes.patch b/ARM-RPi-PCIe-fixes.patch new file mode 100644 index 0000000..2700935 --- /dev/null +++ b/ARM-RPi-PCIe-fixes.patch @@ -0,0 +1,172 @@ +From 354971c474d8a595f3fc610942bf160ac9959343 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 11 Apr 2026 16:14:50 +0100 +Subject: [PATCH 1/2] pci: brcmstb: fix iBAR inbound window address for + pre-BCM2712 + +The reworked brcm_pcie_set_inbound_windows() writes bar_pci (the raw +PCI bus address) directly into the RC BAR config register, and relies +on the UBUS remap registers to supply the CPU-side translation. + +This model works on BCM2712 (RPi5), which has a capable UBUS/AXI +remap block. On BCM2711 (RPi4) the BAR config register expects the +address *offset* (bus_start - phys_start), not the raw bus address, +and the older UBUS remap registers cannot compensate for the +difference. The result is a misconfigured inbound DMA window that +renders the PCIe-attached XHCI USB controller non-functional. + +Fix by branching on the chip type inside brcm_pcie_set_inbound_windows(): + +- Pre-BCM2712: write the offset (bus_start - phys_start) into the BAR + config register, matching the behaviour of the code that was removed. + Skip the UBUS remap registers because the older hardware does not + need them for a single DMA region and setting them to an incorrect + value causes the regression. + +- BCM2712: keep the new behaviour unchanged (raw PCI address in BAR + config, CPU address in UBUS remap registers). + +Also restore the power-of-two size rounding that was present in the +original code (1ULL << fls64(size - 1)) for pre-BCM2712 paths, since +brcm_pcie_encode_ibar_size() is documented to require a power-of-two +input and the DT size value is not guaranteed to already be one. + +Signed-off-by: Peter Robinson +--- + drivers/pci/pcie_brcmstb.c | 58 +++++++++++++++++++++++++++++--------- + 1 file changed, 44 insertions(+), 14 deletions(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index bd1dd17e690..796c3b9ff9c 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -476,10 +476,22 @@ static u32 brcm_ubus_reg_offset(int bar) + return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4); + } + ++/* ++ * Round size up to the next power of two, as required by ++ * brcm_pcie_encode_ibar_size(). If size is already a power of two ++ * fls64(size - 1) still gives the correct result because the hardware ++ * encodes the exponent, not the raw value. ++ */ ++static u64 brcm_ibar_round_size(u64 size) ++{ ++ return 1ULL << fls64(size - 1); ++} ++ + static void brcm_pcie_set_inbound_windows(struct udevice *dev) + { + struct brcm_pcie *pcie = dev_get_priv(dev); + void __iomem *base = pcie->base; ++ bool is_2712 = (pcie->pcie_cfg->type == BCM2712); + int i, ibar_no, ret; + u32 tmp; + +@@ -504,20 +516,38 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) + bar_cpu = region.phys_start; + bar_size = region.size; + +- tmp = lower_32_bits(bar_pci); +- u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), +- RC_BAR2_CONFIG_LO_SIZE_MASK); +- writel(tmp, base + rc_bar_offset); +- writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); +- +- tmp = lower_32_bits(bar_cpu) & +- PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; +- tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; +- writel(tmp, base + ubus_bar_offset); +- +- tmp = upper_32_bits(bar_cpu) & +- PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; +- writel(tmp, base + ubus_bar_offset + 4); ++ if (is_2712) { ++ /* BCM2712: BAR holds raw PCI address; UBUS remap ++ * registers supply the CPU-side translation. */ ++ tmp = lower_32_bits(bar_pci); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); ++ ++ tmp = lower_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; ++ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; ++ writel(tmp, base + ubus_bar_offset); ++ ++ tmp = upper_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; ++ writel(tmp, base + ubus_bar_offset + 4); ++ } else { ++ /* Pre-BCM2712 (e.g. BCM2711 / RPi4): the BAR config ++ * register holds the offset (bus_start - phys_start), ++ * not the raw PCI address. The size must be rounded ++ * up to the next power of two before encoding. */ ++ u64 bar_offset = bar_pci - bar_cpu; ++ u64 bar_size_po2 = brcm_ibar_round_size(bar_size); ++ ++ tmp = lower_32_bits(bar_offset); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size_po2), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_offset), base + rc_bar_offset + 4); ++ /* UBUS remap registers are not used on pre-2712 hardware. */ ++ } + } + } + +-- +2.53.0 + +From d03a2f8be5519519cd1336295cb8627f6a685c07 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 11 Apr 2026 16:21:31 +0100 +Subject: [PATCH 2/2] pci: brcmstb: restore dynamic SCB0 size for pre-BCM2712 + +The reworked probe code hardcodes SCB0 size to 20 (32GB) for all chip +variants. On BCM2712 (RPi5) this is intentional. On BCM2711 (RPi4) +the original code derived the SCB0 size from the actual DMA region size +using ilog2(size) - 15, e.g. 1GB -> value 15 (0xf). Writing 20 +instead misconfigures the inbound memory window and is the remaining +cause of the USB regression after the BAR offset fix. + +Restore the dynamic calculation for pre-BCM2712 chips. + +Signed-off-by: Peter Robinson +--- + drivers/pci/pcie_brcmstb.c | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index 796c3b9ff9c..f0b0f1cc117 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -638,9 +638,22 @@ static int brcm_pcie_probe(struct udevice *dev) + MISC_CTRL_PCIE_RCB_MPS_MODE_MASK | + tmp); + +- /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); +- u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); ++ if (pcie->pcie_cfg->type == BCM2712) { ++ /* BCM2712: fixed 32GB SCB0 window */ ++ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); ++ } else { ++ /* Pre-BCM2712: size SCB0 to match the actual DMA region. ++ * rc_bar2_size must be a power of two; ilog2(size) - 15 ++ * gives the hardware encoding (e.g. 1GB -> 15). */ ++ struct pci_region region; ++ u64 rc_bar2_size; ++ ++ pci_get_dma_regions(dev, ®ion, 0); ++ rc_bar2_size = brcm_ibar_round_size(region.size); ++ u32p_replace_bits(&tmp, rc_bar2_size ? ilog2(rc_bar2_size) - 15 : 0xf, ++ MISC_CTRL_SCB0_SIZE_MASK); ++ } + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + if (pcie->pcie_cfg->type == BCM2712) { +-- +2.53.0 + diff --git a/raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch b/raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch new file mode 100644 index 0000000..d6612ee --- /dev/null +++ b/raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch @@ -0,0 +1,32 @@ +From 72fd4fdb54721a31d2b4e9f95fdd3b3e398bb2c0 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sun, 12 Apr 2026 01:14:12 +0100 +Subject: [PATCH] board/raspberrypi: Add quirk for RPi5 2Gb rev 1.0 + +All 2Gb Raspberry Pi 5s use the BCM2712D0 silicon, but +the early boards were still rev 1.0 so we need a quirk +to ensure the correct device tree is used. + +Signed-off-by: Peter Robinson +--- + board/raspberrypi/rpi/rpi.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index b0a1484c0fa..ff9cab6521b 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -371,6 +371,10 @@ static void set_fdtfile(void) + const char *fdtfile; + int rev = revision & 0x0f; + ++ /* 2GB Pi 5B board rev 1.0 always has BCM2712D0 silicon */ ++ if (revision == 0xb04170) ++ rev = 1; ++ + if (env_get("fdtfile")) + return; + +-- +2.53.0 + diff --git a/uboot-tools.spec b/uboot-tools.spec index 6f1d767..f39ee82 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.04 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -54,6 +54,8 @@ Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi Patch20: ARM-RPi5-Enable-PCIe.patch Patch21: 0001-Add-bcm2712-compat.patch +Patch22: ARM-RPi-PCIe-fixes.patch +Patch23: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch BuildRequires: bc BuildRequires: bison @@ -312,6 +314,10 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Sat Apr 11 2026 Peter Robinson - 1:2026.04-2 +- Fix PCIe/USB on Raspberry Pi 4 (rhbz#2448365) +- Fix detection of some revisions of RPi5 + * Tue Apr 07 2026 Peter Robinson - 1:2026.04-1 - Update to 2026.04 GA From 71d471982e84293ba078777b9294caffe9e15e3d Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 3 May 2026 09:27:45 +0100 Subject: [PATCH 25/38] 2026.07 RC1 --- ARM-RPi-PCIe-fixes.patch | 172 -- ARM-RPi5-Enable-PCIe.patch | 715 ++++---- ...TITION_INFO_PROTOCOL-support-for-MBR.patch | 1527 ----------------- ...ssing-inbound-DMA-offset-calculation.patch | 219 +++ rpi-enable-nvme.patch | 34 + sources | 2 +- uboot-tools.spec | 17 +- uefi-enable-https-boot-by-default.patch | 61 +- 8 files changed, 599 insertions(+), 2148 deletions(-) delete mode 100644 ARM-RPi-PCIe-fixes.patch delete mode 100644 efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch create mode 100644 nvme-Fix-missing-inbound-DMA-offset-calculation.patch create mode 100644 rpi-enable-nvme.patch diff --git a/ARM-RPi-PCIe-fixes.patch b/ARM-RPi-PCIe-fixes.patch deleted file mode 100644 index 2700935..0000000 --- a/ARM-RPi-PCIe-fixes.patch +++ /dev/null @@ -1,172 +0,0 @@ -From 354971c474d8a595f3fc610942bf160ac9959343 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sat, 11 Apr 2026 16:14:50 +0100 -Subject: [PATCH 1/2] pci: brcmstb: fix iBAR inbound window address for - pre-BCM2712 - -The reworked brcm_pcie_set_inbound_windows() writes bar_pci (the raw -PCI bus address) directly into the RC BAR config register, and relies -on the UBUS remap registers to supply the CPU-side translation. - -This model works on BCM2712 (RPi5), which has a capable UBUS/AXI -remap block. On BCM2711 (RPi4) the BAR config register expects the -address *offset* (bus_start - phys_start), not the raw bus address, -and the older UBUS remap registers cannot compensate for the -difference. The result is a misconfigured inbound DMA window that -renders the PCIe-attached XHCI USB controller non-functional. - -Fix by branching on the chip type inside brcm_pcie_set_inbound_windows(): - -- Pre-BCM2712: write the offset (bus_start - phys_start) into the BAR - config register, matching the behaviour of the code that was removed. - Skip the UBUS remap registers because the older hardware does not - need them for a single DMA region and setting them to an incorrect - value causes the regression. - -- BCM2712: keep the new behaviour unchanged (raw PCI address in BAR - config, CPU address in UBUS remap registers). - -Also restore the power-of-two size rounding that was present in the -original code (1ULL << fls64(size - 1)) for pre-BCM2712 paths, since -brcm_pcie_encode_ibar_size() is documented to require a power-of-two -input and the DT size value is not guaranteed to already be one. - -Signed-off-by: Peter Robinson ---- - drivers/pci/pcie_brcmstb.c | 58 +++++++++++++++++++++++++++++--------- - 1 file changed, 44 insertions(+), 14 deletions(-) - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index bd1dd17e690..796c3b9ff9c 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -476,10 +476,22 @@ static u32 brcm_ubus_reg_offset(int bar) - return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4); - } - -+/* -+ * Round size up to the next power of two, as required by -+ * brcm_pcie_encode_ibar_size(). If size is already a power of two -+ * fls64(size - 1) still gives the correct result because the hardware -+ * encodes the exponent, not the raw value. -+ */ -+static u64 brcm_ibar_round_size(u64 size) -+{ -+ return 1ULL << fls64(size - 1); -+} -+ - static void brcm_pcie_set_inbound_windows(struct udevice *dev) - { - struct brcm_pcie *pcie = dev_get_priv(dev); - void __iomem *base = pcie->base; -+ bool is_2712 = (pcie->pcie_cfg->type == BCM2712); - int i, ibar_no, ret; - u32 tmp; - -@@ -504,20 +516,38 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) - bar_cpu = region.phys_start; - bar_size = region.size; - -- tmp = lower_32_bits(bar_pci); -- u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), -- RC_BAR2_CONFIG_LO_SIZE_MASK); -- writel(tmp, base + rc_bar_offset); -- writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); -- -- tmp = lower_32_bits(bar_cpu) & -- PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; -- tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; -- writel(tmp, base + ubus_bar_offset); -- -- tmp = upper_32_bits(bar_cpu) & -- PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; -- writel(tmp, base + ubus_bar_offset + 4); -+ if (is_2712) { -+ /* BCM2712: BAR holds raw PCI address; UBUS remap -+ * registers supply the CPU-side translation. */ -+ tmp = lower_32_bits(bar_pci); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), -+ RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + rc_bar_offset); -+ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); -+ -+ tmp = lower_32_bits(bar_cpu) & -+ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; -+ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; -+ writel(tmp, base + ubus_bar_offset); -+ -+ tmp = upper_32_bits(bar_cpu) & -+ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; -+ writel(tmp, base + ubus_bar_offset + 4); -+ } else { -+ /* Pre-BCM2712 (e.g. BCM2711 / RPi4): the BAR config -+ * register holds the offset (bus_start - phys_start), -+ * not the raw PCI address. The size must be rounded -+ * up to the next power of two before encoding. */ -+ u64 bar_offset = bar_pci - bar_cpu; -+ u64 bar_size_po2 = brcm_ibar_round_size(bar_size); -+ -+ tmp = lower_32_bits(bar_offset); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size_po2), -+ RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + rc_bar_offset); -+ writel(upper_32_bits(bar_offset), base + rc_bar_offset + 4); -+ /* UBUS remap registers are not used on pre-2712 hardware. */ -+ } - } - } - --- -2.53.0 - -From d03a2f8be5519519cd1336295cb8627f6a685c07 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sat, 11 Apr 2026 16:21:31 +0100 -Subject: [PATCH 2/2] pci: brcmstb: restore dynamic SCB0 size for pre-BCM2712 - -The reworked probe code hardcodes SCB0 size to 20 (32GB) for all chip -variants. On BCM2712 (RPi5) this is intentional. On BCM2711 (RPi4) -the original code derived the SCB0 size from the actual DMA region size -using ilog2(size) - 15, e.g. 1GB -> value 15 (0xf). Writing 20 -instead misconfigures the inbound memory window and is the remaining -cause of the USB regression after the BAR offset fix. - -Restore the dynamic calculation for pre-BCM2712 chips. - -Signed-off-by: Peter Robinson ---- - drivers/pci/pcie_brcmstb.c | 17 +++++++++++++++-- - 1 file changed, 15 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 796c3b9ff9c..f0b0f1cc117 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -638,9 +638,22 @@ static int brcm_pcie_probe(struct udevice *dev) - MISC_CTRL_PCIE_RCB_MPS_MODE_MASK | - tmp); - -- /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ - tmp = readl(base + PCIE_MISC_MISC_CTRL); -- u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); -+ if (pcie->pcie_cfg->type == BCM2712) { -+ /* BCM2712: fixed 32GB SCB0 window */ -+ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); -+ } else { -+ /* Pre-BCM2712: size SCB0 to match the actual DMA region. -+ * rc_bar2_size must be a power of two; ilog2(size) - 15 -+ * gives the hardware encoding (e.g. 1GB -> 15). */ -+ struct pci_region region; -+ u64 rc_bar2_size; -+ -+ pci_get_dma_regions(dev, ®ion, 0); -+ rc_bar2_size = brcm_ibar_round_size(region.size); -+ u32p_replace_bits(&tmp, rc_bar2_size ? ilog2(rc_bar2_size) - 15 : 0xf, -+ MISC_CTRL_SCB0_SIZE_MASK); -+ } - writel(tmp, base + PCIE_MISC_MISC_CTRL); - - if (pcie->pcie_cfg->type == BCM2712) { --- -2.53.0 - diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch index 68a3274..f711dc4 100644 --- a/ARM-RPi5-Enable-PCIe.patch +++ b/ARM-RPi5-Enable-PCIe.patch @@ -1,52 +1,48 @@ -From patchwork Fri Feb 27 15:23:26 2026 +From patchwork Tue Apr 28 16:39:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202409 +X-Patchwork-Id: 2229734 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) + key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsY408lKz1xy2 - for ; Sat, 28 Feb 2026 02:23:35 +1100 (AEDT) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mTf0XgQz1yHv + for ; Wed, 29 Apr 2026 02:43:34 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 15CF383EB3; - Fri, 27 Feb 2026 16:23:33 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTP id BE23F84658; + Tue, 28 Apr 2026 18:43:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id CD42E83E8E; Fri, 27 Feb 2026 16:23:31 +0100 (CET) + id 65D5F845D8; Tue, 28 Apr 2026 18:39:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 2240A83CDF - for ; Fri, 27 Feb 2026 16:23:29 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id 81D7A842C7 + for ; Tue, 28 Apr 2026 18:39:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id EAEE468B05; Fri, 27 Feb 2026 16:23:26 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window + id C5D4268C4E; Tue, 28 Apr 2026 18:39:18 +0200 (CEST) +Subject: [PATCH v2 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -65,10 +61,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152326.EAEE468B05@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:26 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163918.C5D4268C4E@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:18 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -92,6 +92,8 @@ memory controller setup. Generously merging the PCIe address spaces works sufficiently well for a boot loader. Signed-off-by: Torsten Duwe +Co-authored-by: Oleksii Moisieiev +Tested-by: Pedro Falcato --- arch/arm/mach-bcm283x/init.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) @@ -125,55 +127,51 @@ index 7a1de22e0ae..7a2faaa4de6 100644 /* SoC bus */ .virt = 0x107c000000UL, -From patchwork Fri Feb 27 15:23:29 2026 +From patchwork Tue Apr 28 16:39:22 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202410 +X-Patchwork-Id: 2229735 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYB682xz1xy2 - for ; Sat, 28 Feb 2026 02:23:42 +1100 (AEDT) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mTn1JZ7z1yHv + for ; Wed, 29 Apr 2026 02:43:41 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 5E6F583E88; - Fri, 27 Feb 2026 16:23:34 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTP id 027E384669; + Tue, 28 Apr 2026 18:43:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id A94A183EE8; Fri, 27 Feb 2026 16:23:33 +0100 (CET) + id A0642845D8; Tue, 28 Apr 2026 18:39:29 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id CBDFA83E88 - for ; Fri, 27 Feb 2026 16:23:30 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id 3B7B4842C7 + for ; Tue, 28 Apr 2026 18:39:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 7C72C68BFE; Fri, 27 Feb 2026 16:23:29 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 2/9] pci: brcmstb: Fix PCIe bus numbers + id 977E668CFE; Tue, 28 Apr 2026 18:39:22 +0200 (CEST) +Subject: [PATCH v2 2/9] pci: brcmstb: Fix PCIe bus numbers To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -192,10 +190,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152329.7C72C68BFE@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:29 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163922.977E668CFE@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:22 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -225,6 +227,7 @@ subtracting the base bus number. Signed-off-by: Andrea della Porta Signed-off-by: Torsten Duwe +Tested-by: Pedro Falcato --- drivers/pci/pcie_brcmstb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) @@ -243,12 +246,13 @@ index f089c48f028..47c0802df23 100644 unsigned int pci_func = PCI_FUNC(bdf); int idx; -From patchwork Fri Feb 27 15:23:31 2026 +From patchwork Tue Apr 28 16:39:25 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202411 +X-Patchwork-Id: 2229737 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org @@ -261,37 +265,33 @@ Received: from phobos.denx.de (phobos.denx.de (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYM0tXtz1xy2 - for ; Sat, 28 Feb 2026 02:23:51 +1100 (AEDT) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mTx6XSTz1yHv + for ; Wed, 29 Apr 2026 02:43:49 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 98AF483E96; - Fri, 27 Feb 2026 16:23:36 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTP id 3A10E84674; + Tue, 28 Apr 2026 18:43:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id C1F7983EF9; Fri, 27 Feb 2026 16:23:34 +0100 (CET) + id 615EF845E3; Tue, 28 Apr 2026 18:39:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id AAFE683E76 - for ; Fri, 27 Feb 2026 16:23:32 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id C130184605 + for ; Tue, 28 Apr 2026 18:39:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 9A6CD68C7B; Fri, 27 Feb 2026 16:23:31 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 3/9] pci: brcmstb: Support different variants using a cfg + id 6DF1968D07; Tue, 28 Apr 2026 18:39:25 +0200 (CEST) +Subject: [PATCH v2 3/9] pci: brcmstb: Support different variants using a cfg struct To: Peter Robinson , Matthias Brugger @@ -311,10 +311,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152331.9A6CD68C7B@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:31 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163925.6DF1968D07@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:25 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -343,6 +347,8 @@ init bit must not remain set, albeit the reset control location is only corrected in patch#6 of this series. Signed-off-by: Torsten Duwe +Co-authored-by: Oleksii Moisieiev +Tested-by: Pedro Falcato --- .../mach-bcm283x/include/mach/acpi/bcm2711.h | 6 +- drivers/pci/pcie_brcmstb.c | 122 ++++++++++++++++-- @@ -583,54 +589,52 @@ index 47c0802df23..261f8790528 100644 }; -From patchwork Fri Feb 27 15:23:34 2026 +From patchwork Tue Apr 28 16:39:29 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202412 +X-Patchwork-Id: 2229738 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) + key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYX5WvXz1xy2 - for ; Sat, 28 Feb 2026 02:24:00 +1100 (AEDT) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mV66Q8Wz1yHv + for ; Wed, 29 Apr 2026 02:43:58 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id D5E9983F14; - Fri, 27 Feb 2026 16:23:38 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTP id 753C58467E; + Tue, 28 Apr 2026 18:43:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 30D3883F0A; Fri, 27 Feb 2026 16:23:37 +0100 (CET) + id 89B69845E3; Tue, 28 Apr 2026 18:39:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 2C96983E76 - for ; Fri, 27 Feb 2026 16:23:35 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id 860B3842D7 + for ; Tue, 28 Apr 2026 18:39:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 4A0BE68D07; Fri, 27 Feb 2026 16:23:34 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 4/9] pci: brcmstb: Add RPi5 reset facilities + id 3501268D0D; Tue, 28 Apr 2026 18:39:29 +0200 (CEST) +Subject: [PATCH v2 4/9] pci: brcmstb: Add RPi5 reset facilities To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -649,10 +653,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152334.4A0BE68D07@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:34 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163929.3501268D0D@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:29 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -675,6 +683,8 @@ A driver for Broadcom reset controllers ported from linux/drivers/reset/reset-brcmstb.c to U-Boot. Signed-off-by: Torsten Duwe +Co-authored-by: Oleksii Moisieiev +Tested-by: Pedro Falcato --- configs/rpi_arm64_defconfig | 1 + drivers/reset/Kconfig | 7 +++ @@ -696,7 +706,7 @@ index 69e8e72c5d7..153d7ed301e 100644 CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index 2fd91d6299c..46ffc103320 100644 +index 66911199c8b..e0561df8058 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -64,6 +64,13 @@ config RESET_BCM6345 @@ -714,7 +724,7 @@ index 2fd91d6299c..46ffc103320 100644 bool "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index ee5b009d134..ebf3d7425a4 100644 +index 088545c6473..ad5fe6b6184 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o @@ -829,54 +839,52 @@ index 00000000000..7861f7c9baf + .priv_auto = sizeof(struct brcmstb_reset), +}; -From patchwork Fri Feb 27 15:23:36 2026 +From patchwork Tue Apr 28 16:39:32 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202413 +X-Patchwork-Id: 2229739 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYk0pstz1xy2 - for ; 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Fri, 27 Feb 2026 16:23:37 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id B3DB9842D7 + for ; Tue, 28 Apr 2026 18:39:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id C7C2E68D0A; Fri, 27 Feb 2026 16:23:36 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 5/9] pci: brcmstb: Add RPi5 rescal reset facilities + id 5540868D0F; Tue, 28 Apr 2026 18:39:32 +0200 (CEST) +Subject: [PATCH v2 5/9] pci: brcmstb: Add RPi5 rescal reset facilities To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -895,10 +903,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152336.C7C2E68D0A@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:36 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163932.5540868D0F@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:32 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -921,6 +933,8 @@ A driver for Broadcom rescal reset controllers ported from linux/drivers/reset/reset-brcmstb-rescal.c to U-Boot. Signed-off-by: Torsten Duwe +Co-authored-by: Oleksii Moisieiev +Tested-by: Pedro Falcato --- configs/rpi_arm64_defconfig | 1 + drivers/reset/Kconfig | 7 ++ @@ -942,7 +956,7 @@ index 153d7ed301e..38af5029403 100644 CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index 46ffc103320..b7d2d4b18d5 100644 +index e0561df8058..b4237bf98bf 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -71,6 +71,13 @@ config RESET_BRCMSTB @@ -960,7 +974,7 @@ index 46ffc103320..b7d2d4b18d5 100644 bool "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index ebf3d7425a4..c7a9da3268d 100644 +index ad5fe6b6184..c369bdb3d6c 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o @@ -1081,55 +1095,51 @@ index 00000000000..fc8fcfa8b3f + .priv_auto = sizeof(struct brcm_rescal_reset), +}; -From patchwork Fri Feb 27 15:23:41 2026 +From patchwork Tue Apr 28 16:39:36 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202414 +X-Patchwork-Id: 2229740 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsYt68Kqz1xy2 - for ; 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Fri, 27 Feb 2026 16:23:42 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id 2F86E845E3 + for ; Tue, 28 Apr 2026 18:39:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 3B6C468D13; Fri, 27 Feb 2026 16:23:41 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 6/9] pci: brcmstb: Get and use bridge and rescal reset + id 7987968D09; Tue, 28 Apr 2026 18:39:36 +0200 (CEST) +Subject: [PATCH v2 6/9] pci: brcmstb: Get and use bridge and rescal reset properties To: Peter Robinson , Matthias Brugger @@ -1149,10 +1159,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152341.3B6C468D13@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:41 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163936.7987968D09@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:36 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1175,6 +1189,8 @@ Check whether the device tree has nodes for the two reset controls and use them if so. Signed-off-by: Torsten Duwe +Co-authored-by: Oleksii Moisieiev +Tested-by: Pedro Falcato --- drivers/pci/pcie_brcmstb.c | 51 +++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) @@ -1284,12 +1300,13 @@ index 261f8790528..1f97cda5cc7 100644 }; -From patchwork Fri Feb 27 15:23:44 2026 +From patchwork Tue Apr 28 16:39:40 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202415 +X-Patchwork-Id: 2229741 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org @@ -1300,39 +1317,35 @@ Authentication-Results: legolas.ozlabs.org; Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) + key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsZ44DGBz1xy2 - for ; Sat, 28 Feb 2026 02:24:28 +1100 (AEDT) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mVg1Q52z1yHv + for ; Wed, 29 Apr 2026 02:44:27 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id ABFF483E76; - Fri, 27 Feb 2026 16:23:47 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTP id 25FEE84692; + Tue, 28 Apr 2026 18:43:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 50B0483F4C; Fri, 27 Feb 2026 16:23:47 +0100 (CET) + id 47298845E3; Tue, 28 Apr 2026 18:39:44 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 7317F83F2A - for ; Fri, 27 Feb 2026 16:23:45 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id 7774B84612 + for ; Tue, 28 Apr 2026 18:39:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 3E13168D0D; Fri, 27 Feb 2026 16:23:44 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 7/9] pci: brcmstb: Fix iBAR size calculation + id CE7CB68D0A; Tue, 28 Apr 2026 18:39:40 +0200 (CEST) +Subject: [PATCH v2 7/9] pci: brcmstb: Fix iBAR size calculation To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1351,10 +1364,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152344.3E13168D0D@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:44 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163940.CE7CB68D0A@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:40 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1376,6 +1393,7 @@ From: Torsten Duwe Fix inbound window size calculation, like Linux commit 25a98c7270156. Signed-off-by: Torsten Duwe +Tested-by: Pedro Falcato --- drivers/pci/pcie_brcmstb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) @@ -1396,54 +1414,52 @@ index 1f97cda5cc7..8a25fb04563 100644 /* Something is awry so disable */ -From patchwork Fri Feb 27 15:23:48 2026 +From patchwork Tue Apr 28 16:39:46 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202416 +X-Patchwork-Id: 2229742 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsZG0Fbrz1xy2 - for ; Sat, 28 Feb 2026 02:24:38 +1100 (AEDT) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mVr1fFhz1yHv + for ; Wed, 29 Apr 2026 02:44:36 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id E5B4883F4D; - Fri, 27 Feb 2026 16:23:52 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTP id 5B6528469E; + Tue, 28 Apr 2026 18:43:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id D7A5283F4D; Fri, 27 Feb 2026 16:23:51 +0100 (CET) + id 0F3038464E; Tue, 28 Apr 2026 18:39:50 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id E27D683F2A - for ; Fri, 27 Feb 2026 16:23:49 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id F29FE8460E + for ; Tue, 28 Apr 2026 18:39:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id BFF2568BFE; Fri, 27 Feb 2026 16:23:48 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 8/9] pci: brcmstb: rework iBAR handling + id 42D4368D12; Tue, 28 Apr 2026 18:39:46 +0200 (CEST) +Subject: [PATCH v2 8/9] pci: brcmstb: rework iBAR handling To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1462,10 +1478,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152348.BFF2568BFE@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:48 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163946.42D4368D12@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:46 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1493,12 +1513,13 @@ and sets the BARs from it later, while U-Boot does it all on the fly, in one go, so the code is not 1:1 comparable. Signed-off-by: Torsten Duwe +Tested-by: Pedro Falcato --- - drivers/pci/pcie_brcmstb.c | 107 ++++++++++++++++++++++++++++++------- - 1 file changed, 88 insertions(+), 19 deletions(-) + drivers/pci/pcie_brcmstb.c | 150 ++++++++++++++++++++++++++++++++----- + 1 file changed, 131 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 8a25fb04563..e5c848c9e8e 100644 +index 8a25fb04563..05b80a45b50 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -50,6 +50,29 @@ @@ -1531,7 +1552,7 @@ index 8a25fb04563..e5c848c9e8e 100644 enum { RGR1_SW_INIT_1, EXT_CFG_INDEX, -@@ -437,17 +460,75 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, +@@ -437,17 +460,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); } @@ -1551,10 +1572,22 @@ index 8a25fb04563..e5c848c9e8e 100644 + return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4); +} + ++/* ++ * Round size up to the next power of two, as required by ++ * brcm_pcie_encode_ibar_size(). If size is already a power of two ++ * fls64(size - 1) still gives the correct result because the hardware ++ * encodes the exponent, not the raw value. ++ */ ++static u64 brcm_ibar_round_size(u64 size) ++{ ++ return 1ULL << fls64(size - 1); ++} ++ +static void brcm_pcie_set_inbound_windows(struct udevice *dev) +{ + struct brcm_pcie *pcie = dev_get_priv(dev); + void __iomem *base = pcie->base; ++ bool is_2712 = (pcie->pcie_cfg->type == BCM2712); + int i, ibar_no, ret; + u32 tmp; + @@ -1579,20 +1612,38 @@ index 8a25fb04563..e5c848c9e8e 100644 + bar_cpu = region.phys_start; + bar_size = region.size; + -+ tmp = lower_32_bits(bar_pci); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), -+ RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + rc_bar_offset); -+ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); ++ if (is_2712) { ++ /* BCM2712: BAR holds raw PCI address; UBUS remap ++ * registers supply the CPU-side translation. */ ++ tmp = lower_32_bits(bar_pci); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); + -+ tmp = lower_32_bits(bar_cpu) & -+ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; -+ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; -+ writel(tmp, base + ubus_bar_offset); ++ tmp = lower_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; ++ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; ++ writel(tmp, base + ubus_bar_offset); + -+ tmp = upper_32_bits(bar_cpu) & -+ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; -+ writel(tmp, base + ubus_bar_offset + 4); ++ tmp = upper_32_bits(bar_cpu) & ++ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; ++ writel(tmp, base + ubus_bar_offset + 4); ++ } else { ++ /* Pre-BCM2712 (e.g. BCM2711 / RPi4): the BAR config ++ * register holds the offset (bus_start - phys_start), ++ * not the raw PCI address. The size must be rounded ++ * up to the next power of two before encoding. */ ++ u64 bar_offset = bar_pci - bar_cpu; ++ u64 bar_size_po2 = brcm_ibar_round_size(bar_size); ++ ++ tmp = lower_32_bits(bar_offset); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size_po2), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + rc_bar_offset); ++ writel(upper_32_bits(bar_offset), base + rc_bar_offset + 4); ++ /* UBUS remap registers are not used on pre-2712 hardware. */ ++ } + } +} + @@ -1610,7 +1661,7 @@ index 8a25fb04563..e5c848c9e8e 100644 int i, ret; u16 nlw, cls, lnksta; u32 tmp; -@@ -488,23 +569,9 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -488,23 +599,22 @@ static int brcm_pcie_probe(struct udevice *dev) MISC_CTRL_CFG_READ_UR_MODE_MASK | MISC_CTRL_MAX_BURST_SIZE_128); @@ -1628,15 +1679,28 @@ index 8a25fb04563..e5c848c9e8e 100644 - scb_size_val = rc_bar2_size ? - ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ - -+ /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ tmp = readl(base + PCIE_MISC_MISC_CTRL); - u32p_replace_bits(&tmp, scb_size_val, - MISC_CTRL_SCB0_SIZE_MASK); -+ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); ++ if (pcie->pcie_cfg->type == BCM2712) { ++ /* BCM2712: fixed 32GB SCB0 window */ ++ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); ++ } else { ++ /* Pre-BCM2712: size SCB0 to match the actual DMA region. ++ * rc_bar2_size must be a power of two; ilog2(size) - 15 ++ * gives the hardware encoding (e.g. 1GB -> 15). */ ++ struct pci_region region; ++ u64 rc_bar2_size; ++ ++ pci_get_dma_regions(dev, ®ion, 0); ++ rc_bar2_size = brcm_ibar_round_size(region.size); ++ u32p_replace_bits(&tmp, rc_bar2_size ? ilog2(rc_bar2_size) - 15 : 0xf, ++ MISC_CTRL_SCB0_SIZE_MASK); ++ } writel(tmp, base + PCIE_MISC_MISC_CTRL); /* Disable the PCIe->GISB memory window (RC_BAR1) */ -@@ -521,6 +588,8 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -521,6 +631,8 @@ static int brcm_pcie_probe(struct udevice *dev) /* Clear any interrupts we find on boot */ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); @@ -1646,12 +1710,13 @@ index 8a25fb04563..e5c848c9e8e 100644 brcm_pcie_set_gen(pcie, pcie->gen); -From patchwork Fri Feb 27 15:23:52 2026 +From patchwork Tue Apr 28 16:39:50 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2202417 +X-Patchwork-Id: 2229743 +X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org @@ -1663,37 +1728,33 @@ Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4fMsZR5GzHz1xy2 - for ; Sat, 28 Feb 2026 02:24:47 +1100 (AEDT) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mW16n64z1yHv + for ; Wed, 29 Apr 2026 02:44:45 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 2D46783EDF; - Fri, 27 Feb 2026 16:23:57 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTP id 8FC1D846A2; + Tue, 28 Apr 2026 18:43:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 5671E83F63; Fri, 27 Feb 2026 16:23:56 +0100 (CET) + id 3186A84656; Tue, 28 Apr 2026 18:39:54 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, - RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, + RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 300CA83F56 - for ; Fri, 27 Feb 2026 16:23:54 +0100 (CET) + by phobos.denx.de (Postfix) with ESMTPS id 3CC6284612 + for ; Tue, 28 Apr 2026 18:39:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id F152968D16; Fri, 27 Feb 2026 16:23:52 +0100 (CET) -In-Reply-To: <20260227152046.42DE068B05@verein.lst.de> -References: <20260227152046.42DE068B05@verein.lst.de> -From: Torsten Duwe -Subject: [PATCH 9/9] pci: brcmstb: Adapt to AXI bridge + id 9BB2668D09; Tue, 28 Apr 2026 18:39:50 +0200 (CEST) +Subject: [PATCH v2 9/9] pci: brcmstb: Adapt to AXI bridge To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1712,10 +1773,14 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_u-boot?= - =?unknown-8bit?q?=40lists=2Edenx=2Ede?= -Message-Id: <20260227152352.F152968D16@verein.lst.de> -Date: Fri, 27 Feb 2026 16:23:52 +0100 (CET) + =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= + =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= + =?unknown-8bit?q?=2Ede?= +In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> +Message-Id: <20260428163950.9BB2668D09@verein.lst.de> +Date: Tue, 28 Apr 2026 18:39:50 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1740,6 +1805,8 @@ bridge and clocked with 54MHz. Some are from kernel commit branch. All reworked for the simpler setup code in U-Boot. Signed-off-by: Torsten Duwe +Co-authored-by: Oleksii Moisieiev +Tested-by: Pedro Falcato --- .../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 + drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++- @@ -1758,10 +1825,10 @@ index 6eb5389b858..869482eaffe 100644 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index e5c848c9e8e..bd1dd17e690 100644 +index 05b80a45b50..f0b0f1cc117 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c -@@ -521,6 +521,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) +@@ -551,6 +551,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) } } @@ -1792,7 +1859,7 @@ index e5c848c9e8e..bd1dd17e690 100644 static int brcm_pcie_probe(struct udevice *dev) { struct udevice *ctlr = pci_get_controller(dev); -@@ -562,18 +586,56 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -592,12 +616,27 @@ static int brcm_pcie_probe(struct udevice *dev) /* Wait for SerDes to be stable */ udelay(100); @@ -1819,9 +1886,10 @@ index e5c848c9e8e..bd1dd17e690 100644 + MISC_CTRL_PCIE_RCB_MPS_MODE_MASK | + tmp); - /* Enable 32GB memory to be accessed from PCIe in the SCB0 */ tmp = readl(base + PCIE_MISC_MISC_CTRL); - u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); + if (pcie->pcie_cfg->type == BCM2712) { +@@ -617,6 +656,29 @@ static int brcm_pcie_probe(struct udevice *dev) + } writel(tmp, base + PCIE_MISC_MISC_CTRL); + if (pcie->pcie_cfg->type == BCM2712) { @@ -1850,178 +1918,3 @@ index e5c848c9e8e..bd1dd17e690 100644 /* Disable the PCIe->GISB memory window (RC_BAR1) */ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, RC_BAR1_CONFIG_LO_SIZE_MASK); -From 9e0fc68de1424b3db495f8a661d578435c4137c1 Mon Sep 17 00:00:00 2001 -From: Torsten Duwe -Date: Mon, 2 Mar 2026 13:59:40 +0100 -Subject: [PATCH] Fix NVMe for non-zero bus offsets - -Hi all, - -working on the RPi5 I found that the U-Boot NVMe code is lacking a significant -feature. The NVMe protocol heavily relies on device access into main memory, -in the medieval times of computing this was called "bus master DMA". The NVMe -device must generate memory addresses and read or write contents there. The -current U-Boot code does in no way account for PCIe bridges in the path that -add an offset to such "inbound accesses". Consequently, U-Boot can only boot -from NVMe on platforms where this address offset is zero. -(These are surprisingly many!) - -This proposed patch uses the already existent dev_phys_to_bus(), which can -dig up the correct offset from associated DT nodes and subtract it. I have -no strong opinion on the macro naming, and whether it should silently pull -in the "dev" from the outer scope or have it better passed explicitly. - -Signed-off-by: Torsten Duwe ---- - drivers/nvme/nvme.c | 29 ++++++++++++++++------------- - 1 file changed, 16 insertions(+), 13 deletions(-) - -diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c -index 2b14437f69c..039fbe0bc75 100644 ---- a/drivers/nvme/nvme.c -+++ b/drivers/nvme/nvme.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -27,6 +28,8 @@ - #define IO_TIMEOUT 30 - #define MAX_PRP_POOL 512 - -+#define BUS_ADDR(a) dev_phys_to_bus(dev->udev, (a)) -+ - static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) - { - int timeout; -@@ -91,12 +94,12 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, - i = 0; - while (nprps) { - if ((i == (prps_per_page - 1)) && nprps > 1) { -- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + -- page_size); -+ *(prp_pool + i) = cpu_to_le64(BUS_ADDR((ulong)prp_pool + -+ page_size)); - i = 0; - prp_pool += page_size; - } -- *(prp_pool + i++) = cpu_to_le64(dma_addr); -+ *(prp_pool + i++) = cpu_to_le64(BUS_ADDR(dma_addr)); - dma_addr += page_size; - nprps--; - } -@@ -393,8 +396,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) - dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; - - writel(aqa, &dev->bar->aqa); -- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); -- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); -+ nvme_writeq(BUS_ADDR((ulong)nvmeq->sq_cmds), &dev->bar->asq); -+ nvme_writeq(BUS_ADDR((ulong)nvmeq->cqes), &dev->bar->acq); - - result = nvme_enable_ctrl(dev); - if (result) -@@ -420,7 +423,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, - - memset(&c, 0, sizeof(c)); - c.create_cq.opcode = nvme_admin_create_cq; -- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); -+ c.create_cq.prp1 = cpu_to_le64(BUS_ADDR((ulong)nvmeq->cqes)); - c.create_cq.cqid = cpu_to_le16(qid); - c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); - c.create_cq.cq_flags = cpu_to_le16(flags); -@@ -437,7 +440,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, - - memset(&c, 0, sizeof(c)); - c.create_sq.opcode = nvme_admin_create_sq; -- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); -+ c.create_sq.prp1 = cpu_to_le64(BUS_ADDR((ulong)nvmeq->sq_cmds)); - c.create_sq.sqid = cpu_to_le16(qid); - c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); - c.create_sq.sq_flags = cpu_to_le16(flags); -@@ -458,14 +461,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, - memset(&c, 0, sizeof(c)); - c.identify.opcode = nvme_admin_identify; - c.identify.nsid = cpu_to_le32(nsid); -- c.identify.prp1 = cpu_to_le64(dma_addr); -+ c.identify.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); - - length -= (page_size - offset); - if (length <= 0) { - c.identify.prp2 = 0; - } else { - dma_addr += (page_size - offset); -- c.identify.prp2 = cpu_to_le64(dma_addr); -+ c.identify.prp2 = cpu_to_le64(BUS_ADDR(dma_addr)); - } - - c.identify.cns = cpu_to_le32(cns); -@@ -490,7 +493,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, - memset(&c, 0, sizeof(c)); - c.features.opcode = nvme_admin_get_features; - c.features.nsid = cpu_to_le32(nsid); -- c.features.prp1 = cpu_to_le64(dma_addr); -+ c.features.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); - c.features.fid = cpu_to_le32(fid); - - ret = nvme_submit_admin_cmd(dev, &c, result); -@@ -516,7 +519,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, - - memset(&c, 0, sizeof(c)); - c.features.opcode = nvme_admin_set_features; -- c.features.prp1 = cpu_to_le64(dma_addr); -+ c.features.prp1 = cpu_to_le64(BUS_ADDR(dma_addr)); - c.features.fid = cpu_to_le32(fid); - c.features.dword11 = cpu_to_le32(dword11); - -@@ -785,8 +788,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, - c.rw.slba = cpu_to_le64(slba); - slba += lbas; - c.rw.length = cpu_to_le16(lbas - 1); -- c.rw.prp1 = cpu_to_le64(temp_buffer); -- c.rw.prp2 = cpu_to_le64(prp2); -+ c.rw.prp1 = cpu_to_le64(BUS_ADDR(temp_buffer)); -+ c.rw.prp2 = cpu_to_le64(BUS_ADDR(prp2)); - status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], - &c, NULL, IO_TIMEOUT); - if (status) --- -2.53.0 - -From 253adf9d1bbf0a166f63b30f6ce38cac69239a34 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sun, 29 Mar 2026 20:28:41 +0100 -Subject: [PATCH] rpi: enable nvme - -Signed-off-by: Peter Robinson ---- - configs/rpi_arm64_defconfig | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 38af5029403..ed4ae6ff522 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -15,7 +15,7 @@ CONFIG_BOOTSTD_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_FDT_SIMPLEFB=y - CONFIG_USE_PREBOOT=y --CONFIG_PREBOOT="pci enum; usb start;" -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_SYS_PBSIZE=1049 - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -41,6 +41,7 @@ CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_MMC_SDHCI_BCMSTB=y - CONFIG_BCMGENET=y -+CONFIG_NVME_PCI=y - CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set --- -2.53.0 - diff --git a/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch b/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch deleted file mode 100644 index f48690e..0000000 --- a/efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch +++ /dev/null @@ -1,1527 +0,0 @@ -From patchwork Thu Feb 12 20:44:55 2026 -Content-Type: text/plain; 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[62.151.111.63]) - by smtp.gmail.com with ESMTPSA id - ffacd0b85a97d-43796ac82f7sm466079f8f.28.2026.02.12.12.45.15 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Thu, 12 Feb 2026 12:45:15 -0800 (PST) -From: Javier Martinez Canillas -To: u-boot@lists.denx.de -Cc: Heinrich Schuchardt , eballetb@redhat.com, - Ilias Apalodimas , - Tom Rini , - Javier Martinez Canillas -Subject: [PATCH v2 1/7] disk: part_dos: Move header to the main include - directory -Date: Thu, 12 Feb 2026 21:44:55 +0100 -Message-ID: <20260212204511.619392-2-javierm@redhat.com> -X-Mailer: git-send-email 2.53.0 -In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> -References: <20260212204511.619392-1-javierm@redhat.com> -MIME-Version: 1.0 -X-Mimecast-Spam-Score: 0 -X-Mimecast-MFC-PROC-ID: IPRNvMIm13yQ-FtMhxNzZkK7Dpa5P_eKViUiJ6XWg7c_1770929117 -X-Mimecast-Originator: redhat.com -content-type: text/plain; charset="US-ASCII"; x-default=true -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -There are two different struct definitions for MBR partition table -entries: one in part_dos.h and a nearly identical one in part_efi.h. - -To enable future consolidation of these two structures, move part_dos.h -to the main include directory. This makes it accessible from other parts -of the codebase, such as part_efi.h, and is the first step toward removing -the redundant definition. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Tom Rini -Reviewed-by: Ilias Apalodimas ---- - -(no changes since v1) - - disk/part_dos.c | 2 +- - {disk => include}/part_dos.h | 0 - 2 files changed, 1 insertion(+), 1 deletion(-) - rename {disk => include}/part_dos.h (100%) - -diff --git a/disk/part_dos.c b/disk/part_dos.c -index 18dd35c9b98e..2545cc6bf5d2 100644 ---- a/disk/part_dos.c -+++ b/disk/part_dos.c -@@ -19,7 +19,7 @@ - #include - #include - #include --#include "part_dos.h" -+#include - #include - - #define DOS_PART_DEFAULT_SECTOR 512 -diff --git a/disk/part_dos.h b/include/part_dos.h -similarity index 100% -rename from disk/part_dos.h -rename to include/part_dos.h - -From patchwork Thu Feb 12 20:44:56 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Javier Martinez Canillas -X-Patchwork-Id: 2196075 -X-Patchwork-Delegate: xypron.glpk@gmx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) - by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-48371a298ebsm1026155e9.13.2026.02.12.12.45.17 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Thu, 12 Feb 2026 12:45:17 -0800 (PST) -From: Javier Martinez Canillas -To: u-boot@lists.denx.de -Cc: Heinrich Schuchardt , eballetb@redhat.com, - Ilias Apalodimas , - Tom Rini , - Javier Martinez Canillas -Subject: [PATCH v2 2/7] disk: part_dos: Align dos_partition_t with struct - partition -Date: Thu, 12 Feb 2026 21:44:56 +0100 -Message-ID: <20260212204511.619392-3-javierm@redhat.com> -X-Mailer: git-send-email 2.53.0 -In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> -References: <20260212204511.619392-1-javierm@redhat.com> -MIME-Version: 1.0 -X-Mimecast-Spam-Score: 0 -X-Mimecast-MFC-PROC-ID: fPt7jBSAujrv4TDFANb7Za8r3XesZKgoNdRV6-QyxLM_1770929120 -X-Mimecast-Originator: redhat.com -content-type: text/plain; charset="US-ASCII"; x-default=true -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -The dos_partition_t struct defined in part_dos.h is nearly identical to -the struct partition defined in part_efi.h. They differ primarily in how -define their starting sector and number of sectors fields. - -The former uses unsigned char arrays while the latter uses __le32 types. -Using __le32 is preferable, as it removes the ambiguity and potential -misuse of a raw byte array. This also aligns the structure with how the -Linux kernel defines it nowadays, which is the original source of it. - -To prepare for future consolidation where one of the data structures can -be removed, this change aligns both definitions and updates all accessors -for dos_partition_t. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Tom Rini -Reviewed-by: Ilias Apalodimas ---- - -(no changes since v1) - - disk/part_dos.c | 16 ++++++++-------- - include/part_dos.h | 6 +++--- - 2 files changed, 11 insertions(+), 11 deletions(-) - -diff --git a/disk/part_dos.c b/disk/part_dos.c -index 2545cc6bf5d2..60c3d6773696 100644 ---- a/disk/part_dos.c -+++ b/disk/part_dos.c -@@ -49,8 +49,8 @@ static int get_bootable(dos_partition_t *p) - static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector, - int part_num, unsigned int disksig) - { -- lbaint_t lba_start = ext_part_sector + get_unaligned_le32(p->start4); -- lbaint_t lba_size = get_unaligned_le32(p->size4); -+ lbaint_t lba_start = ext_part_sector + get_unaligned_le32(&p->start_sect); -+ lbaint_t lba_size = get_unaligned_le32(&p->nr_sects); - - printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength - "u\t%08x-%02x\t%02x%s%s\n", -@@ -185,7 +185,7 @@ static void print_partition_extended(struct blk_desc *desc, - for (i = 0; i < 4; i++, pt++) { - if (is_extended (pt->sys_ind)) { - lbaint_t lba_start -- = get_unaligned_le32 (pt->start4) + relative; -+ = get_unaligned_le32 (&pt->start_sect) + relative; - - print_partition_extended(desc, lba_start, - !ext_part_sector ? lba_start : -@@ -252,8 +252,8 @@ static int part_get_info_extended(struct blk_desc *desc, - else - info->blksz = DOS_PART_DEFAULT_SECTOR; - info->start = (lbaint_t)(ext_part_sector + -- get_unaligned_le32(pt->start4)); -- info->size = (lbaint_t)get_unaligned_le32(pt->size4); -+ get_unaligned_le32(&pt->start_sect)); -+ info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); - part_set_generic_name(desc, part_num, - (char *)info->name); - /* sprintf(info->type, "%d, pt->sys_ind); */ -@@ -281,7 +281,7 @@ static int part_get_info_extended(struct blk_desc *desc, - for (i = 0; i < 4; i++, pt++) { - if (is_extended (pt->sys_ind)) { - lbaint_t lba_start -- = get_unaligned_le32 (pt->start4) + relative; -+ = get_unaligned_le32 (&pt->start_sect) + relative; - - return part_get_info_extended(desc, lba_start, - ext_part_sector == 0 ? lba_start : relative, -@@ -356,8 +356,8 @@ static void mbr_fill_pt_entry(dos_partition_t *pt, lbaint_t start, - pt->sys_ind = sys_ind; - lba_to_chs(start, &pt->cyl, &pt->head, &pt->sector); - lba_to_chs(start + size - 1, &pt->end_cyl, &pt->end_head, &pt->end_sector); -- put_unaligned_le32(relative, &pt->start4); -- put_unaligned_le32(size, &pt->size4); -+ put_unaligned_le32(relative, &pt->start_sect); -+ put_unaligned_le32(size, &pt->nr_sects); - } - - int write_mbr_partitions(struct blk_desc *dev, -diff --git a/include/part_dos.h b/include/part_dos.h -index 505582242281..92956d530637 100644 ---- a/include/part_dos.h -+++ b/include/part_dos.h -@@ -30,8 +30,8 @@ typedef struct dos_partition { - unsigned char end_head; /* end head */ - unsigned char end_sector; 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[62.151.111.63]) - by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-48370a3ecadsm3205185e9.3.2026.02.12.12.45.19 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Thu, 12 Feb 2026 12:45:20 -0800 (PST) -From: Javier Martinez Canillas -To: u-boot@lists.denx.de -Cc: Heinrich Schuchardt , eballetb@redhat.com, - Ilias Apalodimas , - Tom Rini , - Javier Martinez Canillas -Subject: [PATCH v2 3/7] disk: part_efi: Remove redundant struct partition - definition -Date: Thu, 12 Feb 2026 21:44:57 +0100 -Message-ID: <20260212204511.619392-4-javierm@redhat.com> -X-Mailer: git-send-email 2.53.0 -In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> -References: <20260212204511.619392-1-javierm@redhat.com> -MIME-Version: 1.0 -X-Mimecast-Spam-Score: 0 -X-Mimecast-MFC-PROC-ID: waoFTyp5Nb4lUw3OUZ2FyujC5g1lrXxsAubBNTuInkI_1770929122 -X-Mimecast-Originator: redhat.com -content-type: text/plain; charset="US-ASCII"; x-default=true -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -Now that dos_partition_t and struct partition are identical, the duplicated -data structure definition in the part_efi.h header can just be removed. - -This results in a single, shared definition for MBR partition table -entries, instead of having the same definition in two different places. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Tom Rini -Reviewed-by: Ilias Apalodimas ---- - -(no changes since v1) - - disk/part_efi.c | 4 ++-- - include/part_efi.h | 19 +++---------------- - 2 files changed, 5 insertions(+), 18 deletions(-) - -diff --git a/disk/part_efi.c b/disk/part_efi.c -index fb1ed534f861..d8b17ec2e91a 100644 ---- a/disk/part_efi.c -+++ b/disk/part_efi.c -@@ -51,7 +51,7 @@ static inline u32 efi_crc32(const void *buf, u32 len) - * Private function prototypes - */ - --static int pmbr_part_valid(struct partition *part); -+static int pmbr_part_valid(dos_partition_t *part); - static int is_pmbr_valid(legacy_mbr * mbr); - static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head, - gpt_entry **pgpt_pte); -@@ -990,7 +990,7 @@ int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf) - * - * Returns: 1 if EFI GPT partition type is found. - */ --static int pmbr_part_valid(struct partition *part) -+static int pmbr_part_valid(dos_partition_t *part) - { - if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && - get_unaligned_le32(&part->start_sect) == 1UL) { -diff --git a/include/part_efi.h b/include/part_efi.h -index fb402df6f13e..2cea50880465 100644 ---- a/include/part_efi.h -+++ b/include/part_efi.h -@@ -18,6 +18,7 @@ - #define _DISK_PART_EFI_H - - #include -+#include - - #define MSDOS_MBR_SIGNATURE 0xAA55 - #define MSDOS_MBR_BOOT_CODE_SIZE 440 -@@ -77,20 +78,6 @@ - /* linux/include/efi.h */ - typedef u16 efi_char16_t; - --/* based on linux/include/genhd.h */ --struct partition { -- u8 boot_ind; /* 0x80 - active */ -- u8 head; /* starting head */ -- u8 sector; /* starting sector */ -- u8 cyl; /* starting cylinder */ -- u8 sys_ind; /* What partition type */ -- u8 end_head; /* end head */ -- u8 end_sector; /* end sector */ -- u8 end_cyl; /* end cylinder */ -- __le32 start_sect; /* starting sector counting from 0 */ -- __le32 nr_sects; /* nr of sectors in partition */ --} __packed; -- - /* based on linux/fs/partitions/efi.h */ - typedef struct _gpt_header { - __le64 signature; -@@ -134,7 +121,7 @@ typedef struct _legacy_mbr { - u8 boot_code[MSDOS_MBR_BOOT_CODE_SIZE]; - __le32 unique_mbr_signature; - __le16 unknown; -- struct partition partition_record[4]; -+ dos_partition_t partition_record[4]; - __le16 signature; - } __packed legacy_mbr; - -@@ -153,7 +140,7 @@ struct efi_partition_info { - u8 system; - u8 reserved[7]; - union { -- struct partition mbr; -+ dos_partition_t mbr; - gpt_entry gpt; - } info; - } __packed; - -From patchwork Thu Feb 12 20:44:58 2026 -Content-Type: text/plain; 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- } - --/* Print a partition that is relative to its Extended partition table -+/** -+ * part_get_info_extended() - get partition info for a DOS partition -+ * -+ * @desc: Block device descriptor -+ * @ext_part_sector: Partition table sector -+ * @relative: Relative offset for the partition -+ * @part_num: Current partition number -+ * @which_part: Target partition number -+ * @info: Returns a pointer to the partition info -+ * @disksig: Disk signature -+ * -+ * Return: 0 on success, negative on error - */ - static int part_get_info_extended(struct blk_desc *desc, - lbaint_t ext_part_sector, lbaint_t relative, - -From patchwork Thu Feb 12 20:44:59 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Javier Martinez Canillas -X-Patchwork-Id: 2196079 -X-Patchwork-Delegate: xypron.glpk@gmx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; 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[62.151.111.63]) - by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-4835dcfaae1sm112461635e9.10.2026.02.12.12.45.24 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Thu, 12 Feb 2026 12:45:24 -0800 (PST) -From: Javier Martinez Canillas -To: u-boot@lists.denx.de -Cc: Heinrich Schuchardt , eballetb@redhat.com, - Ilias Apalodimas , - Tom Rini , - Javier Martinez Canillas , - Casey Connolly , - Jan Kiszka , Javier Tia , - Rasmus Villemoes , - Varadarajan Narayanan -Subject: [PATCH v2 5/7] disk: part_dos: Refactor to allow retrieving raw MBR - partition data -Date: Thu, 12 Feb 2026 21:44:59 +0100 -Message-ID: <20260212204511.619392-6-javierm@redhat.com> -X-Mailer: git-send-email 2.53.0 -In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> -References: <20260212204511.619392-1-javierm@redhat.com> -MIME-Version: 1.0 -X-Mimecast-Spam-Score: 0 -X-Mimecast-MFC-PROC-ID: Zs6NXSgdnPvAWNkwYY8acCGlkSTO_JLJJjyY6Cc_c5o_1770929127 -X-Mimecast-Originator: redhat.com -content-type: text/plain; charset="US-ASCII"; x-default=true -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -Refactor the part_get_info_extended() helper function (which already -recursively traverses DOS partitions) to optionally return the raw MBR -partition structure (dos_partition_t). - -This allows other subsystems, such as EFI, to retrieve the partition -details in the legacy MBR format. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Ilias Apalodimas ---- - -(no changes since v1) - - disk/part_dos.c | 66 ++++++++++++++++++++++++++++++------------------- - include/part.h | 14 +++++++++++ - 2 files changed, 55 insertions(+), 25 deletions(-) - -diff --git a/disk/part_dos.c b/disk/part_dos.c -index a69ad8962106..4e1d01b2f21e 100644 ---- a/disk/part_dos.c -+++ b/disk/part_dos.c -@@ -204,7 +204,8 @@ static void print_partition_extended(struct blk_desc *desc, - * @relative: Relative offset for the partition - * @part_num: Current partition number - * @which_part: Target partition number -- * @info: Returns a pointer to the partition info -+ * @info: Returns partition information (optional) -+ * @mbr: Returns MBR partition entry (optional) - * @disksig: Disk signature - * - * Return: 0 on success, negative on error -@@ -212,7 +213,9 @@ static void print_partition_extended(struct blk_desc *desc, - static int part_get_info_extended(struct blk_desc *desc, - lbaint_t ext_part_sector, lbaint_t relative, - int part_num, int which_part, -- struct disk_partition *info, uint disksig) -+ struct disk_partition *info, -+ dos_partition_t *mbr, -+ uint disksig) - { - ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz); - struct disk_partition wdinfo = { 0 }; -@@ -243,9 +246,11 @@ static int part_get_info_extended(struct blk_desc *desc, - if (CONFIG_IS_ENABLED(PARTITION_UUIDS) && !ext_part_sector) - disksig = get_unaligned_le32(&buffer[DOS_PART_DISKSIG_OFFSET]); - -- ret = part_get_info_whole_disk(desc, &wdinfo); -- if (ret) -- return ret; -+ if (info) { -+ ret = part_get_info_whole_disk(desc, &wdinfo); -+ if (ret) -+ return ret; -+ } - - /* Print all primary/logical partitions */ - pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); -@@ -258,25 +263,29 @@ static int part_get_info_extended(struct blk_desc *desc, - (pt->sys_ind != 0) && - (part_num == which_part) && - (ext_part_sector == 0 || is_extended(pt->sys_ind) == 0)) { -- if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) -- info->blksz = wdinfo.blksz; -- else -- info->blksz = DOS_PART_DEFAULT_SECTOR; -- info->start = (lbaint_t)(ext_part_sector + -- get_unaligned_le32(&pt->start_sect)); -- info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); -- part_set_generic_name(desc, part_num, -- (char *)info->name); -- /* sprintf(info->type, "%d, pt->sys_ind); */ -- strcpy((char *)info->type, "U-Boot"); -- info->bootable = get_bootable(pt); -- if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { -- char str[12]; -- -- sprintf(str, "%08x-%02x", disksig, part_num); -- disk_partition_set_uuid(info, str); -+ if (info) { -+ if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) -+ info->blksz = wdinfo.blksz; -+ else -+ info->blksz = DOS_PART_DEFAULT_SECTOR; -+ info->start = (lbaint_t)(ext_part_sector + -+ get_unaligned_le32(&pt->start_sect)); -+ info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); -+ part_set_generic_name(desc, part_num, -+ (char *)info->name); -+ /* sprintf(info->type, "%d, pt->sys_ind); */ -+ strcpy((char *)info->type, "U-Boot"); -+ info->bootable = get_bootable(pt); -+ if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { -+ char str[12]; -+ -+ sprintf(str, "%08x-%02x", disksig, part_num); -+ disk_partition_set_uuid(info, str); -+ } -+ info->sys_ind = pt->sys_ind; - } -- info->sys_ind = pt->sys_ind; -+ if (mbr) -+ memcpy(mbr, pt, sizeof(*mbr)); - return 0; - } - -@@ -296,7 +305,8 @@ static int part_get_info_extended(struct blk_desc *desc, - - return part_get_info_extended(desc, lba_start, - ext_part_sector == 0 ? lba_start : relative, -- part_num, which_part, info, disksig); -+ part_num, which_part, info, -+ mbr, disksig); - } - } - -@@ -328,7 +338,13 @@ static void __maybe_unused part_print_dos(struct blk_desc *desc) - static int __maybe_unused part_get_info_dos(struct blk_desc *desc, int part, - struct disk_partition *info) - { -- return part_get_info_extended(desc, 0, 0, 1, part, info, 0); -+ return part_get_info_extended(desc, 0, 0, 1, part, info, NULL, 0); -+} -+ -+int __maybe_unused part_get_mbr(struct blk_desc *desc, int part, -+ dos_partition_t *mbr) -+{ -+ return part_get_info_extended(desc, 0, 0, 1, part, NULL, mbr, 0); - } - - int is_valid_dos_buf(void *buf) -diff --git a/include/part.h b/include/part.h -index daebbbc2e68f..aed089d00f64 100644 ---- a/include/part.h -+++ b/include/part.h -@@ -704,6 +704,20 @@ int write_mbr_partitions(struct blk_desc *dev, - int layout_mbr_partitions(struct disk_partition *p, int count, - lbaint_t total_sectors); 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[62.151.111.63]) - by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-48371a49dc7sm790085e9.31.2026.02.12.12.45.27 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Thu, 12 Feb 2026 12:45:27 -0800 (PST) -From: Javier Martinez Canillas -To: u-boot@lists.denx.de -Cc: Heinrich Schuchardt , eballetb@redhat.com, - Ilias Apalodimas , - Tom Rini , - Javier Martinez Canillas , - Maks Mishin , Simon Glass -Subject: [PATCH v2 6/7] efi_loader: disk: Extend EFI_PARTITION_INFO_PROTOCOL - to support MBR -Date: Thu, 12 Feb 2026 21:45:00 +0100 -Message-ID: <20260212204511.619392-7-javierm@redhat.com> -X-Mailer: git-send-email 2.53.0 -In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> -References: <20260212204511.619392-1-javierm@redhat.com> -MIME-Version: 1.0 -X-Mimecast-Spam-Score: 0 -X-Mimecast-MFC-PROC-ID: We4wNEbtQuTUTq6Fkgi3HWr3Fx0Twiws4fhF79FLAjg_1770929129 -X-Mimecast-Originator: redhat.com -content-type: text/plain; charset="US-ASCII"; x-default=true -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -The EFI_PARTITION_INFO_PROTOCOL provides detailed information about -partitions. The UEFI specification mentions that both GPT and MBR -partition schemes are supported, but the U-Boot implementation only -supports the former. - -This can cause compatibility issues for platforms whose boot ROM only -supports MBR. This change adds support for MBR partition tables to -the protocol, making U-Boot compatible with systems that require a -legacy MBR table. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Ilias Apalodimas ---- - -(no changes since v1) - - lib/efi_loader/efi_disk.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - -diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c -index 130c4db9606f..f8a57539ec61 100644 ---- a/lib/efi_loader/efi_disk.c -+++ b/lib/efi_loader/efi_disk.c -@@ -475,9 +475,12 @@ static efi_status_t efi_disk_add_dev( - #if CONFIG_IS_ENABLED(DOS_PARTITION) - case PART_TYPE_DOS: - info->type = PARTITION_TYPE_MBR; -- -- /* TODO: implement support for MBR partition types */ -- log_debug("EFI_PARTITION_INFO_PROTOCOL doesn't support MBR\n"); -+ ret = part_get_mbr(desc, part, &info->info.mbr); -+ if (ret) { -+ log_debug("get MBR for part %d failed %ld\n", -+ part, ret); -+ goto error; -+ } - break; - #endif - default: - -From patchwork Thu Feb 12 20:45:01 2026 -Content-Type: text/plain; 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[62.151.111.63]) - by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-48370ac3564sm6753225e9.5.2026.02.12.12.45.29 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Thu, 12 Feb 2026 12:45:29 -0800 (PST) -From: Javier Martinez Canillas -To: u-boot@lists.denx.de -Cc: Heinrich Schuchardt , eballetb@redhat.com, - Ilias Apalodimas , - Tom Rini , - Javier Martinez Canillas -Subject: [PATCH v2 7/7] efi_selftest: Enhance MBR test for - PARTITION_INFO_PROTOCOL -Date: Thu, 12 Feb 2026 21:45:01 +0100 -Message-ID: <20260212204511.619392-8-javierm@redhat.com> -X-Mailer: git-send-email 2.53.0 -In-Reply-To: <20260212204511.619392-1-javierm@redhat.com> -References: <20260212204511.619392-1-javierm@redhat.com> -MIME-Version: 1.0 -X-Mimecast-Spam-Score: 0 -X-Mimecast-MFC-PROC-ID: yunYq1YIsh16Z4DQJL5hOi7pdkGhTA9a43HFld0F1eg_1770929132 -X-Mimecast-Originator: redhat.com -content-type: text/plain; charset="US-ASCII"; x-default=true -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -The EFI_PARTITION_INFO_PROTOCOL test was added before the protocol fully -supported MBR partitions. As a result, it lacked specific checks for the -content of the raw MBR partition record. - -Now that MBR support has been implemented, enhance the selftest to provide -coverage for the MBR entries too. - -This verifies that the protocol correctly reads and exposes MBR partition -records and prevents this functionality to regress due future changes. - -Signed-off-by: Javier Martinez Canillas -Acked-by: Ilias Apalodimas -Reviewed-by: Heinrich Schuchardt ---- - -(no changes since v1) - - lib/efi_selftest/efi_selftest_block_device.c | 26 ++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c -index f145e58a267a..9c4be834eebb 100644 ---- a/lib/efi_selftest/efi_selftest_block_device.c -+++ b/lib/efi_selftest/efi_selftest_block_device.c -@@ -19,6 +19,7 @@ - #include "efi_selftest_disk_image.h" - #include - #include -+#include - - /* Block size of compressed disk image */ - #define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8 -@@ -319,6 +320,25 @@ static int execute(void) - u64 pos; - char block_io_aligned[1 << LB_BLOCK_SIZE] __aligned(1 << LB_BLOCK_SIZE); - -+ /* -+ * The test disk image is defined in efi_selftest_disk_image.h, -+ * it contains a single FAT12 partition of 127 sectors size. -+ */ -+ static const dos_partition_t mbr_expected = { -+ .boot_ind = 0x00, -+ .head = 0x00, -+ .sector = 0x02, -+ .cyl = 0x00, -+ .sys_ind = 0x01, /* FAT12 */ -+ .end_head = 0x02, -+ .end_sector = 0x02, -+ .end_cyl = 0x00, -+ /* LBA 1 */ -+ .start_sect = cpu_to_le32(1), -+ /* Size 127 sectors (0x7f) */ -+ .nr_sects = cpu_to_le32(127), -+ }; -+ - /* Connect controller to virtual disk */ - ret = boottime->connect_controller(disk_handle, NULL, NULL, 1); - if (ret != EFI_SUCCESS) { -@@ -405,6 +425,12 @@ static int execute(void) - return EFI_ST_FAILURE; - } - -+ /* Compare the obtained MBR with the expected one for the test partition */ -+ if (memcmp(&part_info->info.mbr, &mbr_expected, sizeof(mbr_expected))) { -+ efi_st_error("MBR partition record mismatch\n"); -+ return EFI_ST_FAILURE; -+ } -+ - /* Open the simple file system protocol */ - ret = boottime->open_protocol(handle_partition, - &guid_simple_file_system_protocol, diff --git a/nvme-Fix-missing-inbound-DMA-offset-calculation.patch b/nvme-Fix-missing-inbound-DMA-offset-calculation.patch new file mode 100644 index 0000000..9731488 --- /dev/null +++ b/nvme-Fix-missing-inbound-DMA-offset-calculation.patch @@ -0,0 +1,219 @@ +From patchwork Thu Apr 30 14:54:12 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2231306 +X-Patchwork-Delegate: trini@ti.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4g5xyj6V6Pz1xqf + for ; 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+ dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id BC53E68AFE; Thu, 30 Apr 2026 16:54:12 +0200 (CEST) +To: Bin Meng , + Andrew Goodbody , + Tom Rini +Cc: Peter Robinson , + Matthias Brugger , + Andrea della Porta , u-boot@lists.denx.de +Subject: [PATCH] nvme: Fix missing inbound DMA offset calculation +Message-Id: <20260430145412.BC53E68AFE@verein.lst.de> +Date: Thu, 30 Apr 2026 16:54:12 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +U-Boot currently does not account for PCIe bridges with a non-zero +inbound access offset when talking NVMe, it only works on platforms +where this offset happens to be zero. + +This patch enhances the NVMe driver with the ability to also handle +these cases. The fix is required to boot e.g. the Raspberry Pi5 from +NVMe. + +Signed-off-by: Torsten Duwe +--- + +Kudos for the idea of case discrimination go to Andrea; this eases +things a lot. + +I do consider this a bug fix. The problem has popped up during RPi5 +development but really is a generic major defect IMHO. Please apply +wherever appropriate. + + Torsten + +--- + drivers/nvme/nvme.c | 39 ++++++++++++++++++++++++++------------- + 1 file changed, 26 insertions(+), 13 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 2b14437f69c..8056f52fb50 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -27,6 +28,18 @@ + #define IO_TIMEOUT 30 + #define MAX_PRP_POOL 512 + ++/* ++ * This macro detects the correct inbound DMA offset in both cases: ++ * 1) the NVMe is mentioned in the device tree, along with its parent, ++ * and no intermediate PCIe bus node in between. ++ * 2) the NVMe was found dynamically by PCI enumeration which has created ++ * an intermediate PCIe bus node. That node will be skipped and the offset ++ * looked up in the grandparent. ++ */ ++#define DEV_ADDR(a) (dev_has_ofnode(dev->udev) ? \ ++ dev_phys_to_bus(dev->udev, (a)) : \ ++ dev_phys_to_bus(dev->udev->parent, (a))) ++ + static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) + { + int timeout; +@@ -91,12 +104,12 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + i = 0; + while (nprps) { + if ((i == (prps_per_page - 1)) && nprps > 1) { +- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + +- page_size); ++ *(prp_pool + i) = cpu_to_le64(DEV_ADDR((ulong)prp_pool + ++ page_size)); + i = 0; + prp_pool += page_size; + } +- *(prp_pool + i++) = cpu_to_le64(dma_addr); ++ *(prp_pool + i++) = cpu_to_le64(DEV_ADDR(dma_addr)); + dma_addr += page_size; + nprps--; + } +@@ -393,8 +406,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) + dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; + + writel(aqa, &dev->bar->aqa); +- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); +- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); ++ nvme_writeq(DEV_ADDR((ulong)nvmeq->sq_cmds), &dev->bar->asq); ++ nvme_writeq(DEV_ADDR((ulong)nvmeq->cqes), &dev->bar->acq); + + result = nvme_enable_ctrl(dev); + if (result) +@@ -420,7 +433,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_cq.opcode = nvme_admin_create_cq; +- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); ++ c.create_cq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->cqes)); + c.create_cq.cqid = cpu_to_le16(qid); + c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_cq.cq_flags = cpu_to_le16(flags); +@@ -437,7 +450,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_sq.opcode = nvme_admin_create_sq; +- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); ++ c.create_sq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->sq_cmds)); + c.create_sq.sqid = cpu_to_le16(qid); + c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_sq.sq_flags = cpu_to_le16(flags); +@@ -458,14 +471,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.identify.opcode = nvme_admin_identify; + c.identify.nsid = cpu_to_le32(nsid); +- c.identify.prp1 = cpu_to_le64(dma_addr); ++ c.identify.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); + + length -= (page_size - offset); + if (length <= 0) { + c.identify.prp2 = 0; + } else { + dma_addr += (page_size - offset); +- c.identify.prp2 = cpu_to_le64(dma_addr); ++ c.identify.prp2 = cpu_to_le64(DEV_ADDR(dma_addr)); + } + + c.identify.cns = cpu_to_le32(cns); +@@ -490,7 +503,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_get_features; + c.features.nsid = cpu_to_le32(nsid); +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + + ret = nvme_submit_admin_cmd(dev, &c, result); +@@ -516,7 +529,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, + + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_set_features; +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + c.features.dword11 = cpu_to_le32(dword11); + +@@ -785,8 +798,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + c.rw.slba = cpu_to_le64(slba); + slba += lbas; + c.rw.length = cpu_to_le16(lbas - 1); +- c.rw.prp1 = cpu_to_le64(temp_buffer); +- c.rw.prp2 = cpu_to_le64(prp2); ++ c.rw.prp1 = cpu_to_le64(DEV_ADDR(temp_buffer)); ++ c.rw.prp2 = cpu_to_le64(DEV_ADDR(prp2)); + status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], + &c, NULL, IO_TIMEOUT); + if (status) diff --git a/rpi-enable-nvme.patch b/rpi-enable-nvme.patch new file mode 100644 index 0000000..c5a2ff1 --- /dev/null +++ b/rpi-enable-nvme.patch @@ -0,0 +1,34 @@ +From 94d8dfad9b381cd914fd11b2c6286084dd46b7a9 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sun, 29 Mar 2026 20:28:41 +0100 +Subject: [PATCH] rpi: enable nvme + +Signed-off-by: Peter Robinson +--- + configs/rpi_arm64_defconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 38af5029403..ed4ae6ff522 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -15,7 +15,7 @@ CONFIG_BOOTSTD_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_FDT_SIMPLEFB=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="pci enum; usb start;" ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_SYS_PBSIZE=1049 + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -41,6 +41,7 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_MMC_SDHCI_BCMSTB=y + CONFIG_BCMGENET=y ++CONFIG_NVME_PCI=y + CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set +-- +2.54.0 + diff --git a/sources b/sources index d751131..5a8707a 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.04.tar.bz2) = c5fca2abc533759985dfcc6d071d154007535787b0bbd569b61bda1fe2f3a31fba08481c8caf18cf5f2bc79609f50dee504977a8b65e8c4cc21f277268232e03 +SHA512 (u-boot-2026.07-rc1.tar.bz2) = 9e926fdea78c02c81ebe79383623ec34af78debee3dcb35a7b1968646cd3b296768e2acbb29ccf93b92031905761be4424241dabc01ee16202e1efb47c9589eb diff --git a/uboot-tools.spec b/uboot-tools.spec index f39ee82..f589fb8 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -#global candidate rc0 +%global candidate rc1 %if 0%{?rhel} %bcond_with toolsonly %else @@ -9,8 +9,8 @@ %global opensbi opensbi Name: uboot-tools -Version: 2026.04 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Version: 2026.07 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -37,7 +37,6 @@ Patch6: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch Patch7: uefi-enable-SetVariableRT-with-volotile-storage.patch # Enable UEFI HTTPS boot for all Fedora firmware Patch8: uefi-enable-https-boot-by-default.patch -Patch9: efi_loader-disk-Add-EFI_PARTITION_INFO_PROTOCOL-support-for-MBR.patch # Device improvments # USB-PD improvements @@ -53,9 +52,10 @@ Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi Patch20: ARM-RPi5-Enable-PCIe.patch -Patch21: 0001-Add-bcm2712-compat.patch -Patch22: ARM-RPi-PCIe-fixes.patch -Patch23: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch +Patch21: nvme-Fix-missing-inbound-DMA-offset-calculation.patch +Patch22: rpi-enable-nvme.patch +Patch23: 0001-Add-bcm2712-compat.patch +Patch24: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch BuildRequires: bc BuildRequires: bison @@ -314,6 +314,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Fri May 01 2026 Peter Robinson - 1:2026.07-0.1.rc1 +- Update to 2026.07 RC1 + * Sat Apr 11 2026 Peter Robinson - 1:2026.04-2 - Fix PCIe/USB on Raspberry Pi 4 (rhbz#2448365) - Fix detection of some revisions of RPi5 diff --git a/uefi-enable-https-boot-by-default.patch b/uefi-enable-https-boot-by-default.patch index a30879b..c584f9b 100644 --- a/uefi-enable-https-boot-by-default.patch +++ b/uefi-enable-https-boot-by-default.patch @@ -1,41 +1,21 @@ -From 8253233373e608dd5b41544d63e0555f713fe876 Mon Sep 17 00:00:00 2001 +From 4e6c3762cc86f6fab6f18ffd2a99ff921cd0fd38 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Wed, 10 Sep 2025 13:37:01 +0100 +Date: Sun, 3 May 2026 09:24:34 +0100 Subject: [PATCH] enable https boot by default +Signed-off-by: Peter Robinson --- - Kconfig | 3 ++- cmd/Kconfig | 1 + lib/efi_loader/Kconfig | 1 + lib/mbedtls/Kconfig | 3 ++- + net/Kconfig | 3 ++- 4 files changed, 6 insertions(+), 2 deletions(-) -diff --git a/Kconfig b/Kconfig -index 70125c4e5a6..89e82d7818f 100644 ---- a/Kconfig -+++ b/Kconfig -@@ -774,7 +774,7 @@ menu "Networking" - - choice - prompt "Networking stack" -- default NET -+ default NET_LWIP - - config NO_NET - bool "No networking support" -@@ -790,6 +790,7 @@ config NET - - config NET_LWIP - bool "Use lwIP for networking stack" -+ default y - imply NETDEVICES - help - Include networking support based on the lwIP (lightweight IP) diff --git a/cmd/Kconfig b/cmd/Kconfig -index 29de857ba7c..277b7be0b89 100644 +index c71c6824a19..8ff14adffe1 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -2174,6 +2174,7 @@ config CMD_WGET +@@ -2289,6 +2289,7 @@ config CMD_WGET config WGET_HTTPS bool "wget https" @@ -44,15 +24,15 @@ index 29de857ba7c..277b7be0b89 100644 depends on PROT_TCP_LWIP depends on MBEDTLS_LIB diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig -index 900113ca3e9..2188b4bd6e5 100644 +index 0b6c2eaac60..268d9eb8544 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig -@@ -563,6 +563,7 @@ config EFI_BOOTMGR +@@ -609,6 +609,7 @@ config EFI_BOOTMGR config EFI_HTTP_BOOT bool "EFI HTTP Boot support" + default y - depends on NET || NET_LWIP + depends on NET select CMD_NET select CMD_DHCP diff --git a/lib/mbedtls/Kconfig b/lib/mbedtls/Kconfig @@ -76,6 +56,27 @@ index 789721ee6cd..7a241c2bc26 100644 select MBEDTLS_LIB_X509 endchoice +diff --git a/net/Kconfig b/net/Kconfig +index e712a0dd2ac..3158d37dff7 100644 +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -16,7 +16,7 @@ if NET + + choice + prompt "Networking stack" +- default NET_LEGACY ++ default NET_LWIP + + config NET_LEGACY + bool "Legacy U-Boot networking stack" +@@ -27,6 +27,7 @@ config NET_LEGACY + + config NET_LWIP + bool "Use lwIP for networking stack" ++ default y + select NETDEVICES + help + Include networking support based on the lwIP (lightweight IP) -- -2.51.0 +2.54.0 From a1afa6b9d73e7bfa6a6dde09eac2573e775dff4a Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 29 May 2026 14:14:46 +0100 Subject: [PATCH 26/38] 2026.07 RC3 --- ...r-install-device-tree-on-configurati.patch | 85 --- ARM-RPi5-Enable-PCIe.patch | 526 +++++++++--------- Fix-NVMe-not-only-on-Raspberry-Pi-5.patch | 215 +++++++ ...state-access-to-memory-above-ram_top.patch | 50 ++ ...e-generic-MMC-device-tree-properties.patch | 167 ++++++ ...-non-removable-check-in-bcm2712-init.patch | 185 ++++++ ...ssing-inbound-DMA-offset-calculation.patch | 219 -------- ...hip-Enable-preboot-start-for-pci-usb.patch | 249 ++++++--- rpi-enable-nvme.patch | 8 - ...ble-MBEDTLS-LWIP-WGET-and-WGET_HTTPS.patch | 171 ++++++ sources | 2 +- uboot-tools.spec | 31 +- uefi-enable-https-boot-by-default.patch | 6 +- ..._location-for-finding-the-DT-on-disk.patch | 33 +- ...pi-Add-brcm-bcm2712-hdmi0-compatible.patch | 152 +++++ 15 files changed, 1407 insertions(+), 692 deletions(-) delete mode 100644 0001-Revert-efi_loader-install-device-tree-on-configurati.patch create mode 100644 Fix-NVMe-not-only-on-Raspberry-Pi-5.patch create mode 100644 Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch create mode 100644 mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch create mode 100644 mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch delete mode 100644 nvme-Fix-missing-inbound-DMA-offset-calculation.patch create mode 100644 rpi_arm64-Enable-MBEDTLS-LWIP-WGET-and-WGET_HTTPS.patch create mode 100644 video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch diff --git a/0001-Revert-efi_loader-install-device-tree-on-configurati.patch b/0001-Revert-efi_loader-install-device-tree-on-configurati.patch deleted file mode 100644 index 0cc6786..0000000 --- a/0001-Revert-efi_loader-install-device-tree-on-configurati.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 72a5b6b3cafc7d1f58f451c26eedfb678e54bd9f Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sun, 7 Sep 2025 16:32:30 +0100 -Subject: [PATCH] Revert "efi_loader: install device-tree on configuration - table on every invocation" - -This reverts commit 7e624377e99314bdfac6cb5a3d216dff49a047e9. ---- - lib/efi_loader/efi_helper.c | 39 ++++++++++--------------------------- - 1 file changed, 10 insertions(+), 29 deletions(-) - -diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c -index 44b806aadc4..f211782389a 100644 ---- a/lib/efi_loader/efi_helper.c -+++ b/lib/efi_loader/efi_helper.c -@@ -456,30 +456,11 @@ efi_status_t efi_env_set_load_options(efi_handle_t handle, - */ - static efi_status_t copy_fdt(void **fdtp) - { -+ unsigned long fdt_pages; - efi_status_t ret = 0; - void *fdt, *new_fdt; -- static u64 new_fdt_addr; -- static efi_uintn_t fdt_pages; -- ulong fdt_size; -- -- /* -- * Remove the configuration table that might already be -- * installed, ignoring EFI_NOT_FOUND if no device-tree -- * is installed -- */ -- efi_install_configuration_table(&efi_guid_fdt, NULL); -- -- if (new_fdt_addr) { -- log_debug("%s: Found allocated memory at %#llx, with %#zx pages\n", -- __func__, new_fdt_addr, fdt_pages); -- -- ret = efi_free_pages(new_fdt_addr, fdt_pages); -- if (ret != EFI_SUCCESS) -- log_err("Unable to free up existing FDT memory region\n"); -- -- new_fdt_addr = 0; -- fdt_pages = 0; -- } -+ u64 new_fdt_addr; -+ uint fdt_size; - - /* - * Give us at least 12 KiB of breathing room in case the device tree -@@ -494,18 +475,15 @@ static efi_status_t copy_fdt(void **fdtp) - &new_fdt_addr); - if (ret != EFI_SUCCESS) { - log_err("Failed to reserve space for FDT\n"); -- return ret; -+ goto done; - } -- log_debug("%s: Allocated memory at %#llx, with %#zx pages\n", -- __func__, new_fdt_addr, fdt_pages); -- - new_fdt = (void *)(uintptr_t)new_fdt_addr; - memcpy(new_fdt, fdt, fdt_totalsize(fdt)); - fdt_set_totalsize(new_fdt, fdt_size); - -- *fdtp = new_fdt; -- -- return EFI_SUCCESS; -+ *fdtp = (void *)(uintptr_t)new_fdt_addr; -+done: -+ return ret; - } - - /** -@@ -558,6 +536,9 @@ efi_status_t efi_install_fdt(void *fdt) - const char *fdt_opt; - uintptr_t fdt_addr; - -+ /* Look for device tree that is already installed */ -+ if (efi_get_configuration_table(&efi_guid_fdt)) -+ return EFI_SUCCESS; - /* Check if there is a hardware device tree */ - fdt_opt = env_get("fdt_addr"); - /* Use our own device tree as fallback */ --- -2.51.0 - diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch index f711dc4..f86ae64 100644 --- a/ARM-RPi5-Enable-PCIe.patch +++ b/ARM-RPi5-Enable-PCIe.patch @@ -1,9 +1,9 @@ -From patchwork Tue Apr 28 16:39:18 2026 +From patchwork Sat May 23 16:34:24 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229734 +X-Patchwork-Id: 2243363 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org @@ -16,17 +16,17 @@ Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mTf0XgQz1yHv - for ; Wed, 29 Apr 2026 02:43:34 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN75k43NLz1xx5 + for ; Sun, 24 May 2026 02:34:34 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id BE23F84658; - Tue, 28 Apr 2026 18:43:23 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id DA6A1848D1; + Sat, 23 May 2026 18:34:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 65D5F845D8; Tue, 28 Apr 2026 18:39:24 +0200 (CEST) + id AA584848B6; Sat, 23 May 2026 18:34:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -35,14 +35,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 81D7A842C7 - for ; Tue, 28 Apr 2026 18:39:22 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id B859684659 + for ; Sat, 23 May 2026 18:34:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id C5D4268C4E; Tue, 28 Apr 2026 18:39:18 +0200 (CEST) -Subject: [PATCH v2 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window + id B4EE268BEB; Sat, 23 May 2026 18:34:24 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -64,11 +66,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163918.C5D4268C4E@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:18 +0200 (CEST) +Message-Id: <20260523163424.B4EE268BEB@verein.lst.de> +Date: Sat, 23 May 2026 18:34:24 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -94,6 +94,7 @@ works sufficiently well for a boot loader. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato +Reviewed-by: Peter Robinson --- arch/arm/mach-bcm283x/init.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) @@ -127,35 +128,36 @@ index 7a1de22e0ae..7a2faaa4de6 100644 /* SoC bus */ .virt = 0x107c000000UL, -From patchwork Tue Apr 28 16:39:22 2026 +From patchwork Sat May 23 16:34:26 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229735 +X-Patchwork-Id: 2243364 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) + key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mTn1JZ7z1yHv - for ; Wed, 29 Apr 2026 02:43:41 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN75r2nngz1xx5 + for ; Sun, 24 May 2026 02:34:40 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 027E384669; - Tue, 28 Apr 2026 18:43:24 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 2890A848BF; + Sat, 23 May 2026 18:34:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id A0642845D8; Tue, 28 Apr 2026 18:39:29 +0200 (CEST) + id 3969B848F3; Sat, 23 May 2026 18:34:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -164,14 +166,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 3B7B4842C7 - for ; Tue, 28 Apr 2026 18:39:25 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id C0D4A84659 + for ; Sat, 23 May 2026 18:34:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 977E668CFE; Tue, 28 Apr 2026 18:39:22 +0200 (CEST) -Subject: [PATCH v2 2/9] pci: brcmstb: Fix PCIe bus numbers + id BDC5168C7B; Sat, 23 May 2026 18:34:26 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 2/9] pci: brcmstb: Fix PCIe bus numbers To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -193,11 +197,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163922.977E668CFE@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:22 +0200 (CEST) +Message-Id: <20260523163426.BDC5168C7B@verein.lst.de> +Date: Sat, 23 May 2026 18:34:26 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -228,6 +230,7 @@ subtracting the base bus number. Signed-off-by: Andrea della Porta Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato +Reviewed-by: Peter Robinson --- drivers/pci/pcie_brcmstb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) @@ -246,36 +249,35 @@ index f089c48f028..47c0802df23 100644 unsigned int pci_func = PCI_FUNC(bdf); int idx; -From patchwork Tue Apr 28 16:39:25 2026 +From patchwork Sat May 23 16:34:28 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229737 +X-Patchwork-Id: 2243366 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mTx6XSTz1yHv - for ; Wed, 29 Apr 2026 02:43:49 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN7614lMDz1xx5 + for ; Sun, 24 May 2026 02:34:49 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 3A10E84674; - Tue, 28 Apr 2026 18:43:24 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 63143848A4; + Sat, 23 May 2026 18:34:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 615EF845E3; Tue, 28 Apr 2026 18:39:32 +0200 (CEST) + id 99621848A4; Sat, 23 May 2026 18:34:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -284,14 +286,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id C130184605 - for ; Tue, 28 Apr 2026 18:39:27 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id 8BD35848B6 + for ; Sat, 23 May 2026 18:34:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 6DF1968D07; Tue, 28 Apr 2026 18:39:25 +0200 (CEST) -Subject: [PATCH v2 3/9] pci: brcmstb: Support different variants using a cfg + id C612768D05; Sat, 23 May 2026 18:34:28 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 3/9] pci: brcmstb: Support different variants using a cfg struct To: Peter Robinson , Matthias Brugger @@ -314,11 +318,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163925.6DF1968D07@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:25 +0200 (CEST) +Message-Id: <20260523163428.C612768D05@verein.lst.de> +Date: Sat, 23 May 2026 18:34:28 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -342,20 +344,18 @@ variants when the bcm2712 was added (see e.g. linux commit 10dbedad3c818 which is the last in a longer set of changes). This patch brings in this required infrastructure and adds a differentiation between 2711 and 2712 register layouts on top. -It also accounts for the bcm2712 reset logic quirk that the software -init bit must not remain set, albeit the reset control location is -only corrected in patch#6 of this series. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato +Reviewed-by: Neil Armstrong --- - .../mach-bcm283x/include/mach/acpi/bcm2711.h | 6 +- - drivers/pci/pcie_brcmstb.c | 122 ++++++++++++++++-- - 2 files changed, 114 insertions(+), 14 deletions(-) + .../mach-bcm283x/include/mach/acpi/bcm2711.h | 5 + + drivers/pci/pcie_brcmstb.c | 104 ++++++++++++++++-- + 2 files changed, 99 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -index a86875b1833..6eb5389b858 100644 +index a86875b1833..5171c593c72 100644 --- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h @@ -70,6 +70,7 @@ @@ -366,11 +366,10 @@ index a86875b1833..6eb5389b858 100644 #define PCIE_MISC_PCIE_STATUS 0x4068 #define STATUS_PCIE_PORT_MASK 0x80 #define STATUS_PCIE_PORT_SHIFT 7 -@@ -107,7 +108,10 @@ - #define PCIE_MSI_INTR2_MASK_SET 0x4510 +@@ -108,6 +109,10 @@ #define PCIE_RGR1_SW_INIT_1 0x9210 --#define PCIE_EXT_CFG_INDEX 0x9000 + #define PCIE_EXT_CFG_INDEX 0x9000 +#define RGR1_SW_INIT_1_PERST_MASK 0x1 +#define RGR1_SW_INIT_1_PERSTB_MASK 0x4 +#define RGR1_SW_INIT_1_INIT_MASK 0x2 @@ -379,17 +378,15 @@ index a86875b1833..6eb5389b858 100644 #define PCIE_EXT_CFG_DATA 0x8000 diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 47c0802df23..261f8790528 100644 +index 47c0802df23..5cb39dfd136 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c -@@ -49,6 +49,28 @@ +@@ -49,6 +49,24 @@ #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define SSC_STATUS_PLL_LOCK_SHIFT 11 +enum { + RGR1_SW_INIT_1, -+ EXT_CFG_INDEX, -+ EXT_CFG_DATA, + PCIE_HARD_DEBUG, +}; + @@ -404,14 +401,12 @@ index 47c0802df23..261f8790528 100644 + const int *offsets; + const enum brcm_pcie_type type; + void (*perst_set)(struct brcm_pcie *pcie, u32 val); -+ void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); -+ bool (*rc_mode)(struct brcm_pcie *pcie); +}; + /** * struct brcm_pcie - the PCIe controller state * @base: Base address of memory mapped IO registers of the controller -@@ -61,6 +83,7 @@ struct brcm_pcie { +@@ -61,6 +79,7 @@ struct brcm_pcie { int gen; bool ssc; @@ -419,7 +414,7 @@ index 47c0802df23..261f8790528 100644 }; /** -@@ -104,6 +127,36 @@ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) +@@ -104,6 +123,36 @@ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; } @@ -443,7 +438,7 @@ index 47c0802df23..261f8790528 100644 + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); +} + -+static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) ++static void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) +{ + if (val) + setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], @@ -456,42 +451,31 @@ index 47c0802df23..261f8790528 100644 /** * brcm_pcie_link_up() - Check whether the PCIe link is up * @pcie: Pointer to the PCIe controller state -@@ -150,8 +203,8 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, - /* For devices, write to the config space index register */ - idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0); - -- writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); -- *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; -+ writel(idx, pcie->base + pcie->pcie_cfg->offsets[EXT_CFG_INDEX]); -+ *paddress = pcie->base + pcie->pcie_cfg->offsets[EXT_CFG_DATA] + offset; - - return 0; - } -@@ -365,8 +418,9 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -365,8 +414,9 @@ static int brcm_pcie_probe(struct udevice *dev) * e.g. BCM7278, the fundamental reset should not be asserted here. * This will need to be changed when support for other SoCs is added. */ - setbits_le32(base + PCIE_RGR1_SW_INIT_1, - PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK); -+ pcie->pcie_cfg->bridge_sw_init_set(pcie, 1); ++ brcm_pcie_bridge_sw_init_set(pcie, 1); + if (pcie->pcie_cfg->type != BCM2712) + pcie->pcie_cfg->perst_set(pcie, 1); /* * The delay is a safety precaution to preclude the reset signal * from looking like a glitch. -@@ -374,9 +428,9 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -374,9 +424,9 @@ static int brcm_pcie_probe(struct udevice *dev) udelay(100); /* Take the bridge out of reset */ - clrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); -+ pcie->pcie_cfg->bridge_sw_init_set(pcie, 0); ++ brcm_pcie_bridge_sw_init_set(pcie, 0); - clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, + clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); /* Wait for SerDes to be stable */ -@@ -426,8 +480,7 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -426,8 +476,7 @@ static int brcm_pcie_probe(struct udevice *dev) brcm_pcie_set_gen(pcie, pcie->gen); /* Unassert the fundamental reset */ @@ -501,16 +485,7 @@ index 47c0802df23..261f8790528 100644 /* * Wait for 100ms after PERST# deassertion; see PCIe CEM specification -@@ -446,7 +499,7 @@ static int brcm_pcie_probe(struct udevice *dev) - return -EINVAL; - } - -- if (!brcm_pcie_rc_mode(pcie)) { -+ if (!pcie->pcie_cfg->rc_mode(pcie)) { - printf("PCIe misconfigured; is in EP mode\n"); - return -EINVAL; - } -@@ -514,14 +567,25 @@ static int brcm_pcie_remove(struct udevice *dev) +@@ -514,14 +563,25 @@ static int brcm_pcie_remove(struct udevice *dev) void __iomem *base = pcie->base; /* Assert fundamental reset */ @@ -525,7 +500,7 @@ index 47c0802df23..261f8790528 100644 /* Shutdown bridge */ - setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); -+ pcie->pcie_cfg->bridge_sw_init_set(pcie, 1); ++ brcm_pcie_bridge_sw_init_set(pcie, 1); + + /* + * For the controllers that are utilizing reset for bridge Sw init, @@ -535,11 +510,11 @@ index 47c0802df23..261f8790528 100644 + * and start accessing device memory. + */ + if (pcie->pcie_cfg->type == BCM2712) -+ pcie->pcie_cfg->bridge_sw_init_set(pcie, 0); ++ brcm_pcie_bridge_sw_init_set(pcie, 0); return 0; } -@@ -546,6 +610,7 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) +@@ -546,6 +606,7 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) else pcie->gen = max_link_speed; @@ -547,14 +522,12 @@ index 47c0802df23..261f8790528 100644 return 0; } -@@ -554,8 +619,39 @@ static const struct dm_pci_ops brcm_pcie_ops = { +@@ -554,8 +615,31 @@ static const struct dm_pci_ops brcm_pcie_ops = { .write_config = brcm_pcie_write_config, }; +static const int pcie_offsets[] = { + [RGR1_SW_INIT_1] = 0x9210, -+ [EXT_CFG_INDEX] = 0x9000, -+ [EXT_CFG_DATA] = 0x8000, + [PCIE_HARD_DEBUG] = 0x4204, +}; + @@ -562,14 +535,10 @@ index 47c0802df23..261f8790528 100644 + .offsets = pcie_offsets, + .type = BCM2711, + .perst_set = brcm_pcie_perst_set_generic, -+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, -+ .rc_mode = brcm_pcie_rc_mode, +}; + +static const int pcie_offsets_bcm2712[] = { + [RGR1_SW_INIT_1] = 0x0, -+ [EXT_CFG_INDEX] = 0x9000, -+ [EXT_CFG_DATA] = 0x8000, + [PCIE_HARD_DEBUG] = 0x4304, +}; + @@ -577,8 +546,6 @@ index 47c0802df23..261f8790528 100644 + .offsets = pcie_offsets_bcm2712, + .type = BCM2712, + .perst_set = brcm_pcie_perst_set_2712, -+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, -+ .rc_mode = brcm_pcie_rc_mode, +}; + static const struct udevice_id brcm_pcie_ids[] = { @@ -589,12 +556,12 @@ index 47c0802df23..261f8790528 100644 }; -From patchwork Tue Apr 28 16:39:29 2026 +From patchwork Sat May 23 16:34:30 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229738 +X-Patchwork-Id: 2243367 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org @@ -608,17 +575,17 @@ Received: from phobos.denx.de (phobos.denx.de (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mV66Q8Wz1yHv - for ; Wed, 29 Apr 2026 02:43:58 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76L65v2z1xx5 + for ; Sun, 24 May 2026 02:35:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 753C58467E; - Tue, 28 Apr 2026 18:43:24 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 896D584932; + Sat, 23 May 2026 18:34:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; 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Tue, 28 Apr 2026 18:39:29 +0200 (CEST) -Subject: [PATCH v2 4/9] pci: brcmstb: Add RPi5 reset facilities + id DA8E768D09; Sat, 23 May 2026 18:34:30 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 4/9] reset: Add RPi5 brcmstb reset facilities To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -656,11 +625,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163929.3501268D0D@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:29 +0200 (CEST) +Message-Id: <20260523163430.DA8E768D09@verein.lst.de> +Date: Sat, 23 May 2026 18:34:30 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -687,10 +654,10 @@ Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato --- configs/rpi_arm64_defconfig | 1 + - drivers/reset/Kconfig | 7 +++ + drivers/reset/Kconfig | 8 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-brcmstb.c | 97 +++++++++++++++++++++++++++++++++++ - 4 files changed, 106 insertions(+) + 4 files changed, 107 insertions(+) create mode 100644 drivers/reset/reset-brcmstb.c diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig @@ -706,14 +673,15 @@ index 69e8e72c5d7..153d7ed301e 100644 CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index 66911199c8b..e0561df8058 100644 +index 2fd91d6299c..8f4c9e29baa 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig -@@ -64,6 +64,13 @@ config RESET_BCM6345 +@@ -64,6 +64,14 @@ config RESET_BCM6345 help Support reset controller on BCM6345. +config RESET_BRCMSTB ++ depends on ARCH_BCM283X + bool "Generic Reset controller driver for Broadcom" + help + This enables reset controller for Broadcom devices. @@ -724,7 +692,7 @@ index 66911199c8b..e0561df8058 100644 bool "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index 088545c6473..ad5fe6b6184 100644 +index ee5b009d134..ebf3d7425a4 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o @@ -839,12 +807,12 @@ index 00000000000..7861f7c9baf + .priv_auto = sizeof(struct brcmstb_reset), +}; -From patchwork Tue Apr 28 16:39:32 2026 +From patchwork Sat May 23 16:34:33 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229739 +X-Patchwork-Id: 2243368 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org @@ -858,17 +826,17 @@ Received: from phobos.denx.de (phobos.denx.de (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mVK2R1cz1yHv - for ; Wed, 29 Apr 2026 02:44:09 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76Y28Xyz1xx5 + for ; Sun, 24 May 2026 02:35:17 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id AF8D884686; - Tue, 28 Apr 2026 18:43:24 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id C8E4B8493F; + Sat, 23 May 2026 18:34:39 +0200 (CEST) Authentication-Results: phobos.denx.de; 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spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 5540868D0F; Tue, 28 Apr 2026 18:39:32 +0200 (CEST) -Subject: [PATCH v2 5/9] pci: brcmstb: Add RPi5 rescal reset facilities + id 3B46568D0D; Sat, 23 May 2026 18:34:33 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 5/9] reset: Add RPi5 rescal reset facilities To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -906,11 +876,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163932.5540868D0F@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:32 +0200 (CEST) +Message-Id: <20260523163433.3B46568D0D@verein.lst.de> +Date: Sat, 23 May 2026 18:34:33 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -937,10 +905,10 @@ Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato --- configs/rpi_arm64_defconfig | 1 + - drivers/reset/Kconfig | 7 ++ + drivers/reset/Kconfig | 8 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-brcmstb-rescal.c | 103 +++++++++++++++++++++++++++ - 4 files changed, 112 insertions(+) + 4 files changed, 113 insertions(+) create mode 100644 drivers/reset/reset-brcmstb-rescal.c diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig @@ -956,14 +924,15 @@ index 153d7ed301e..38af5029403 100644 CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index e0561df8058..b4237bf98bf 100644 +index 8f4c9e29baa..e6c23368428 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig -@@ -71,6 +71,13 @@ config RESET_BRCMSTB +@@ -72,6 +72,14 @@ config RESET_BRCMSTB If you wish to use reset resources managed by the Broadcom Reset Controller, say Y here. Otherwise, say N. +config RESET_BRCMSTB_RESCAL ++ depends on ARCH_BCM283X + bool "Generic Rescal Reset controller driver for Broadcom" + help + Support rescal reset controller on Broadcom. @@ -974,7 +943,7 @@ index e0561df8058..b4237bf98bf 100644 bool "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index ad5fe6b6184..c369bdb3d6c 100644 +index ebf3d7425a4..c7a9da3268d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o @@ -1095,35 +1064,36 @@ index 00000000000..fc8fcfa8b3f + .priv_auto = sizeof(struct brcm_rescal_reset), +}; -From patchwork Tue Apr 28 16:39:36 2026 +From patchwork Sat May 23 16:34:35 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229740 +X-Patchwork-Id: 2243369 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mVT5K55z1yHv - for ; Wed, 29 Apr 2026 02:44:17 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76l00M8z1xx5 + for ; Sun, 24 May 2026 02:35:26 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id E33338468B; - Tue, 28 Apr 2026 18:43:24 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 100FA84922; + Sat, 23 May 2026 18:34:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 2414F845D8; Tue, 28 Apr 2026 18:39:40 +0200 (CEST) + id 4B5048493E; Sat, 23 May 2026 18:34:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -1132,14 +1102,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 2F86E845E3 - for ; Tue, 28 Apr 2026 18:39:38 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id 4D28084927 + for ; Sat, 23 May 2026 18:34:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 7987968D09; Tue, 28 Apr 2026 18:39:36 +0200 (CEST) -Subject: [PATCH v2 6/9] pci: brcmstb: Get and use bridge and rescal reset + id E58D768D12; Sat, 23 May 2026 18:34:35 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 6/9] pci: brcmstb: Get and use bridge and rescal reset properties To: Peter Robinson , Matthias Brugger @@ -1162,11 +1134,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163936.7987968D09@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:36 +0200 (CEST) +Message-Id: <20260523163435.E58D768D12@verein.lst.de> +Date: Sat, 23 May 2026 18:34:35 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1191,12 +1161,13 @@ them if so. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato +Reviewed-by: Neil Armstrong --- - drivers/pci/pcie_brcmstb.c | 51 +++++++++++++++++++++++++++++++++++++- - 1 file changed, 50 insertions(+), 1 deletion(-) + drivers/pci/pcie_brcmstb.c | 70 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 65 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 261f8790528..1f97cda5cc7 100644 +index 5cb39dfd136..4d253440de9 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -21,6 +21,7 @@ @@ -1207,7 +1178,7 @@ index 261f8790528..1f97cda5cc7 100644 /* PCIe parameters */ #define BRCM_NUM_PCIE_OUT_WINS 4 -@@ -83,6 +84,8 @@ struct brcm_pcie { +@@ -79,6 +80,8 @@ struct brcm_pcie { int gen; bool ssc; @@ -1216,29 +1187,30 @@ index 261f8790528..1f97cda5cc7 100644 const struct brcm_pcie_cfg_data *pcie_cfg; }; -@@ -147,6 +150,34 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) +@@ -143,14 +146,57 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); } -+static void brcm_pcie_get_resets_dt(struct udevice *dev) -+{ +-static void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) ++static int brcm_pcie_get_resets_dt(struct udevice *dev) + { + struct brcm_pcie *pcie = dev_get_priv(dev); + int ret; + + ret = reset_get_by_name(dev, "rescal", &pcie->rescal); + if (ret) { + printf("Unable to get rescal reset\n"); -+ return; ++ return ret; + } + + ret = reset_get_by_name(dev, "bridge", &pcie->bridge_reset); + if (ret) { + printf("Unable to get bridge reset\n"); -+ return; + } ++ return ret; +} + -+static void brcm_pcie_do_reset(struct udevice *dev) ++static int brcm_pcie_do_reset(struct udevice *dev) +{ + struct brcm_pcie *pcie = dev_get_priv(dev); + int ret; @@ -1246,27 +1218,40 @@ index 261f8790528..1f97cda5cc7 100644 + ret = reset_deassert(&pcie->rescal); + if (ret) + printf("failed to deassert 'rescal'\n"); ++ return ret; +} + - static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) - { ++static int brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) ++{ ++ int ret = 0; ++ ++ if (pcie->bridge_reset.dev) ++ { ++ if (val) ++ ret = reset_assert(&pcie->bridge_reset); ++ else ++ ret = reset_deassert(&pcie->bridge_reset); ++ if (ret) ++ log_err("failed to %sassert bridge reset, err=%d\n", ++ val ? "" : "de", ret); ++ return ret; ++ } if (val) -@@ -157,6 +188,14 @@ static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val + setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], RGR1_SW_INIT_1_INIT_MASK); + else + clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], + RGR1_SW_INIT_1_INIT_MASK); ++ return ret; } -+static void brcm_pcie_bridge_sw_init_set_2712(struct brcm_pcie *pcie, u32 val) -+{ -+ if (val) -+ reset_assert(&pcie->bridge_reset); -+ else -+ reset_deassert(&pcie->bridge_reset); -+} -+ /** - * brcm_pcie_link_up() - Check whether the PCIe link is up - * @pcie: Pointer to the PCIe controller state -@@ -413,6 +452,12 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -405,16 +451,25 @@ static int brcm_pcie_probe(struct udevice *dev) + int num_out_wins = 0; + u64 rc_bar2_offset, rc_bar2_size; + unsigned int scb_size_val; +- int i, ret; ++ int i, ret = 0; u16 nlw, cls, lnksta; u32 tmp; @@ -1274,38 +1259,51 @@ index 261f8790528..1f97cda5cc7 100644 + * Ensure rescal reset for BCM2712 is really disabled. + */ + if (pcie->pcie_cfg->type == BCM2712) -+ brcm_pcie_do_reset(dev); -+ ++ ret = brcm_pcie_do_reset(dev); ++ if (ret) ++ return ret; /* * Reset the bridge, assert the fundamental reset. Note for some SoCs, * e.g. BCM7278, the fundamental reset should not be asserted here. -@@ -611,6 +656,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) + * This will need to be changed when support for other SoCs is added. + */ +- brcm_pcie_bridge_sw_init_set(pcie, 1); ++ ret = brcm_pcie_bridge_sw_init_set(pcie, 1); ++ if (ret) ++ return ret; + if (pcie->pcie_cfg->type != BCM2712) + pcie->pcie_cfg->perst_set(pcie, 1); + /* +@@ -424,8 +479,9 @@ static int brcm_pcie_probe(struct udevice *dev) + udelay(100); + + /* Take the bridge out of reset */ +- brcm_pcie_bridge_sw_init_set(pcie, 0); +- ++ ret = brcm_pcie_bridge_sw_init_set(pcie, 0); ++ if (ret) ++ return ret; + clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], + PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); + +@@ -607,6 +663,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) pcie->gen = max_link_speed; pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); + + if (pcie->pcie_cfg->type == BCM2712) -+ brcm_pcie_get_resets_dt(dev); ++ return brcm_pcie_get_resets_dt(dev); + return 0; } -@@ -645,7 +694,7 @@ static const struct brcm_pcie_cfg_data bcm2712_cfg = { - .offsets = pcie_offsets_bcm2712, - .type = BCM2712, - .perst_set = brcm_pcie_perst_set_2712, -- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, -+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_2712, - .rc_mode = brcm_pcie_rc_mode, - }; - -From patchwork Tue Apr 28 16:39:40 2026 +From patchwork Sat May 23 16:34:38 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229741 +X-Patchwork-Id: 2243370 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org @@ -1319,17 +1317,17 @@ Received: from phobos.denx.de (phobos.denx.de (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mVg1Q52z1yHv - for ; Wed, 29 Apr 2026 02:44:27 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76w469Wz1xx5 + for ; Sun, 24 May 2026 02:35:36 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 25FEE84692; - Tue, 28 Apr 2026 18:43:25 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 4BA1184946; + Sat, 23 May 2026 18:34:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 47298845E3; Tue, 28 Apr 2026 18:39:44 +0200 (CEST) + id 7A0F284912; Sat, 23 May 2026 18:34:41 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -1338,14 +1336,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 7774B84612 - for ; Tue, 28 Apr 2026 18:39:42 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id A63948493E + for ; Sat, 23 May 2026 18:34:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id CE7CB68D0A; Tue, 28 Apr 2026 18:39:40 +0200 (CEST) -Subject: [PATCH v2 7/9] pci: brcmstb: Fix iBAR size calculation + id 6EF7568C4E; Sat, 23 May 2026 18:34:38 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 7/9] pci: brcmstb: Fix iBAR size calculation To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1367,11 +1367,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163940.CE7CB68D0A@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:40 +0200 (CEST) +Message-Id: <20260523163438.6EF7568C4E@verein.lst.de> +Date: Sat, 23 May 2026 18:34:38 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1394,15 +1392,16 @@ Fix inbound window size calculation, like Linux commit 25a98c7270156. Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato +Reviewed-by: Neil Armstrong --- drivers/pci/pcie_brcmstb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 1f97cda5cc7..8a25fb04563 100644 +index 4d253440de9..1022f275dc8 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c -@@ -105,8 +105,8 @@ static int brcm_pcie_encode_ibar_size(u64 size) +@@ -101,8 +101,8 @@ static int brcm_pcie_encode_ibar_size(u64 size) if (log2_in >= 12 && log2_in <= 15) /* Covers 4KB to 32KB (inclusive) */ return (log2_in - 12) + 0x1c; @@ -1414,36 +1413,35 @@ index 1f97cda5cc7..8a25fb04563 100644 /* Something is awry so disable */ -From patchwork Tue Apr 28 16:39:46 2026 +From patchwork Sat May 23 16:34:40 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229742 +X-Patchwork-Id: 2243371 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mVr1fFhz1yHv - for ; Wed, 29 Apr 2026 02:44:36 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN7764HYQz1xx5 + for ; Sun, 24 May 2026 02:35:46 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 5B6528469E; - Tue, 28 Apr 2026 18:43:25 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id CC5608494B; + Sat, 23 May 2026 18:34:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 0F3038464E; Tue, 28 Apr 2026 18:39:50 +0200 (CEST) + id 5BDB084912; Sat, 23 May 2026 18:34:44 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -1452,14 +1450,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id F29FE8460E - for ; Tue, 28 Apr 2026 18:39:47 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id 1783D84931 + for ; Sat, 23 May 2026 18:34:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 42D4368D12; Tue, 28 Apr 2026 18:39:46 +0200 (CEST) -Subject: [PATCH v2 8/9] pci: brcmstb: rework iBAR handling + id A928768CFE; Sat, 23 May 2026 18:34:40 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 8/9] pci: brcmstb: rework iBAR handling To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1481,11 +1481,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163946.42D4368D12@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:46 +0200 (CEST) +Message-Id: <20260523163440.A928768CFE@verein.lst.de> +Date: Sat, 23 May 2026 18:34:40 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1514,12 +1512,13 @@ in one go, so the code is not 1:1 comparable. Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato +Reviewed-by: Neil Armstrong --- drivers/pci/pcie_brcmstb.c | 150 ++++++++++++++++++++++++++++++++----- 1 file changed, 131 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 8a25fb04563..05b80a45b50 100644 +index 1022f275dc8..74d6f2564c2 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -50,6 +50,29 @@ @@ -1551,8 +1550,8 @@ index 8a25fb04563..05b80a45b50 100644 + enum { RGR1_SW_INIT_1, - EXT_CFG_INDEX, -@@ -437,17 +460,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + PCIE_HARD_DEBUG, +@@ -440,17 +463,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); } @@ -1658,10 +1657,10 @@ index 8a25fb04563..05b80a45b50 100644 int num_out_wins = 0; - u64 rc_bar2_offset, rc_bar2_size; - unsigned int scb_size_val; - int i, ret; + int i, ret = 0; u16 nlw, cls, lnksta; u32 tmp; -@@ -488,23 +599,22 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -495,23 +606,22 @@ static int brcm_pcie_probe(struct udevice *dev) MISC_CTRL_CFG_READ_UR_MODE_MASK | MISC_CTRL_MAX_BURST_SIZE_128); @@ -1700,7 +1699,7 @@ index 8a25fb04563..05b80a45b50 100644 writel(tmp, base + PCIE_MISC_MISC_CTRL); /* Disable the PCIe->GISB memory window (RC_BAR1) */ -@@ -521,6 +631,8 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -528,6 +638,8 @@ static int brcm_pcie_probe(struct udevice *dev) /* Clear any interrupts we find on boot */ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); @@ -1710,12 +1709,12 @@ index 8a25fb04563..05b80a45b50 100644 brcm_pcie_set_gen(pcie, pcie->gen); -From patchwork Tue Apr 28 16:39:50 2026 +From patchwork Sat May 23 16:34:43 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2229743 +X-Patchwork-Id: 2243372 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org @@ -1728,17 +1727,17 @@ Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mW16n64z1yHv - for ; Wed, 29 Apr 2026 02:44:45 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN77J1wL6z1xx5 + for ; Sun, 24 May 2026 02:35:56 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 8FC1D846A2; - Tue, 28 Apr 2026 18:43:25 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 14D8F8493A; + Sat, 23 May 2026 18:34:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 3186A84656; Tue, 28 Apr 2026 18:39:54 +0200 (CEST) + id 2F22B8493A; Sat, 23 May 2026 18:34:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -1747,14 +1746,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 3CC6284612 - for ; Tue, 28 Apr 2026 18:39:52 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id DEF5D84912 + for ; Sat, 23 May 2026 18:34:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 9BB2668D09; Tue, 28 Apr 2026 18:39:50 +0200 (CEST) -Subject: [PATCH v2 9/9] pci: brcmstb: Adapt to AXI bridge + id 8B3CA68D0A; Sat, 23 May 2026 18:34:43 +0200 (CEST) +In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> +References: <20260523163239.8EEA768BEB@verein.lst.de> +Subject: [PATCH v4 9/9] pci: brcmstb: Adapt to AXI bridge To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1776,11 +1777,9 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -In-Reply-To: <20260428162319.99B4268B05@verein.lst.de> -Message-Id: <20260428163950.9BB2668D09@verein.lst.de> -Date: Tue, 28 Apr 2026 18:39:50 +0200 (CEST) +Message-Id: <20260523163443.8B3CA68D0A@verein.lst.de> +Date: Sat, 23 May 2026 18:34:43 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) -X-Mailman-Approved-At: Tue, 28 Apr 2026 18:43:21 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list @@ -1807,13 +1806,14 @@ branch. All reworked for the simpler setup code in U-Boot. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato +Reviewed-by: Neil Armstrong --- .../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 + drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -index 6eb5389b858..869482eaffe 100644 +index 5171c593c72..c72b47e1b10 100644 --- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h @@ -54,6 +54,7 @@ @@ -1825,10 +1825,10 @@ index 6eb5389b858..869482eaffe 100644 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 05b80a45b50..f0b0f1cc117 100644 +index 74d6f2564c2..a14efa31734 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c -@@ -551,6 +551,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) +@@ -554,6 +554,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) } } @@ -1859,7 +1859,7 @@ index 05b80a45b50..f0b0f1cc117 100644 static int brcm_pcie_probe(struct udevice *dev) { struct udevice *ctlr = pci_get_controller(dev); -@@ -592,12 +616,27 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -599,12 +623,27 @@ static int brcm_pcie_probe(struct udevice *dev) /* Wait for SerDes to be stable */ udelay(100); @@ -1888,7 +1888,7 @@ index 05b80a45b50..f0b0f1cc117 100644 tmp = readl(base + PCIE_MISC_MISC_CTRL); if (pcie->pcie_cfg->type == BCM2712) { -@@ -617,6 +656,29 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -624,6 +663,29 @@ static int brcm_pcie_probe(struct udevice *dev) } writel(tmp, base + PCIE_MISC_MISC_CTRL); diff --git a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch new file mode 100644 index 0000000..48bad44 --- /dev/null +++ b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch @@ -0,0 +1,215 @@ +From 06179e084181cbbc1e20121dc525621b77733bbc Mon Sep 17 00:00:00 2001 +From: Torsten Duwe +Date: Fri, 8 May 2026 17:42:39 +0200 +Subject: [PATCH 1/3] core: Skip parent device nodes without a DT reference + when looking for dma-ranges + +If a device node got created dynamically, there is no guarantee that the +parent node has an associated device tree node which could specify dma +constraints. Especially PCI(e) enumeration adds intermediate "bus nodes", +also dynamically. + +Try harder to find the correct configuration by walking up the tree until +a DT association is found. + +Suggested-by: Neil Armstrong +Signed-off-by: Torsten Duwe +Reviewed-by: Peter Robinson +Tested-by: Peter Robinson +--- + drivers/core/device.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/drivers/core/device.c b/drivers/core/device.c +index d365204ba11..b6d00cf4714 100644 +--- a/drivers/core/device.c ++++ b/drivers/core/device.c +@@ -459,7 +459,19 @@ static int device_get_dma_constraints(struct udevice *dev) + u64 size = 0; + int ret; + +- if (!CONFIG_IS_ENABLED(DM_DMA) || !parent || !dev_has_ofnode(parent)) ++ if (!CONFIG_IS_ENABLED(DM_DMA) || !parent) ++ return 0; ++ ++ /* Look for the first node in the parent chain */ ++ while (parent) { ++ if (dev_has_ofnode(parent)) ++ break; ++ ++ parent = dev_get_parent(parent); ++ } ++ ++ /* No parents have a node, bail out */ ++ if (!parent) + return 0; + + /* +-- +2.54.0 + +From 38978e38c1246972a318479a1e833d66f06e41be Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 29 May 2026 13:38:27 +0100 +Subject: [PATCH 2/3] nvme: Fix missing address translation for PCIe inbound + access + +U-Boot currently does not account for PCIe bridges with a non-zero +inbound access offset when talking NVMe, it only works on platforms +where this offset happens to be zero. + +This patch enhances the NVMe driver with the ability to also handle +these cases. + +Signed-off-by: Torsten Duwe +Reviewed-by: Peter Robinson +Tested-by: Peter Robinson +Signed-off-by: Peter Robinson +--- + drivers/nvme/nvme.c | 32 ++++++++++++++++++++------------ + 1 file changed, 20 insertions(+), 12 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 0631b190b97..713f2b0b713 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -27,6 +28,13 @@ + #define IO_TIMEOUT 30 + #define MAX_PRP_POOL 512 + ++/* ++ * Convert a memory address to the value needed by the PCI device to ++ * access the given location, taking into account inbound window ++ * translations of PCI bridges: ++ */ ++#define DEV_ADDR(a) dev_phys_to_bus(dev->udev, (a)) ++ + static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) + { + int timeout; +@@ -91,8 +99,8 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + i = 0; + while (nprps) { + if ((i == (prps_per_page - 1)) && nprps > 1) { +- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + +- page_size); ++ *(prp_pool + i) = cpu_to_le64(DEV_ADDR((ulong)prp_pool + ++ page_size)); + i = 0; + prp_pool = (u64 *)((uintptr_t)prp_pool + page_size); + } +@@ -396,8 +404,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) + dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; + + writel(aqa, &dev->bar->aqa); +- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); +- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); ++ nvme_writeq(DEV_ADDR((ulong)nvmeq->sq_cmds), &dev->bar->asq); ++ nvme_writeq(DEV_ADDR((ulong)nvmeq->cqes), &dev->bar->acq); + + result = nvme_enable_ctrl(dev); + if (result) +@@ -423,7 +431,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_cq.opcode = nvme_admin_create_cq; +- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); ++ c.create_cq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->cqes)); + c.create_cq.cqid = cpu_to_le16(qid); + c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_cq.cq_flags = cpu_to_le16(flags); +@@ -440,7 +448,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_sq.opcode = nvme_admin_create_sq; +- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); ++ c.create_sq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->sq_cmds)); + c.create_sq.sqid = cpu_to_le16(qid); + c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_sq.sq_flags = cpu_to_le16(flags); +@@ -461,14 +469,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.identify.opcode = nvme_admin_identify; + c.identify.nsid = cpu_to_le32(nsid); +- c.identify.prp1 = cpu_to_le64(dma_addr); ++ c.identify.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); + + length -= (page_size - offset); + if (length <= 0) { + c.identify.prp2 = 0; + } else { + dma_addr += (page_size - offset); +- c.identify.prp2 = cpu_to_le64(dma_addr); ++ c.identify.prp2 = cpu_to_le64(DEV_ADDR(dma_addr)); + } + + c.identify.cns = cpu_to_le32(cns); +@@ -493,7 +501,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_get_features; + c.features.nsid = cpu_to_le32(nsid); +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + + ret = nvme_submit_admin_cmd(dev, &c, result); +@@ -519,7 +527,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, + + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_set_features; +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); + c.features.fid = cpu_to_le32(fid); + c.features.dword11 = cpu_to_le32(dword11); + +@@ -788,8 +796,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + c.rw.slba = cpu_to_le64(slba); + slba += lbas; + c.rw.length = cpu_to_le16(lbas - 1); +- c.rw.prp1 = cpu_to_le64(temp_buffer); +- c.rw.prp2 = cpu_to_le64(prp2); ++ c.rw.prp1 = cpu_to_le64(DEV_ADDR(temp_buffer)); ++ c.rw.prp2 = cpu_to_le64(DEV_ADDR(prp2)); + status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], + &c, NULL, IO_TIMEOUT); + if (status) +-- +2.54.0 + +From 0e9d37b398f25bcb05525910d515559c9090c0aa Mon Sep 17 00:00:00 2001 +From: Torsten Duwe +Date: Fri, 8 May 2026 17:42:48 +0200 +Subject: [PATCH 3/3] configs: enable NVMe + +Enable NVMe in the Raspberry Pi 64-Bit default config + +Signed-off-by: Torsten Duwe +Reviewed-by: Peter Robinson +Tested-by: Peter Robinson +--- + configs/rpi_arm64_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 69e8e72c5d7..acf44f44fc5 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -41,6 +41,7 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_MMC_SDHCI_BCMSTB=y + CONFIG_BCMGENET=y ++CONFIG_NVME_PCI=y + CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set +-- +2.54.0 + diff --git a/Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch b/Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch new file mode 100644 index 0000000..3e9fce8 --- /dev/null +++ b/Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch @@ -0,0 +1,50 @@ +From 8a88eb4883b16b84ad44db400ee2572966c2dd37 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 29 May 2026 13:11:06 +0100 +Subject: [PATCH] Revert "lmb: Reinstate access to memory above ram_top" + +This reverts commit a3075db94d49f415658bf7e961e1eae90d9abc33. +--- + lib/lmb.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +diff --git a/lib/lmb.c b/lib/lmb.c +index 8f12c6ad8e5..e2d9fe86c14 100644 +--- a/lib/lmb.c ++++ b/lib/lmb.c +@@ -611,6 +611,7 @@ static __maybe_unused void lmb_reserve_common_spl(void) + static void lmb_add_memory(void) + { + int i; ++ phys_addr_t bank_end; + phys_size_t size; + u64 ram_top = gd->ram_top; + struct bd_info *bd = gd->bd; +@@ -624,9 +625,23 @@ static void lmb_add_memory(void) + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + size = bd->bi_dram[i].size; ++ bank_end = bd->bi_dram[i].start + size; + +- if (size) ++ if (size) { + lmb_add(bd->bi_dram[i].start, size); ++ ++ /* ++ * Reserve memory above ram_top as ++ * no-overwrite so that it cannot be ++ * allocated ++ */ ++ if (bd->bi_dram[i].start >= ram_top) ++ lmb_reserve(bd->bi_dram[i].start, size, ++ LMB_NOOVERWRITE); ++ else if (bank_end > ram_top) ++ lmb_reserve(ram_top, bank_end - ram_top, ++ LMB_NOOVERWRITE); ++ } + } + } + +-- +2.54.0 + diff --git a/mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch b/mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch new file mode 100644 index 0000000..ae37019 --- /dev/null +++ b/mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch @@ -0,0 +1,167 @@ +From patchwork Sat May 9 21:06:07 2026 +Content-Type: text/plain; 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+ Sat, 09 May 2026 14:06:44 -0700 (PDT) +Received: from Liel.localdomain ([77.137.77.46]) + by smtp.gmail.com with ESMTPSA id + ffacd0b85a97d-45491f8d4c3sm13600391f8f.34.2026.05.09.14.06.43 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Sat, 09 May 2026 14:06:43 -0700 (PDT) +From: Liel@denx.de, Harel@denx.de, liel.harel@gmail.com +To: u-boot@lists.denx.de +Cc: Liel Harel , Matthias Brugger , + Peter Robinson , Peng Fan , + Jaehoon Chung , Tom Rini +Subject: [PATCH] mmc: bcm2835_sdhci: Parse generic MMC device tree properties +Date: Sun, 10 May 2026 00:06:07 +0300 +Message-ID: <20260509210607.51303-1-liel.harel@gmail.com> +X-Mailer: git-send-email 2.43.0 +MIME-Version: 1.0 +X-Mailman-Approved-At: Sun, 10 May 2026 03:42:13 +0200 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Liel Harel + +The bcm2835 SDHCI driver sets up the MMC host configuration via +sdhci_setup_cfg(), but does not parse generic MMC device tree +properties. + +As a result, properties such as bus-width are ignored. On Raspberry Pi +Compute Module 4, the eMMC node describes an 8-bit bus, but U-Boot +initialized the device as 4-bit. + +Call mmc_of_parse() before sdhci_setup_cfg() so that generic MMC +properties are folded into the host configuration before the MMC core +selects the bus width. + +Before this change, mmc info reported: + + Bus Speed: 52000000 + Bus Width: 4-bit + +After this change, mmc info reports: + + Bus Speed: 52000000 + Bus Width: 8-bit + +Tested on Raspberry Pi Compute Module 4 with onboard eMMC. + +Signed-off-by: Liel Harel +--- + drivers/mmc/bcm2835_sdhci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c +index 655d9902dfa..efa4d14f5da 100644 +--- a/drivers/mmc/bcm2835_sdhci.c ++++ b/drivers/mmc/bcm2835_sdhci.c +@@ -219,6 +219,10 @@ static int bcm2835_sdhci_probe(struct udevice *dev) + host->mmc = &plat->mmc; + host->mmc->dev = dev; + ++ ret = mmc_of_parse(dev, &plat->cfg); ++ if (ret) ++ return ret; ++ + ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ); + if (ret) { + debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret); diff --git a/mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch b/mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch new file mode 100644 index 0000000..bb7d1a9 --- /dev/null +++ b/mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch @@ -0,0 +1,185 @@ +From patchwork Tue May 12 12:24:35 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?b?SmFuIMSMZXJtw6Fr?= +X-Patchwork-Id: 2236827 +X-Patchwork-Delegate: pbrobinson@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (2048-bit key; + secure) header.d=sairon.cz header.i=@sairon.cz header.a=rsa-sha256 + header.s=google header.b=QyEawGu/; + dkim-atps=neutral +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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[89.103.66.201]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-48e8e606020sm18361395e9.5.2026.05.12.05.25.06 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Tue, 12 May 2026 05:25:06 -0700 (PDT) +From: =?utf-8?b?SmFuIMSMZXJtw6Fr?= +To: u-boot@lists.denx.de +Cc: Thomas Fitzsimmons , Peng Fan , + Jaehoon Chung , Tom Rini , + Matthias Brugger , "Ivan T . Ivanov" , + =?utf-8?b?SmFuIMSMZXJtw6Fr?= +Subject: [PATCH] mmc: bcmstb: Fix non-removable check in bcm2712 init +Date: Tue, 12 May 2026 14:24:35 +0200 +Message-ID: <20260512122435.1118557-1-sairon@sairon.cz> +X-Mailer: git-send-email 2.54.0 +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +sdhci_brcmstb_init_2712() reads host->mmc->host_caps to decide whether +to force card-detect for a non-removable eMMC, or to route the CD signal +for a removable SD card. At the time this function runs from +sdhci_bcmstb_probe(), however, host->mmc->host_caps is still zero, that +field is only populated later by the MMC uclass, after the driver's +probe returns. mmc_of_parse() has already filled plat->cfg.host_caps +from the device tree by this point, so check that field instead. + +Without the fix, every BCM2712 SDHCI instance takes the else branch and +writes SDIO_CFG_SD_PIN_SEL = SDIO_CFG_SD_PIN_SEL_CARD (0x02), including +the non-removable eMMC on boards such as CM5 on Home Assistant Yellow. +The SDIO_CFG block lies outside the SDHCI core's reset scope, so this +value persists across SDHCI_RESET_ALL into the next stage. On the +BCM2712, having SD_PIN_SEL set to "SD" when the Linux kernel performs +its first set_power(MMC_POWER_UP) write racily prevents the SDHCI +POWER_ON bit from latching (see [1] for the whole backstory) - the +voltage bits stick but POWER_ON drops - which wedges the first CMD0 the +full 10 s software timeout. On Home Assistant Yellow this manifested as +a ~20 s eMMC probe delay on roughly one in two Linux boots when U-Boot +was the previous stage. Booting directly from the Pi firmware (no U-Boot +in between) left SD_PIN_SEL at its default and did not exhibit the race. + +Reading plat->cfg.host_caps lets init_2712 see the "non-removable" +property and take the correct branch, leaving SD_PIN_SEL untouched for +the eMMC. + +[1] https://github.com/home-assistant/operating-system/pull/3700#issuecomment-4430229511 + +Fixes: 10127cdbab64 ("mmc: bcmstb: Add support for bcm2712 SD controller") +Signed-off-by: Jan Čermák +Reviewed-by: Ivan T. Ivanov +--- + drivers/mmc/bcmstb_sdhci.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c +index 7bddbebb162..f27b84a6ee4 100644 +--- a/drivers/mmc/bcmstb_sdhci.c ++++ b/drivers/mmc/bcmstb_sdhci.c +@@ -56,7 +56,7 @@ struct sdhci_brcmstb_dev_priv { + + static int sdhci_brcmstb_init_2712(struct udevice *dev) + { +- struct sdhci_host *host = dev_get_priv(dev); ++ struct sdhci_bcmstb_plat *plat = dev_get_plat(dev); + void *cfg_regs; + u32 reg; + +@@ -65,8 +65,8 @@ static int sdhci_brcmstb_init_2712(struct udevice *dev) + if (!cfg_regs) + return -ENOENT; + +- if ((host->mmc->host_caps & MMC_CAP_NONREMOVABLE) || +- (host->mmc->host_caps & MMC_CAP_NEEDS_POLL)) { ++ if ((plat->cfg.host_caps & MMC_CAP_NONREMOVABLE) || ++ (plat->cfg.host_caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg = readl(cfg_regs + SDIO_CFG_CTRL); + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; diff --git a/nvme-Fix-missing-inbound-DMA-offset-calculation.patch b/nvme-Fix-missing-inbound-DMA-offset-calculation.patch deleted file mode 100644 index 9731488..0000000 --- a/nvme-Fix-missing-inbound-DMA-offset-calculation.patch +++ /dev/null @@ -1,219 +0,0 @@ -From patchwork Thu Apr 30 14:54:12 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2231306 -X-Patchwork-Delegate: trini@ti.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4g5xyj6V6Pz1xqf - for ; Fri, 01 May 2026 00:54:21 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id E820B80433; - Thu, 30 Apr 2026 16:54:17 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 68D388063E; Thu, 30 Apr 2026 16:54:16 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, - RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham - autolearn_force=no version=3.4.2 -Received: from verein.lst.de (verein.lst.de [213.95.11.211]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id E883980086 - for ; Thu, 30 Apr 2026 16:54:13 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id BC53E68AFE; Thu, 30 Apr 2026 16:54:12 +0200 (CEST) -To: Bin Meng , - Andrew Goodbody , - Tom Rini -Cc: Peter Robinson , - Matthias Brugger , - Andrea della Porta , u-boot@lists.denx.de -Subject: [PATCH] nvme: Fix missing inbound DMA offset calculation -Message-Id: <20260430145412.BC53E68AFE@verein.lst.de> -Date: Thu, 30 Apr 2026 16:54:12 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -U-Boot currently does not account for PCIe bridges with a non-zero -inbound access offset when talking NVMe, it only works on platforms -where this offset happens to be zero. - -This patch enhances the NVMe driver with the ability to also handle -these cases. The fix is required to boot e.g. the Raspberry Pi5 from -NVMe. - -Signed-off-by: Torsten Duwe ---- - -Kudos for the idea of case discrimination go to Andrea; this eases -things a lot. - -I do consider this a bug fix. The problem has popped up during RPi5 -development but really is a generic major defect IMHO. Please apply -wherever appropriate. - - Torsten - ---- - drivers/nvme/nvme.c | 39 ++++++++++++++++++++++++++------------- - 1 file changed, 26 insertions(+), 13 deletions(-) - -diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c -index 2b14437f69c..8056f52fb50 100644 ---- a/drivers/nvme/nvme.c -+++ b/drivers/nvme/nvme.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -27,6 +28,18 @@ - #define IO_TIMEOUT 30 - #define MAX_PRP_POOL 512 - -+/* -+ * This macro detects the correct inbound DMA offset in both cases: -+ * 1) the NVMe is mentioned in the device tree, along with its parent, -+ * and no intermediate PCIe bus node in between. -+ * 2) the NVMe was found dynamically by PCI enumeration which has created -+ * an intermediate PCIe bus node. That node will be skipped and the offset -+ * looked up in the grandparent. -+ */ -+#define DEV_ADDR(a) (dev_has_ofnode(dev->udev) ? \ -+ dev_phys_to_bus(dev->udev, (a)) : \ -+ dev_phys_to_bus(dev->udev->parent, (a))) -+ - static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) - { - int timeout; -@@ -91,12 +104,12 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, - i = 0; - while (nprps) { - if ((i == (prps_per_page - 1)) && nprps > 1) { -- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + -- page_size); -+ *(prp_pool + i) = cpu_to_le64(DEV_ADDR((ulong)prp_pool + -+ page_size)); - i = 0; - prp_pool += page_size; - } -- *(prp_pool + i++) = cpu_to_le64(dma_addr); -+ *(prp_pool + i++) = cpu_to_le64(DEV_ADDR(dma_addr)); - dma_addr += page_size; - nprps--; - } -@@ -393,8 +406,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) - dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; - - writel(aqa, &dev->bar->aqa); -- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); -- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); -+ nvme_writeq(DEV_ADDR((ulong)nvmeq->sq_cmds), &dev->bar->asq); -+ nvme_writeq(DEV_ADDR((ulong)nvmeq->cqes), &dev->bar->acq); - - result = nvme_enable_ctrl(dev); - if (result) -@@ -420,7 +433,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, - - memset(&c, 0, sizeof(c)); - c.create_cq.opcode = nvme_admin_create_cq; -- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); -+ c.create_cq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->cqes)); - c.create_cq.cqid = cpu_to_le16(qid); - c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); - c.create_cq.cq_flags = cpu_to_le16(flags); -@@ -437,7 +450,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, - - memset(&c, 0, sizeof(c)); - c.create_sq.opcode = nvme_admin_create_sq; -- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); -+ c.create_sq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->sq_cmds)); - c.create_sq.sqid = cpu_to_le16(qid); - c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); - c.create_sq.sq_flags = cpu_to_le16(flags); -@@ -458,14 +471,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, - memset(&c, 0, sizeof(c)); - c.identify.opcode = nvme_admin_identify; - c.identify.nsid = cpu_to_le32(nsid); -- c.identify.prp1 = cpu_to_le64(dma_addr); -+ c.identify.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); - - length -= (page_size - offset); - if (length <= 0) { - c.identify.prp2 = 0; - } else { - dma_addr += (page_size - offset); -- c.identify.prp2 = cpu_to_le64(dma_addr); -+ c.identify.prp2 = cpu_to_le64(DEV_ADDR(dma_addr)); - } - - c.identify.cns = cpu_to_le32(cns); -@@ -490,7 +503,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, - memset(&c, 0, sizeof(c)); - c.features.opcode = nvme_admin_get_features; - c.features.nsid = cpu_to_le32(nsid); -- c.features.prp1 = cpu_to_le64(dma_addr); -+ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); - c.features.fid = cpu_to_le32(fid); - - ret = nvme_submit_admin_cmd(dev, &c, result); -@@ -516,7 +529,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, - - memset(&c, 0, sizeof(c)); - c.features.opcode = nvme_admin_set_features; -- c.features.prp1 = cpu_to_le64(dma_addr); -+ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); - c.features.fid = cpu_to_le32(fid); - c.features.dword11 = cpu_to_le32(dword11); - -@@ -785,8 +798,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, - c.rw.slba = cpu_to_le64(slba); - slba += lbas; - c.rw.length = cpu_to_le16(lbas - 1); -- c.rw.prp1 = cpu_to_le64(temp_buffer); -- c.rw.prp2 = cpu_to_le64(prp2); -+ c.rw.prp1 = cpu_to_le64(DEV_ADDR(temp_buffer)); -+ c.rw.prp2 = cpu_to_le64(DEV_ADDR(prp2)); - status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], - &c, NULL, IO_TIMEOUT); - if (status) diff --git a/rockchip-Enable-preboot-start-for-pci-usb.patch b/rockchip-Enable-preboot-start-for-pci-usb.patch index 155c570..30aad4d 100644 --- a/rockchip-Enable-preboot-start-for-pci-usb.patch +++ b/rockchip-Enable-preboot-start-for-pci-usb.patch @@ -1,6 +1,6 @@ -From 020f67a37342b091c74dab93a133253401d4d899 Mon Sep 17 00:00:00 2001 +From a6909a16b4cc301f1007d9e75d02abb6d06a1ea7 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 31 Dec 2024 14:15:41 +0000 +Date: Thu, 28 May 2026 21:29:29 +0100 Subject: [PATCH] rockchip: Enable preboot start for pci/usb Enable the preboot so nvme works OOTB @@ -29,14 +29,18 @@ Signed-off-by: Peter Robinson configs/neu6b-io-rk3588_defconfig | 2 ++ configs/nova-rk3588s_defconfig | 2 ++ configs/odroid-m1-rk3568_defconfig | 2 ++ + configs/odroid-m1s-rk3566_defconfig | 2 ++ + configs/odroid-m2-rk3588s_defconfig | 2 ++ configs/orangepi-3b-rk3566_defconfig | 2 ++ + configs/orangepi-5-max-rk3588_defconfig | 2 ++ configs/orangepi-5-plus-rk3588_defconfig | 2 ++ configs/orangepi-5-rk3588s_defconfig | 2 ++ + configs/orangepi-5-ultra-rk3588_defconfig | 2 ++ configs/pinebook-pro-rk3399_defconfig | 1 + configs/pinetab2-rk3566_defconfig | 2 ++ configs/powkiddy-x55-rk3566_defconfig | 2 ++ configs/quartz64-a-rk3566_defconfig | 2 ++ - configs/quartz64-b-rk3566_defconfig | 2 ++ + configs/quartz64-b-rk3566_defconfig | 4 ++++ configs/quartzpro64-rk3588_defconfig | 2 ++ configs/radxa-cm3-io-rk3566_defconfig | 2 ++ configs/radxa-e25-rk3568_defconfig | 2 ++ @@ -48,6 +52,7 @@ Signed-off-by: Peter Robinson configs/rock-4c-plus-rk3399_defconfig | 2 ++ configs/rock-4se-rk3399_defconfig | 2 ++ configs/rock-5-itx-rk3588_defconfig | 2 ++ + configs/rock-5c-rk3588s_defconfig | 2 ++ configs/rock-pi-4-rk3399_defconfig | 2 ++ configs/rock-pi-4c-rk3399_defconfig | 2 ++ configs/rock-pi-n10-rk3399pro_defconfig | 2 ++ @@ -62,10 +67,10 @@ Signed-off-by: Peter Robinson configs/tiger-rk3588_defconfig | 2 ++ configs/toybrick-rk3588_defconfig | 2 ++ configs/turing-rk1-rk3588_defconfig | 2 ++ - 55 files changed, 109 insertions(+) + 60 files changed, 121 insertions(+) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig -index 14c97b4c5bf..de92e1b4141 100644 +index 854de8b00a4..cd91f18ba80 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -12,6 +12,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -78,7 +83,7 @@ index 14c97b4c5bf..de92e1b4141 100644 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig -index d84ea2f955f..de777817c37 100644 +index c5199a39448..603e07f2456 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -87,11 +92,11 @@ index d84ea2f955f..de777817c37 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/cm3588-nas-rk3588_defconfig b/configs/cm3588-nas-rk3588_defconfig -index fd0a32d6d79..e561be511d4 100644 +index 5b5ef8d5ac1..53147d115dd 100644 --- a/configs/cm3588-nas-rk3588_defconfig +++ b/configs/cm3588-nas-rk3588_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -104,7 +109,7 @@ index fd0a32d6d79..e561be511d4 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig -index ea985b81670..96d7cffb075 100644 +index e6772622403..75e0b373ce9 100644 --- a/configs/coolpi-4b-rk3588s_defconfig +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -113,11 +118,11 @@ index ea985b81670..96d7cffb075 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig -index 58ffe7baf5f..5eadc091242 100644 +index 4326e116849..a005e4441d3 100644 --- a/configs/coolpi-cm5-evb-rk3588_defconfig +++ b/configs/coolpi-cm5-evb-rk3588_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -126,11 +131,11 @@ index 58ffe7baf5f..5eadc091242 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig -index a068bc6846c..8c94f7b21bc 100644 +index 4a5a7454e10..7ec199a08af 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -143,7 +148,7 @@ index a068bc6846c..8c94f7b21bc 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig -index 3d4d2747145..051015fd811 100644 +index c7f6256a626..cfa73c660e7 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -156,7 +161,7 @@ index 3d4d2747145..051015fd811 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig -index 3871627318b..b96aadc78eb 100644 +index 83b9de5feb9..2ba8f5029c3 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -169,7 +174,7 @@ index 3871627318b..b96aadc78eb 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig -index f79f0e84400..ba5339a004f 100644 +index a33c3af9255..20966793568 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -182,7 +187,7 @@ index f79f0e84400..ba5339a004f 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig -index 51e31dce3a9..1c767caa06a 100644 +index ac450e6d757..b5424ac9f16 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -195,7 +200,7 @@ index 51e31dce3a9..1c767caa06a 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig -index 6e853991d1d..a5a56a33d09 100644 +index ed3883b4f9c..47dbd834f30 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -16,6 +16,8 @@ CONFIG_DEBUG_UART_BASE=0xfeb50000 @@ -208,7 +213,7 @@ index 6e853991d1d..a5a56a33d09 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig -index 46cc3c03fff..8915d5bfba9 100644 +index 7548bf60b06..2fb8a432503 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -221,10 +226,10 @@ index 46cc3c03fff..8915d5bfba9 100644 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig -index 26c12c51078..33f7e838c2c 100644 +index f8ae436a1ee..7aa8e1a8d42 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig -@@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 +@@ -15,6 +15,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y @@ -234,7 +239,7 @@ index 26c12c51078..33f7e838c2c 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig -index 772b7df1555..ba6cf48308c 100644 +index ba9a5adece7..eaf7fa5a0fc 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -247,7 +252,7 @@ index 772b7df1555..ba6cf48308c 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig -index 4a43b17ccb1..91c95b491d5 100644 +index e75a24dadc8..159ef033932 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -260,7 +265,7 @@ index 4a43b17ccb1..91c95b491d5 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig -index a60d229fbbf..355d8114a9b 100644 +index c971f376b38..60b5e8fa014 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -273,7 +278,7 @@ index a60d229fbbf..355d8114a9b 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r6c-rk3588s_defconfig b/configs/nanopi-r6c-rk3588s_defconfig -index c4de5518a72..92697c536d9 100644 +index 861e3234d29..bb6e2082e3b 100644 --- a/configs/nanopi-r6c-rk3588s_defconfig +++ b/configs/nanopi-r6c-rk3588s_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -286,7 +291,7 @@ index c4de5518a72..92697c536d9 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nanopi-r6s-rk3588s_defconfig b/configs/nanopi-r6s-rk3588s_defconfig -index 2726729b9ac..63a3690db8e 100644 +index 743dfca441b..903ec56ad6f 100644 --- a/configs/nanopi-r6s-rk3588s_defconfig +++ b/configs/nanopi-r6s-rk3588s_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -299,7 +304,7 @@ index 2726729b9ac..63a3690db8e 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig -index 291e0d26d42..e385aba7bc4 100644 +index 19f129e96f0..08ed699b01d 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -312,7 +317,7 @@ index 291e0d26d42..e385aba7bc4 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig -index 4e22852f23c..79f4e66cb9b 100644 +index 2cf5aeccf51..8cafd779a1c 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -325,7 +330,7 @@ index 4e22852f23c..79f4e66cb9b 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig -index fb30dfd1db8..e99898355e1 100644 +index f7d7492ff46..5abb6ebbe18 100644 --- a/configs/nova-rk3588s_defconfig +++ b/configs/nova-rk3588s_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -338,7 +343,7 @@ index fb30dfd1db8..e99898355e1 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig -index a8e8a8781e1..a3ea2e592b9 100644 +index b00985b0405..19d7af53c7f 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -347,11 +352,37 @@ index a8e8a8781e1..a3ea2e592b9 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig +index d59882a2a59..20f6dc3c26e 100644 +--- a/configs/odroid-m1s-rk3566_defconfig ++++ b/configs/odroid-m1s-rk3566_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/odroid-m2-rk3588s_defconfig b/configs/odroid-m2-rk3588s_defconfig +index e71e61ddb0b..561c2b28b7a 100644 +--- a/configs/odroid-m2-rk3588s_defconfig ++++ b/configs/odroid-m2-rk3588s_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/orangepi-3b-rk3566_defconfig b/configs/orangepi-3b-rk3566_defconfig -index 2181c9caf58..fee0c719f25 100644 +index 1cd78789fa1..dcf182231da 100644 --- a/configs/orangepi-3b-rk3566_defconfig +++ b/configs/orangepi-3b-rk3566_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -360,11 +391,24 @@ index 2181c9caf58..fee0c719f25 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/orangepi-5-max-rk3588_defconfig b/configs/orangepi-5-max-rk3588_defconfig +index 0861df962cf..744aad89c4a 100644 +--- a/configs/orangepi-5-max-rk3588_defconfig ++++ b/configs/orangepi-5-max-rk3588_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig -index 9050fceda45..2e1fe2c6dc5 100644 +index 52523f87aec..e3bb4e43da9 100644 --- a/configs/orangepi-5-plus-rk3588_defconfig +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -373,11 +417,11 @@ index 9050fceda45..2e1fe2c6dc5 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig -index 6e2ff7d338a..7ec7d13e1f9 100644 +index e0eba389289..33fe68add7b 100644 --- a/configs/orangepi-5-rk3588s_defconfig +++ b/configs/orangepi-5-rk3588s_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -386,11 +430,24 @@ index 6e2ff7d338a..7ec7d13e1f9 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/orangepi-5-ultra-rk3588_defconfig b/configs/orangepi-5-ultra-rk3588_defconfig +index fb7f4432983..62419609695 100644 +--- a/configs/orangepi-5-ultra-rk3588_defconfig ++++ b/configs/orangepi-5-ultra-rk3588_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index dfa927ccb17..acc2a0a9fcd 100644 +index cbf95b4692f..9e4d1b1061d 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -22,6 +22,7 @@ CONFIG_PCI=y @@ -402,7 +459,7 @@ index dfa927ccb17..acc2a0a9fcd 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig -index 45e63b42d19..3ef0ddbbe31 100644 +index f284dadb99d..d87849f0a45 100644 --- a/configs/pinetab2-rk3566_defconfig +++ b/configs/pinetab2-rk3566_defconfig @@ -18,6 +18,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -415,7 +472,7 @@ index 45e63b42d19..3ef0ddbbe31 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/powkiddy-x55-rk3566_defconfig b/configs/powkiddy-x55-rk3566_defconfig -index 85280839889..f93a463087b 100644 +index 37a359c91a9..70bc5ab6402 100644 --- a/configs/powkiddy-x55-rk3566_defconfig +++ b/configs/powkiddy-x55-rk3566_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -428,7 +485,7 @@ index 85280839889..f93a463087b 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig -index fe3fa37611a..60b1f8f1784 100644 +index 780fd581f0a..7938b5c0d1b 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -437,24 +494,31 @@ index fe3fa37611a..60b1f8f1784 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig -index 929736f76af..c3155d9b835 100644 +index 4d92a67cd73..fe8a168373d 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig -@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_COUNTER_FREQUENCY=24000000 + CONFIG_ARCH_ROCKCHIP=y +@@ -17,6 +19,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig -index ade7be27e92..263d21bee8b 100644 +index 0ad74e8bbef..b9cbddfae77 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 @@ -463,11 +527,11 @@ index ade7be27e92..263d21bee8b 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig -index 2655fdc3170..c1a27f6e310 100644 +index 875f0b76fa5..2523dccd6a3 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -480,7 +544,7 @@ index 2655fdc3170..c1a27f6e310 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig -index 4df594ddc01..3830d27b264 100644 +index 779d540e22d..7e003e74520 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -489,11 +553,11 @@ index 4df594ddc01..3830d27b264 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/radxa-zero-3-rk3566_defconfig b/configs/radxa-zero-3-rk3566_defconfig -index 5989b07ad79..1b571ec3847 100644 +index f5cf09a5e4a..7db7e3fcd3d 100644 --- a/configs/radxa-zero-3-rk3566_defconfig +++ b/configs/radxa-zero-3-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -506,7 +570,7 @@ index 5989b07ad79..1b571ec3847 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig -index 3ab5fd69c62..ba254d8f6c0 100644 +index 8b4d8c1b0aa..54baa07aeae 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -21,6 +21,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -519,7 +583,7 @@ index 3ab5fd69c62..ba254d8f6c0 100644 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig -index 733ce631457..3387796a0c5 100644 +index e753185610f..19d303e7f70 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -528,11 +592,11 @@ index 733ce631457..3387796a0c5 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-3b-rk3568_defconfig b/configs/rock-3b-rk3568_defconfig -index 2023feb36c2..84c6aab6b33 100644 +index c3bf48b9e34..0cfa8eba168 100644 --- a/configs/rock-3b-rk3568_defconfig +++ b/configs/rock-3b-rk3568_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -541,11 +605,11 @@ index 2023feb36c2..84c6aab6b33 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig -index 2528c7c639c..0a0010b1268 100644 +index 417aa33a663..61d0e1b8c6a 100644 --- a/configs/rock-3c-rk3566_defconfig +++ b/configs/rock-3c-rk3566_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -554,11 +618,11 @@ index 2528c7c639c..0a0010b1268 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig -index 0c73a212ea1..2ae2eff39e2 100644 +index 0f6bdfdfb06..f31cb061a83 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -571,7 +635,7 @@ index 0c73a212ea1..2ae2eff39e2 100644 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig -index 3ae19692155..12621b8a41b 100644 +index 7f22aede912..caf8e02bece 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -580,11 +644,11 @@ index 3ae19692155..12621b8a41b 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y + # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig -index d0dd1c20ece..b3a778907c8 100644 +index cb014de4188..e26a126533c 100644 --- a/configs/rock-5-itx-rk3588_defconfig +++ b/configs/rock-5-itx-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -593,11 +657,24 @@ index d0dd1c20ece..b3a778907c8 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig +index 3d044a81498..27234c250d1 100644 +--- a/configs/rock-5c-rk3588s_defconfig ++++ b/configs/rock-5c-rk3588s_defconfig +@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig -index f3a5c2c45f3..d95576e804a 100644 +index e5c9072c27f..35852c017da 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -606,11 +683,11 @@ index f3a5c2c45f3..d95576e804a 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y + # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig -index 9bda50c8c77..d26eb3dcb44 100644 +index 4be7b0f8130..eeee446a5bd 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -619,11 +696,11 @@ index 9bda50c8c77..d26eb3dcb44 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y + # CONFIG_ANDROID_BOOT_IMAGE is not set diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig -index a9c6d8a907a..1cde3859eef 100644 +index 602a723ea7d..3dcc2932ae3 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -13,6 +13,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -636,7 +713,7 @@ index a9c6d8a907a..1cde3859eef 100644 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig -index 9618d590009..9608f7e7e4c 100644 +index 24b2eef35f2..c5830054921 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -649,7 +726,7 @@ index 9618d590009..9608f7e7e4c 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig -index 47ee2109f8e..e1c6961a3ab 100644 +index da5fb3a2c30..053346fc035 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -658,11 +735,11 @@ index 47ee2109f8e..e1c6961a3ab 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -index aebfa73459c..8b60ad3bf00 100644 +index db121f03ae6..e55f1b6a034 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -675,7 +752,7 @@ index aebfa73459c..8b60ad3bf00 100644 CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig -index 08b7e2784e9..d80e120c66f 100644 +index 1d2bff35fc0..ea8e90b9f6a 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -688,7 +765,7 @@ index 08b7e2784e9..d80e120c66f 100644 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig -index 8b033e22b84..978df10442c 100644 +index 00b9759715b..1b837bd554c 100644 --- a/configs/sige7-rk3588_defconfig +++ b/configs/sige7-rk3588_defconfig @@ -13,6 +13,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -697,11 +774,11 @@ index 8b033e22b84..978df10442c 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig -index a1a51b2c657..4083f217c0b 100644 +index 7de159a8881..4137f0459b5 100644 --- a/configs/soquartz-blade-rk3566_defconfig +++ b/configs/soquartz-blade-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -710,11 +787,11 @@ index a1a51b2c657..4083f217c0b 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig -index a8bca0eaccc..c3dd48d9dc1 100644 +index 4455ee5b5aa..ad63ba0204f 100644 --- a/configs/soquartz-cm4-rk3566_defconfig +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -723,11 +800,11 @@ index a8bca0eaccc..c3dd48d9dc1 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig -index f080d2e36d2..f6f2f67b0a6 100644 +index abdab514496..9e01345bdaa 100644 --- a/configs/soquartz-model-a-rk3566_defconfig +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -736,11 +813,11 @@ index f080d2e36d2..f6f2f67b0a6 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig -index f962ac416f3..1fc7301f6ae 100644 +index 105e8e10e0b..bcc2ae302a5 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 @@ -753,7 +830,7 @@ index f962ac416f3..1fc7301f6ae 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig -index 5e70341c987..fd7e842f9e5 100644 +index 14b231ae3e2..7af393731cd 100644 --- a/configs/toybrick-rk3588_defconfig +++ b/configs/toybrick-rk3588_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 @@ -766,7 +843,7 @@ index 5e70341c987..fd7e842f9e5 100644 CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig -index 0eddf15833c..1a9aacc7b5d 100644 +index 0b3efec23e6..515db2a2b0c 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEBC0000 @@ -775,9 +852,9 @@ index 0eddf15833c..1a9aacc7b5d 100644 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y -- -2.47.1 +2.54.0 diff --git a/rpi-enable-nvme.patch b/rpi-enable-nvme.patch index c5a2ff1..52a1153 100644 --- a/rpi-enable-nvme.patch +++ b/rpi-enable-nvme.patch @@ -21,14 +21,6 @@ index 38af5029403..ed4ae6ff522 100644 CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -@@ -41,6 +41,7 @@ CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_MMC_SDHCI_BCMSTB=y - CONFIG_BCMGENET=y -+CONFIG_NVME_PCI=y - CONFIG_PCI_BRCMSTB=y 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5b1f17b1804b1-488ffc5e3f4sm181160215e9.2.2026.04.21.07.11.59 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Tue, 21 Apr 2026 07:11:59 -0700 (PDT) +From: Peter Robinson +To: Matthias Brugger , + u-boot@lists.denx.de +Cc: Peter Robinson +Subject: [PATCH] rpi_arm64: Enable MBEDTLS/LWIP/WGET and WGET_HTTPS +Date: Tue, 21 Apr 2026 15:11:38 +0100 +Message-ID: <20260421141156.359690-1-pbrobinson@gmail.com> +X-Mailer: git-send-email 2.53.0 +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +Enable LWIP and HTTPS on the Raspberry Pi arm64 platform to be able to +use it in the boot process. + +Signed-off-by: Peter Robinson +Reviewed-by: Matthias Brugger +--- + configs/rpi_arm64_defconfig | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 69e8e72c5d7..90048a418f6 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -11,6 +11,7 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_PCI=y + CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y + CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y ++CONFIG_EFI_HTTP_BOOT=y + CONFIG_BOOTSTD_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_FDT_SIMPLEFB=y +@@ -26,11 +27,13 @@ CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y ++CONFIG_CMD_SNTP=y ++CONFIG_WGET_HTTPS=y + CONFIG_CMD_EFIDEBUG=y + CONFIG_CMD_FS_UUID=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +-CONFIG_TFTP_TSIZE=y ++CONFIG_NET_LWIP=y + CONFIG_DM_DMA=y + CONFIG_DFU_MMC=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +@@ -64,4 +67,5 @@ CONFIG_SYS_WHITE_ON_BLACK=y + CONFIG_VIDEO_BCM2835=y + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y ++CONFIG_MBEDTLS_LIB=y + # CONFIG_HEXDUMP is not set diff --git a/sources b/sources index 5a8707a..9208a63 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.07-rc1.tar.bz2) = 9e926fdea78c02c81ebe79383623ec34af78debee3dcb35a7b1968646cd3b296768e2acbb29ccf93b92031905761be4424241dabc01ee16202e1efb47c9589eb +SHA512 (u-boot-2026.07-rc3.tar.bz2) = 1aef3d2c5c773244bbc3eb8f63543e84aa5a127c3dd58dabbb2714473f8233d299e610ddeb4e18f6c7b012ca8f3152688bc0ae3fcebc0867a7a7fae43018192d diff --git a/uboot-tools.spec b/uboot-tools.spec index f589fb8..6c1de18 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc1 +%global candidate rc3 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,12 +10,12 @@ Name: uboot-tools Version: 2026.07 -Release: 0.1%{?candidate:.%{candidate}}%{?dist} +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. License: GPL-2.0-or-later AND LicenseRef-Callaway-BSD AND LGPL-2.1-or-later AND LGPL-2.0-or-later -URL: http://www.denx.de/wiki/U-Boot +URL: https://u-boot-project.org/ ExcludeArch: s390x Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: aarch64-boards @@ -29,14 +29,14 @@ Patch2: enable-bootmenu-by-default.patch Patch3: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch # Identify VFAT partitions as ESP, allows EFI setvar on our images Patch4: uefi-Add-all-options-for-EFI-System-Partitions.patch -# Upstream revert for rpi boot fix -Patch5: 0001-Revert-efi_loader-install-device-tree-on-configurati.patch # New function to find fdt for loading from disk -Patch6: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch +Patch5: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch # Enable UEFI SetVariable for devices without backed storage -Patch7: uefi-enable-SetVariableRT-with-volotile-storage.patch +Patch6: uefi-enable-SetVariableRT-with-volotile-storage.patch # Enable UEFI HTTPS boot for all Fedora firmware -Patch8: uefi-enable-https-boot-by-default.patch +Patch7: uefi-enable-https-boot-by-default.patch +# Upstream revert to fix boot on RPi +Patch8: Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch # Device improvments # USB-PD improvements @@ -51,11 +51,14 @@ Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch # Fix AllWinner Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi -Patch20: ARM-RPi5-Enable-PCIe.patch -Patch21: nvme-Fix-missing-inbound-DMA-offset-calculation.patch +Patch20: Fix-NVMe-not-only-on-Raspberry-Pi-5.patch +Patch21: ARM-RPi5-Enable-PCIe.patch Patch22: rpi-enable-nvme.patch -Patch23: 0001-Add-bcm2712-compat.patch +Patch23: video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch Patch24: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch +Patch25: mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch +Patch26: rpi_arm64-Enable-MBEDTLS-LWIP-WGET-and-WGET_HTTPS.patch +Patch27: mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch BuildRequires: bc BuildRequires: bison @@ -314,6 +317,12 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Fri May 29 2026 Peter Robinson - 1:2026.07-0.2.rc3 +- Update to 2026.07 RC3 +- Update U-Boot Project URL +- Update RPi PCIe patches +- Various RPi fixes + * Fri May 01 2026 Peter Robinson - 1:2026.07-0.1.rc1 - Update to 2026.07 RC1 diff --git a/uefi-enable-https-boot-by-default.patch b/uefi-enable-https-boot-by-default.patch index c584f9b..dc0a683 100644 --- a/uefi-enable-https-boot-by-default.patch +++ b/uefi-enable-https-boot-by-default.patch @@ -1,4 +1,4 @@ -From 4e6c3762cc86f6fab6f18ffd2a99ff921cd0fd38 Mon Sep 17 00:00:00 2001 +From 7eabab2fda12b7a4417e5c7f29a507dfa9e7fffd Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 3 May 2026 09:24:34 +0100 Subject: [PATCH] enable https boot by default @@ -24,7 +24,7 @@ index c71c6824a19..8ff14adffe1 100644 depends on PROT_TCP_LWIP depends on MBEDTLS_LIB diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig -index 0b6c2eaac60..268d9eb8544 100644 +index 4cb13ae7c8a..20733429962 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -609,6 +609,7 @@ config EFI_BOOTMGR @@ -33,8 +33,8 @@ index 0b6c2eaac60..268d9eb8544 100644 bool "EFI HTTP Boot support" + default y depends on NET + depends on CMDLINE select CMD_NET - select CMD_DHCP diff --git a/lib/mbedtls/Kconfig b/lib/mbedtls/Kconfig index 789721ee6cd..7a241c2bc26 100644 --- a/lib/mbedtls/Kconfig diff --git a/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch index 0a1727a..5948f93 100644 --- a/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch +++ b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch @@ -1,6 +1,6 @@ -From 121fd475757e183428ca78f43420c42b9973aa33 Mon Sep 17 00:00:00 2001 +From 56a985cec8592a8de88e7f254df82f5d444a5ecc Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 31 Dec 2024 14:11:12 +0000 +Date: Thu, 28 May 2026 22:08:07 +0100 Subject: [PATCH] initial find_fdt_location for finding the DT on disk The old distro boot looked for a DT on the first boot partition @@ -18,14 +18,14 @@ Signed-off-by: Peter Robinson --- cmd/bootmenu.c | 5 ++ include/efi_loader.h | 2 + - lib/efi_loader/efi_helper.c | 105 +++++++++++++++++++++++++++++++++++- - 4 files changed, 112 insertions(+), 1 deletion(-) + lib/efi_loader/efi_helper.c | 106 +++++++++++++++++++++++++++++++++++- + 3 files changed, 112 insertions(+), 1 deletion(-) diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c -index b633aedf011..96a71a96820 100644 +index 528afd221d0..a10ea35a687 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c -@@ -461,6 +461,11 @@ static void handle_uefi_bootnext(void) +@@ -502,6 +502,11 @@ static void handle_uefi_bootnext(void) u16 bootnext; efi_status_t ret; efi_uintn_t size; @@ -38,10 +38,10 @@ index b633aedf011..96a71a96820 100644 /* Initialize EFI drivers */ ret = efi_init_obj_list(); diff --git a/include/efi_loader.h b/include/efi_loader.h -index 39809eac1bc..511eba655e7 100644 +index 3a4d502631c..b11f8a2cb42 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h -@@ -514,6 +514,8 @@ struct efi_register_notify_event { +@@ -574,6 +574,8 @@ struct efi_register_notify_event { struct list_head handles; }; @@ -51,10 +51,10 @@ index 39809eac1bc..511eba655e7 100644 int efi_init_early(void); /* Initialize efi execution environment */ diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c -index bf96f61d3d0..3f496cc0dfb 100644 +index 44b806aadc4..61e982091b9 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c -@@ -12,6 +12,7 @@ +@@ -15,6 +15,7 @@ #include #include #include @@ -62,7 +62,7 @@ index bf96f61d3d0..3f496cc0dfb 100644 #include #include #include -@@ -95,6 +96,99 @@ int efi_get_pxe_arch(void) +@@ -98,6 +99,99 @@ int efi_get_pxe_arch(void) return -EINVAL; } @@ -162,14 +162,15 @@ index bf96f61d3d0..3f496cc0dfb 100644 /** * efi_create_current_boot_var() - Return Boot#### name were #### is replaced by * the value of BootCurrent -@@ -548,11 +642,20 @@ efi_status_t efi_install_fdt(void *fdt) - /* Look for device tree that is already installed */ - if (efi_get_configuration_table(&efi_guid_fdt)) - return EFI_SUCCESS; +@@ -558,11 +652,21 @@ efi_status_t efi_install_fdt(void *fdt) + const char *fdt_opt; + uintptr_t fdt_addr; + + /* Check if there is device tree loaded from disk */ + fdt_opt = find_fdt_location(); + if (fdt_opt) + log_debug("Found DTB on disk\n"); ++ /* Check if there is a hardware device tree */ - fdt_opt = env_get("fdt_addr"); + if (!fdt_opt) { @@ -185,5 +186,5 @@ index bf96f61d3d0..3f496cc0dfb 100644 log_err("need device tree\n"); return EFI_NOT_FOUND; -- -2.47.1 +2.54.0 diff --git a/video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch b/video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch new file mode 100644 index 0000000..f1fed33 --- /dev/null +++ b/video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch @@ -0,0 +1,152 @@ +From patchwork Tue Apr 21 08:51:59 2026 +Content-Type: text/plain; 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+ Tue, 21 Apr 2026 01:52:10 -0700 (PDT) +Received: from cypher.home.roving-it.com + (7.9.7.f.b.1.3.0.b.8.f.0.9.e.0.0.1.8.6.2.1.1.b.f.0.b.8.0.1.0.0.2.ip6.arpa. + [2001:8b0:fb11:2681:e9:f8b:31b:f797]) + by smtp.googlemail.com with ESMTPSA id + 5b1f17b1804b1-488fc18bccfsm319754095e9.8.2026.04.21.01.52.09 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Tue, 21 Apr 2026 01:52:09 -0700 (PDT) +From: Peter Robinson +To: Matthias Brugger , + u-boot@lists.denx.de +Cc: Peter Robinson +Subject: [PATCH] video: arm: rpi: Add brcm,bcm2712-hdmi0 compatible +Date: Tue, 21 Apr 2026 09:51:59 +0100 +Message-ID: <20260421085207.273703-1-pbrobinson@gmail.com> +X-Mailer: git-send-email 2.53.0 +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The 'brcm,bcm2712-hdmi0' compatible string is used on RPi5. +There appears to be no change that impacts early boot output +on the display controller so add the RPi5 compatible string. + +Signed-off-by: Peter Robinson +Reviewed-by: Matthias Brugger +--- + drivers/video/bcm2835.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c +index 0c81e606622..0e0cc1979eb 100644 +--- a/drivers/video/bcm2835.c ++++ b/drivers/video/bcm2835.c +@@ -66,6 +66,7 @@ static int bcm2835_video_probe(struct udevice *dev) + static const struct udevice_id bcm2835_video_ids[] = { + { .compatible = "brcm,bcm2835-hdmi" }, + { .compatible = "brcm,bcm2711-hdmi0" }, ++ { .compatible = "brcm,bcm2712-hdmi0" }, + { .compatible = "brcm,bcm2708-fb" }, + #if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB) + { .compatible = "simple-framebuffer" }, From 7131d07d8690764d5b941d12c0e16102886fa33e Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 3 Jun 2026 12:31:56 +0100 Subject: [PATCH 27/38] Update brcmstb pcie patch --- ARM-RPi5-Enable-PCIe.patch | 354 +++++++++++++++++++------------------ 1 file changed, 178 insertions(+), 176 deletions(-) diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch index f86ae64..db052eb 100644 --- a/ARM-RPi5-Enable-PCIe.patch +++ b/ARM-RPi5-Enable-PCIe.patch @@ -1,32 +1,33 @@ -From patchwork Sat May 23 16:34:24 2026 +From patchwork Mon Jun 1 10:39:20 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243363 +X-Patchwork-Id: 2247313 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN75k43NLz1xx5 - for ; Sun, 24 May 2026 02:34:34 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVny5cjnz1yCV + for ; Mon, 01 Jun 2026 20:39:34 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id DA6A1848D1; - Sat, 23 May 2026 18:34:30 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 24CA484884; + Mon, 1 Jun 2026 12:39:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id AA584848B6; Sat, 23 May 2026 18:34:28 +0200 (CEST) + id 0DE0984881; Mon, 1 Jun 2026 12:39:25 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -35,16 +36,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id B859684659 - for ; Sat, 23 May 2026 18:34:26 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id 371C384878 + for ; Mon, 1 Jun 2026 12:39:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id B4EE268BEB; Sat, 23 May 2026 18:34:24 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window + id 1371668BEB; Mon, 1 Jun 2026 12:39:20 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -66,8 +67,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163424.B4EE268BEB@verein.lst.de> -Date: Sat, 23 May 2026 18:34:24 +0200 (CEST) +Message-Id: <20260601103920.1371668BEB@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:20 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -128,36 +129,35 @@ index 7a1de22e0ae..7a2faaa4de6 100644 /* SoC bus */ .virt = 0x107c000000UL, -From patchwork Sat May 23 16:34:26 2026 +From patchwork Mon Jun 1 10:39:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243364 +X-Patchwork-Id: 2247314 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) + key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN75r2nngz1xx5 - for ; Sun, 24 May 2026 02:34:40 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVnz6yLbz1yDm + for ; Mon, 01 Jun 2026 20:39:35 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 2890A848BF; - Sat, 23 May 2026 18:34:33 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 5BC4C8487C; + Mon, 1 Jun 2026 12:39:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 3969B848F3; Sat, 23 May 2026 18:34:31 +0200 (CEST) + id 913B184894; Mon, 1 Jun 2026 12:39:27 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -166,16 +166,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id C0D4A84659 - for ; Sat, 23 May 2026 18:34:28 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id BD0EB8487C + for ; Mon, 1 Jun 2026 12:39:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id BDC5168C7B; Sat, 23 May 2026 18:34:26 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 2/9] pci: brcmstb: Fix PCIe bus numbers + id 30A1F68C4E; Mon, 1 Jun 2026 12:39:23 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 2/9] pci: brcmstb: Fix PCIe bus numbers To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -197,8 +197,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163426.BDC5168C7B@verein.lst.de> -Date: Sat, 23 May 2026 18:34:26 +0200 (CEST) +Message-Id: <20260601103923.30A1F68C4E@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:23 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -249,35 +249,36 @@ index f089c48f028..47c0802df23 100644 unsigned int pci_func = PCI_FUNC(bdf); int idx; -From patchwork Sat May 23 16:34:28 2026 +From patchwork Mon Jun 1 10:39:25 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243366 +X-Patchwork-Id: 2247315 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN7614lMDz1xx5 - for ; Sun, 24 May 2026 02:34:49 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVp75WJXz1yCV + for ; Mon, 01 Jun 2026 20:39:43 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 63143848A4; - Sat, 23 May 2026 18:34:35 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 8D7F484881; + Mon, 1 Jun 2026 12:39:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 99621848A4; Sat, 23 May 2026 18:34:32 +0200 (CEST) + id 34B298489E; Mon, 1 Jun 2026 12:39:29 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -286,16 +287,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 8BD35848B6 - for ; Sat, 23 May 2026 18:34:30 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id 2B8088488A + for ; Mon, 1 Jun 2026 12:39:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id C612768D05; Sat, 23 May 2026 18:34:28 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 3/9] pci: brcmstb: Support different variants using a cfg + id 6B2FE68C7B; Mon, 1 Jun 2026 12:39:25 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 3/9] pci: brcmstb: Support different variants using a cfg struct To: Peter Robinson , Matthias Brugger @@ -318,8 +319,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163428.C612768D05@verein.lst.de> -Date: Sat, 23 May 2026 18:34:28 +0200 (CEST) +Message-Id: <20260601103925.6B2FE68C7B@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:25 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -556,12 +557,12 @@ index 47c0802df23..5cb39dfd136 100644 }; -From patchwork Sat May 23 16:34:30 2026 +From patchwork Mon Jun 1 10:39:27 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243367 +X-Patchwork-Id: 2247316 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org @@ -575,17 +576,17 @@ Received: from phobos.denx.de (phobos.denx.de (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76L65v2z1xx5 - for ; Sun, 24 May 2026 02:35:06 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVpJ3NjHz1yCV + for ; Mon, 01 Jun 2026 20:39:52 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 896D584932; - Sat, 23 May 2026 18:34:37 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id C82428489D; + Mon, 1 Jun 2026 12:39:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id E440884913; Sat, 23 May 2026 18:34:34 +0200 (CEST) + id EB978848A2; Mon, 1 Jun 2026 12:39:30 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -594,16 +595,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 5696584659 - for ; Sat, 23 May 2026 18:34:32 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id F11D784898 + for ; Mon, 1 Jun 2026 12:39:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id DA8E768D09; Sat, 23 May 2026 18:34:30 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 4/9] reset: Add RPi5 brcmstb reset facilities + id 7616B68D05; Mon, 1 Jun 2026 12:39:27 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 4/9] reset: Add RPi5 brcmstb reset facilities To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -625,8 +626,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163430.DA8E768D09@verein.lst.de> -Date: Sat, 23 May 2026 18:34:30 +0200 (CEST) +Message-Id: <20260601103927.7616B68D05@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:27 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -807,36 +808,35 @@ index 00000000000..7861f7c9baf + .priv_auto = sizeof(struct brcmstb_reset), +}; -From patchwork Sat May 23 16:34:33 2026 +From patchwork Mon Jun 1 10:39:29 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243368 +X-Patchwork-Id: 2247317 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76Y28Xyz1xx5 - for ; Sun, 24 May 2026 02:35:17 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVpT3Zvdz1yCV + for ; Mon, 01 Jun 2026 20:40:01 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id C8E4B8493F; - Sat, 23 May 2026 18:34:39 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 0947E848A1; + Mon, 1 Jun 2026 12:39:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 79B8A8491C; Sat, 23 May 2026 18:34:36 +0200 (CEST) + id B273384878; Mon, 1 Jun 2026 12:39:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -845,16 +845,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 81EC68490A - for ; Sat, 23 May 2026 18:34:34 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id C0E1D8489E + for ; Mon, 1 Jun 2026 12:39:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 3B46568D0D; Sat, 23 May 2026 18:34:33 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 5/9] reset: Add RPi5 rescal reset facilities + id 751D668D09; Mon, 1 Jun 2026 12:39:29 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 5/9] reset: Add RPi5 rescal reset facilities To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -876,8 +876,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163433.3B46568D0D@verein.lst.de> -Date: Sat, 23 May 2026 18:34:33 +0200 (CEST) +Message-Id: <20260601103929.751D668D09@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:29 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -1064,36 +1064,35 @@ index 00000000000..fc8fcfa8b3f + .priv_auto = sizeof(struct brcm_rescal_reset), +}; -From patchwork Sat May 23 16:34:35 2026 +From patchwork Mon Jun 1 10:39:31 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243369 +X-Patchwork-Id: 2247318 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76l00M8z1xx5 - for ; Sun, 24 May 2026 02:35:26 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVph2NvWz1yDY + for ; Mon, 01 Jun 2026 20:40:12 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 100FA84922; - Sat, 23 May 2026 18:34:42 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 3C481848B9; + Mon, 1 Jun 2026 12:39:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 4B5048493E; Sat, 23 May 2026 18:34:39 +0200 (CEST) + id 33481848B4; Mon, 1 Jun 2026 12:39:35 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -1102,16 +1101,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 4D28084927 - for ; Sat, 23 May 2026 18:34:37 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id 39C6584878 + for ; Mon, 1 Jun 2026 12:39:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id E58D768D12; Sat, 23 May 2026 18:34:35 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 6/9] pci: brcmstb: Get and use bridge and rescal reset + id BD8CC68D0D; Mon, 1 Jun 2026 12:39:31 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 6/9] pci: brcmstb: Get and use bridge and rescal reset properties To: Peter Robinson , Matthias Brugger @@ -1134,8 +1133,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163435.E58D768D12@verein.lst.de> -Date: Sat, 23 May 2026 18:34:35 +0200 (CEST) +Message-Id: <20260601103931.BD8CC68D0D@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:31 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -1163,11 +1162,11 @@ Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato Reviewed-by: Neil Armstrong --- - drivers/pci/pcie_brcmstb.c | 70 +++++++++++++++++++++++++++++++++++--- - 1 file changed, 65 insertions(+), 5 deletions(-) + drivers/pci/pcie_brcmstb.c | 71 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 66 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 5cb39dfd136..4d253440de9 100644 +index 5cb39dfd136..012b501078a 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -21,6 +21,7 @@ @@ -1187,7 +1186,7 @@ index 5cb39dfd136..4d253440de9 100644 const struct brcm_pcie_cfg_data *pcie_cfg; }; -@@ -143,14 +146,57 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) +@@ -143,14 +146,58 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); } @@ -1204,9 +1203,9 @@ index 5cb39dfd136..4d253440de9 100644 + } + + ret = reset_get_by_name(dev, "bridge", &pcie->bridge_reset); -+ if (ret) { ++ if (ret) + printf("Unable to get bridge reset\n"); -+ } ++ + return ret; +} + @@ -1225,7 +1224,7 @@ index 5cb39dfd136..4d253440de9 100644 +{ + int ret = 0; + -+ if (pcie->bridge_reset.dev) ++ if (reset_valid(&pcie->bridge_reset)) + { + if (val) + ret = reset_assert(&pcie->bridge_reset); @@ -1236,17 +1235,18 @@ index 5cb39dfd136..4d253440de9 100644 + val ? "" : "de", ret); + return ret; + } ++ if (val) setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], RGR1_SW_INIT_1_INIT_MASK); else clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], RGR1_SW_INIT_1_INIT_MASK); -+ return ret; ++ return 0; } /** -@@ -405,16 +451,25 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -405,16 +452,25 @@ static int brcm_pcie_probe(struct udevice *dev) int num_out_wins = 0; u64 rc_bar2_offset, rc_bar2_size; unsigned int scb_size_val; @@ -1274,7 +1274,7 @@ index 5cb39dfd136..4d253440de9 100644 if (pcie->pcie_cfg->type != BCM2712) pcie->pcie_cfg->perst_set(pcie, 1); /* -@@ -424,8 +479,9 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -424,8 +480,9 @@ static int brcm_pcie_probe(struct udevice *dev) udelay(100); /* Take the bridge out of reset */ @@ -1286,7 +1286,7 @@ index 5cb39dfd136..4d253440de9 100644 clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); -@@ -607,6 +663,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) +@@ -607,6 +664,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) pcie->gen = max_link_speed; pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); @@ -1298,12 +1298,12 @@ index 5cb39dfd136..4d253440de9 100644 } -From patchwork Sat May 23 16:34:38 2026 +From patchwork Mon Jun 1 10:39:34 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243370 +X-Patchwork-Id: 2247319 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org @@ -1317,17 +1317,17 @@ Received: from phobos.denx.de (phobos.denx.de (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN76w469Wz1xx5 - for ; Sun, 24 May 2026 02:35:36 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVpv2npJz1yDY + for ; Mon, 01 Jun 2026 20:40:23 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 4BA1184946; - Sat, 23 May 2026 18:34:42 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 4CB0084898; + Mon, 1 Jun 2026 12:39:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 7A0F284912; Sat, 23 May 2026 18:34:41 +0200 (CEST) + id 0F793848B0; Mon, 1 Jun 2026 12:39:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -1336,16 +1336,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id A63948493E - for ; Sat, 23 May 2026 18:34:39 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id BFE818489E + for ; Mon, 1 Jun 2026 12:39:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id 6EF7568C4E; Sat, 23 May 2026 18:34:38 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 7/9] pci: brcmstb: Fix iBAR size calculation + id 5B8CC68D0E; Mon, 1 Jun 2026 12:39:34 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 7/9] pci: brcmstb: Fix iBAR size calculation To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1367,8 +1367,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163438.6EF7568C4E@verein.lst.de> -Date: Sat, 23 May 2026 18:34:38 +0200 (CEST) +Message-Id: <20260601103934.5B8CC68D0E@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:34 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -1392,13 +1392,13 @@ Fix inbound window size calculation, like Linux commit 25a98c7270156. Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong +Reviewed-by: Neil Armstrong --- drivers/pci/pcie_brcmstb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 4d253440de9..1022f275dc8 100644 +index 012b501078a..164d8e2b7fe 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -101,8 +101,8 @@ static int brcm_pcie_encode_ibar_size(u64 size) @@ -1413,35 +1413,36 @@ index 4d253440de9..1022f275dc8 100644 /* Something is awry so disable */ -From patchwork Sat May 23 16:34:40 2026 +From patchwork Mon Jun 1 10:39:36 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243371 +X-Patchwork-Id: 2247320 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gN7764HYQz1xx5 - for ; Sun, 24 May 2026 02:35:46 +1000 (AEST) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVq615M9z1yDY + for ; Mon, 01 Jun 2026 20:40:34 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id CC5608494B; - Sat, 23 May 2026 18:34:45 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTP id 845E4848C5; + Mon, 1 Jun 2026 12:39:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) - id 5BDB084912; Sat, 23 May 2026 18:34:44 +0200 (CEST) + id 098BD848B4; Mon, 1 Jun 2026 12:39:40 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, @@ -1450,16 +1451,16 @@ X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 1783D84931 - for ; Sat, 23 May 2026 18:34:42 +0200 (CEST) + by phobos.denx.de (Postfix) with ESMTPS id F147D84878 + for ; Mon, 1 Jun 2026 12:39:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) - id A928768CFE; Sat, 23 May 2026 18:34:40 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 8/9] pci: brcmstb: rework iBAR handling + id A1A3068BFE; Mon, 1 Jun 2026 12:39:36 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 8/9] pci: brcmstb: rework iBAR handling To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1481,8 +1482,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163440.A928768CFE@verein.lst.de> -Date: Sat, 23 May 2026 18:34:40 +0200 (CEST) +Message-Id: <20260601103936.A1A3068BFE@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:36 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -1512,13 +1513,13 @@ in one go, so the code is not 1:1 comparable. Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong +Reviewed-by: Neil Armstrong --- drivers/pci/pcie_brcmstb.c | 150 ++++++++++++++++++++++++++++++++----- 1 file changed, 131 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 1022f275dc8..74d6f2564c2 100644 +index 164d8e2b7fe..624376fe235 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -50,6 +50,29 @@ @@ -1551,7 +1552,7 @@ index 1022f275dc8..74d6f2564c2 100644 enum { RGR1_SW_INIT_1, PCIE_HARD_DEBUG, -@@ -440,17 +463,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, +@@ -441,17 +464,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); } @@ -1660,7 +1661,7 @@ index 1022f275dc8..74d6f2564c2 100644 int i, ret = 0; u16 nlw, cls, lnksta; u32 tmp; -@@ -495,23 +606,22 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -496,23 +607,22 @@ static int brcm_pcie_probe(struct udevice *dev) MISC_CTRL_CFG_READ_UR_MODE_MASK | MISC_CTRL_MAX_BURST_SIZE_128); @@ -1699,7 +1700,7 @@ index 1022f275dc8..74d6f2564c2 100644 writel(tmp, base + PCIE_MISC_MISC_CTRL); /* Disable the PCIe->GISB memory window (RC_BAR1) */ -@@ -528,6 +638,8 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -529,6 +639,8 @@ static int brcm_pcie_probe(struct udevice *dev) /* Clear any interrupts we find on boot */ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); @@ -1709,35 +1710,36 @@ index 1022f275dc8..74d6f2564c2 100644 brcm_pcie_set_gen(pcie, pcie->gen); -From patchwork Sat May 23 16:34:43 2026 +From patchwork Mon Jun 1 10:39:40 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2243372 +X-Patchwork-Id: 2247321 X-Patchwork-Delegate: pbrobinson@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; 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Sat, 23 May 2026 18:34:43 +0200 (CEST) -In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de> -References: <20260523163239.8EEA768BEB@verein.lst.de> -Subject: [PATCH v4 9/9] pci: brcmstb: Adapt to AXI bridge + id 3EFB268C7B; Mon, 1 Jun 2026 12:39:40 +0200 (CEST) +In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> +References: <20260601103557.022EB68B05@verein.lst.de> +Subject: [PATCH v5 9/9] pci: brcmstb: Adapt to AXI bridge To: Peter Robinson , Matthias Brugger Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= @@ -1777,8 +1779,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= =?unknown-8bit?q?=2Ede?= -Message-Id: <20260523163443.8B3CA68D0A@verein.lst.de> -Date: Sat, 23 May 2026 18:34:43 +0200 (CEST) +Message-Id: <20260601103940.3EFB268C7B@verein.lst.de> +Date: Mon, 1 Jun 2026 12:39:40 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 @@ -1806,7 +1808,7 @@ branch. All reworked for the simpler setup code in U-Boot. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong +Reviewed-by: Neil Armstrong --- .../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 + drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++- @@ -1825,10 +1827,10 @@ index 5171c593c72..c72b47e1b10 100644 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 74d6f2564c2..a14efa31734 100644 +index 624376fe235..1b03b0a7b05 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c -@@ -554,6 +554,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) +@@ -555,6 +555,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) } } @@ -1859,7 +1861,7 @@ index 74d6f2564c2..a14efa31734 100644 static int brcm_pcie_probe(struct udevice *dev) { struct udevice *ctlr = pci_get_controller(dev); -@@ -599,12 +623,27 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -600,12 +624,27 @@ static int brcm_pcie_probe(struct udevice *dev) /* Wait for SerDes to be stable */ udelay(100); @@ -1888,7 +1890,7 @@ index 74d6f2564c2..a14efa31734 100644 tmp = readl(base + PCIE_MISC_MISC_CTRL); if (pcie->pcie_cfg->type == BCM2712) { -@@ -624,6 +663,29 @@ static int brcm_pcie_probe(struct udevice *dev) +@@ -625,6 +664,29 @@ static int brcm_pcie_probe(struct udevice *dev) } writel(tmp, base + PCIE_MISC_MISC_CTRL); From 40a137ae166cd4a38133cf8bb4be8b012be721e6 Mon Sep 17 00:00:00 2001 From: Dusty Mabe Date: Fri, 19 Jun 2026 14:18:37 -0400 Subject: [PATCH 28/38] FFL: convert a few debug statements into info This way on boot we'll get one of the three: - Found DTB on disk - Found DTB: Prior firmware - Using DT from U-Boot Since it's only one log statement per boot I don't think this will add too much noise. --- ...initial-find_fdt_location-for-finding-the-DT-on-disk.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch index 5948f93..ac58bad 100644 --- a/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch +++ b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch @@ -169,7 +169,7 @@ index 44b806aadc4..61e982091b9 100644 + /* Check if there is device tree loaded from disk */ + fdt_opt = find_fdt_location(); + if (fdt_opt) -+ log_debug("Found DTB on disk\n"); ++ log_info("Found DTB on disk\n"); + /* Check if there is a hardware device tree */ - fdt_opt = env_get("fdt_addr"); @@ -181,7 +181,7 @@ index 44b806aadc4..61e982091b9 100644 /* Use our own device tree as fallback */ if (!fdt_opt) { fdt_opt = env_get("fdtcontroladdr"); -+ log_debug("Using DT from U-Boot\n"); ++ log_info("Using DT from U-Boot\n"); if (!fdt_opt) { log_err("need device tree\n"); return EFI_NOT_FOUND; From 6cdb801508369da8fd5d781a26209c376f5fe7e0 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 23 Jun 2026 10:59:52 +0100 Subject: [PATCH 29/38] 2026.07 RC5 --- 0001-Add-bcm2712-compat.patch | 24 - ARM-RPi5-Enable-PCIe.patch | 1922 ----------------- Fix-NVMe-not-only-on-Raspberry-Pi-5.patch | 36 +- ...state-access-to-memory-above-ram_top.patch | 50 - ...e-generic-MMC-device-tree-properties.patch | 167 -- ...-non-removable-check-in-bcm2712-init.patch | 185 -- ...ble-MBEDTLS-LWIP-WGET-and-WGET_HTTPS.patch | 171 -- sources | 2 +- uboot-tools.spec | 21 +- ...pi-Add-brcm-bcm2712-hdmi0-compatible.patch | 152 -- 10 files changed, 29 insertions(+), 2701 deletions(-) delete mode 100644 0001-Add-bcm2712-compat.patch delete mode 100644 ARM-RPi5-Enable-PCIe.patch delete mode 100644 Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch delete mode 100644 mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch delete mode 100644 mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch delete mode 100644 rpi_arm64-Enable-MBEDTLS-LWIP-WGET-and-WGET_HTTPS.patch delete mode 100644 video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch diff --git a/0001-Add-bcm2712-compat.patch b/0001-Add-bcm2712-compat.patch deleted file mode 100644 index 1e497b8..0000000 --- a/0001-Add-bcm2712-compat.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 83612ecf30e9192247ad8c2f67f585360f5ea68b Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 11 Mar 2026 14:27:21 +0000 -Subject: [PATCH] Add bcm2712 compat - ---- - drivers/video/bcm2835.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c -index 0c81e606622..0e0cc1979eb 100644 ---- a/drivers/video/bcm2835.c -+++ b/drivers/video/bcm2835.c -@@ -66,6 +66,7 @@ static int bcm2835_video_probe(struct udevice *dev) - static const struct udevice_id bcm2835_video_ids[] = { - { .compatible = "brcm,bcm2835-hdmi" }, - { .compatible = "brcm,bcm2711-hdmi0" }, -+ { .compatible = "brcm,bcm2712-hdmi0" }, - { .compatible = "brcm,bcm2708-fb" }, - #if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB) - { .compatible = "simple-framebuffer" }, --- -2.53.0 - diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch deleted file mode 100644 index db052eb..0000000 --- a/ARM-RPi5-Enable-PCIe.patch +++ /dev/null @@ -1,1922 +0,0 @@ -From patchwork Mon Jun 1 10:39:20 2026 -Content-Type: text/plain; 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Mon, 1 Jun 2026 12:39:20 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103920.1371668BEB@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:20 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -Add a mapping region for the PCIe bus address spaces to the BCM2712 -memory controller setup. Generously merging the PCIe address spaces -works sufficiently well for a boot loader. - -Signed-off-by: Torsten Duwe -Co-authored-by: Oleksii Moisieiev -Tested-by: Pedro Falcato -Reviewed-by: Peter Robinson ---- - arch/arm/mach-bcm283x/init.c | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 7a1de22e0ae..7a2faaa4de6 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -18,7 +18,7 @@ - #ifdef CONFIG_ARM64 - #include - --#define MEM_MAP_MAX_ENTRIES (4) -+#define MEM_MAP_MAX_ENTRIES (5) - - static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { - { -@@ -83,6 +83,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = { - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ /* Whole PCIe section */ -+ .virt = 0x1800000000UL, -+ .phys = 0x1800000000UL, -+ .size = 0x0800000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* SoC bus */ - .virt = 0x107c000000UL, - -From patchwork Mon Jun 1 10:39:23 2026 -Content-Type: text/plain; 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Mon, 1 Jun 2026 12:39:23 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 2/9] pci: brcmstb: Fix PCIe bus numbers -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103923.30A1F68C4E@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:23 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Andrea della Porta - -The linux kernel assigns a new domain for every Root Complex where bus -numbering starts from 0 for each domain. U-Boot does not have domains -and uses a flattened bus numbering scheme instead. This means that any -device or bridge on the second enumerated RC will receive a bus number -equal to the last assigned one +1. This bus number contributes to the -address written into the index register, which will select the -configuration space to be read. Compensate for this contribution by -subtracting the base bus number. - -Signed-off-by: Andrea della Porta -Signed-off-by: Torsten Duwe -Tested-by: Pedro Falcato -Reviewed-by: Peter Robinson ---- - drivers/pci/pcie_brcmstb.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index f089c48f028..47c0802df23 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -125,7 +125,7 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, - uint offset, void **paddress) - { - struct brcm_pcie *pcie = dev_get_priv(dev); -- unsigned int pci_bus = PCI_BUS(bdf); -+ unsigned int pci_bus = PCI_BUS(bdf) - dev_seq(dev); - unsigned int pci_dev = PCI_DEV(bdf); - unsigned int pci_func = PCI_FUNC(bdf); - int idx; - -From patchwork Mon Jun 1 10:39:25 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2247315 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; 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Mon, 1 Jun 2026 12:39:27 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id 6B2FE68C7B; Mon, 1 Jun 2026 12:39:25 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 3/9] pci: brcmstb: Support different variants using a cfg - struct -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103925.6B2FE68C7B@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:25 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -The Linux kernel driver already had support for multiple hardware -variants when the bcm2712 was added (see e.g. linux commit -10dbedad3c818 which is the last in a longer set of changes). This -patch brings in this required infrastructure and adds a -differentiation between 2711 and 2712 register layouts on top. - -Signed-off-by: Torsten Duwe -Co-authored-by: Oleksii Moisieiev -Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong ---- - .../mach-bcm283x/include/mach/acpi/bcm2711.h | 5 + - drivers/pci/pcie_brcmstb.c | 104 ++++++++++++++++-- - 2 files changed, 99 insertions(+), 10 deletions(-) - -diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -index a86875b1833..5171c593c72 100644 ---- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -@@ -70,6 +70,7 @@ - #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 - #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c - #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f -+#define PCIE_MISC_PCIE_CTRL 0x4064 - #define PCIE_MISC_PCIE_STATUS 0x4068 - #define STATUS_PCIE_PORT_MASK 0x80 - #define STATUS_PCIE_PORT_SHIFT 7 -@@ -108,6 +109,10 @@ - - #define PCIE_RGR1_SW_INIT_1 0x9210 - #define PCIE_EXT_CFG_INDEX 0x9000 -+#define RGR1_SW_INIT_1_PERST_MASK 0x1 -+#define RGR1_SW_INIT_1_PERSTB_MASK 0x4 -+#define RGR1_SW_INIT_1_INIT_MASK 0x2 -+ - /* A small window pointing at the ECAM of the device selected by CFG_INDEX */ - #define PCIE_EXT_CFG_DATA 0x8000 - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 47c0802df23..5cb39dfd136 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -49,6 +49,24 @@ - #define SSC_STATUS_PLL_LOCK_MASK 0x800 - #define SSC_STATUS_PLL_LOCK_SHIFT 11 - -+enum { -+ RGR1_SW_INIT_1, -+ PCIE_HARD_DEBUG, -+}; -+ -+enum brcm_pcie_type { -+ BCM2711, -+ BCM2712 -+}; -+ -+struct brcm_pcie; -+ -+struct brcm_pcie_cfg_data { -+ const int *offsets; -+ const enum brcm_pcie_type type; -+ void (*perst_set)(struct brcm_pcie *pcie, u32 val); -+}; -+ - /** - * struct brcm_pcie - the PCIe controller state - * @base: Base address of memory mapped IO registers of the controller -@@ -61,6 +79,7 @@ struct brcm_pcie { - - int gen; - bool ssc; -+ const struct brcm_pcie_cfg_data *pcie_cfg; - }; - - /** -@@ -104,6 +123,36 @@ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) - return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; - } - -+static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) -+{ -+ if (val) -+ setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], -+ RGR1_SW_INIT_1_PERST_MASK); -+ else -+ clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], -+ RGR1_SW_INIT_1_PERST_MASK); -+} -+ -+static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) -+{ -+ u32 tmp; -+ -+ /* Perst bit has moved and assert value is 0 */ -+ tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); -+ u32p_replace_bits(&tmp, !val, RGR1_SW_INIT_1_PERSTB_MASK); -+ writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); -+} -+ -+static void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) -+{ -+ if (val) -+ setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], -+ RGR1_SW_INIT_1_INIT_MASK); -+ else -+ clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], -+ RGR1_SW_INIT_1_INIT_MASK); -+} -+ - /** - * brcm_pcie_link_up() - Check whether the PCIe link is up - * @pcie: Pointer to the PCIe controller state -@@ -365,8 +414,9 @@ static int brcm_pcie_probe(struct udevice *dev) - * e.g. BCM7278, the fundamental reset should not be asserted here. - * This will need to be changed when support for other SoCs is added. - */ -- setbits_le32(base + PCIE_RGR1_SW_INIT_1, -- PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK); -+ brcm_pcie_bridge_sw_init_set(pcie, 1); -+ if (pcie->pcie_cfg->type != BCM2712) -+ pcie->pcie_cfg->perst_set(pcie, 1); - /* - * The delay is a safety precaution to preclude the reset signal - * from looking like a glitch. -@@ -374,9 +424,9 @@ static int brcm_pcie_probe(struct udevice *dev) - udelay(100); - - /* Take the bridge out of reset */ -- clrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); -+ brcm_pcie_bridge_sw_init_set(pcie, 0); - -- clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, -+ clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], - PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); - - /* Wait for SerDes to be stable */ -@@ -426,8 +476,7 @@ static int brcm_pcie_probe(struct udevice *dev) - brcm_pcie_set_gen(pcie, pcie->gen); - - /* Unassert the fundamental reset */ -- clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, -- PCIE_RGR1_SW_INIT_1_PERST_MASK); -+ pcie->pcie_cfg->perst_set(pcie, 0); - - /* - * Wait for 100ms after PERST# deassertion; see PCIe CEM specification -@@ -514,14 +563,25 @@ static int brcm_pcie_remove(struct udevice *dev) - void __iomem *base = pcie->base; - - /* Assert fundamental reset */ -- setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK); -+ setbits_le32(base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], -+ PCIE_RGR1_SW_INIT_1_PERST_MASK); - - /* Turn off SerDes */ -- setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, -+ setbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], - PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); - - /* Shutdown bridge */ -- setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK); -+ brcm_pcie_bridge_sw_init_set(pcie, 1); -+ -+ /* -+ * For the controllers that are utilizing reset for bridge Sw init, -+ * such as BCM2712, reset should be deasserted after assertion. -+ * Leaving it in asserted state may lead to unexpected hangs in -+ * the Linux Kernel driver because it do not perform reset initialization -+ * and start accessing device memory. -+ */ -+ if (pcie->pcie_cfg->type == BCM2712) -+ brcm_pcie_bridge_sw_init_set(pcie, 0); - - return 0; - } -@@ -546,6 +606,7 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) - else - pcie->gen = max_link_speed; - -+ pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); - return 0; - } - -@@ -554,8 +615,31 @@ static const struct dm_pci_ops brcm_pcie_ops = { - .write_config = brcm_pcie_write_config, - }; - -+static const int pcie_offsets[] = { -+ [RGR1_SW_INIT_1] = 0x9210, -+ [PCIE_HARD_DEBUG] = 0x4204, -+}; -+ -+static const struct brcm_pcie_cfg_data bcm2711_cfg = { -+ .offsets = pcie_offsets, -+ .type = BCM2711, -+ .perst_set = brcm_pcie_perst_set_generic, -+}; -+ -+static const int pcie_offsets_bcm2712[] = { -+ [RGR1_SW_INIT_1] = 0x0, -+ [PCIE_HARD_DEBUG] = 0x4304, -+}; -+ -+static const struct brcm_pcie_cfg_data bcm2712_cfg = { -+ .offsets = pcie_offsets_bcm2712, -+ .type = BCM2712, -+ .perst_set = brcm_pcie_perst_set_2712, -+}; -+ - static const struct udevice_id brcm_pcie_ids[] = { -- { .compatible = "brcm,bcm2711-pcie" }, -+ { .compatible = "brcm,bcm2711-pcie", .data = (ulong)&bcm2711_cfg }, -+ { .compatible = "brcm,bcm2712-pcie", .data = (ulong)&bcm2712_cfg }, - { } - }; - - -From patchwork Mon Jun 1 10:39:27 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2247316 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVpJ3NjHz1yCV - for ; Mon, 01 Jun 2026 20:39:52 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id C82428489D; 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Mon, 1 Jun 2026 12:39:27 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 4/9] reset: Add RPi5 brcmstb reset facilities -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103927.7616B68D05@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:27 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -A driver for Broadcom reset controllers ported from -linux/drivers/reset/reset-brcmstb.c to U-Boot. - -Signed-off-by: Torsten Duwe -Co-authored-by: Oleksii Moisieiev -Tested-by: Pedro Falcato ---- - configs/rpi_arm64_defconfig | 1 + - drivers/reset/Kconfig | 8 +++ - drivers/reset/Makefile | 1 + - drivers/reset/reset-brcmstb.c | 97 +++++++++++++++++++++++++++++++++++ - 4 files changed, 107 insertions(+) - create mode 100644 drivers/reset/reset-brcmstb.c - -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 69e8e72c5d7..153d7ed301e 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -44,6 +44,7 @@ CONFIG_BCMGENET=y - CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set -+CONFIG_RESET_BRCMSTB=y - CONFIG_DM_RNG=y - CONFIG_RNG_IPROC200=y - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set -diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index 2fd91d6299c..8f4c9e29baa 100644 ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -64,6 +64,14 @@ config RESET_BCM6345 - help - Support reset controller on BCM6345. - -+config RESET_BRCMSTB -+ depends on ARCH_BCM283X -+ bool "Generic Reset controller driver for Broadcom" -+ help -+ This enables reset controller for Broadcom devices. -+ If you wish to use reset resources managed by the Broadcom -+ Reset Controller, say Y here. Otherwise, say N. -+ - config RESET_UNIPHIER - bool "Reset controller driver for UniPhier SoCs" - depends on ARCH_UNIPHIER -diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index ee5b009d134..ebf3d7425a4 100644 ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o - obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o - obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o - obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o -+obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o - obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o - obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o - obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c -new file mode 100644 -index 00000000000..7861f7c9baf ---- /dev/null -+++ b/drivers/reset/reset-brcmstb.c -@@ -0,0 +1,97 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Broadcom STB generic reset controller -+ * -+ * Copyright (C) 2024 EPAM Systems -+ * -+ * Moved from linux kernel: -+ * Author: Florian Fainelli -+ * Copyright (C) 2018 Broadcom -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct brcmstb_reset { -+ void __iomem *base; -+}; -+ -+#define SW_INIT_SET 0x00 -+#define SW_INIT_CLEAR 0x04 -+#define SW_INIT_STATUS 0x08 -+ -+#define SW_INIT_BIT(id) BIT((id) & 0x1f) -+#define SW_INIT_BANK(id) ((id) >> 5) -+ -+#define usleep_range(a, b) udelay((b)) -+ -+/* A full bank contains extra registers that we are not utilizing but still -+ * qualify as a single bank. -+ */ -+#define SW_INIT_BANK_SIZE 0x18 -+ -+static int brcmstb_reset_assert(struct reset_ctl *rst) -+{ -+ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; -+ struct brcmstb_reset *priv = dev_get_priv(rst->dev); -+ -+ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_SET); -+ return 0; -+} -+ -+static int brcmstb_reset_deassert(struct reset_ctl *rst) -+{ -+ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; -+ struct brcmstb_reset *priv = dev_get_priv(rst->dev); -+ -+ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_CLEAR); -+ /* Maximum reset delay after de-asserting a line and seeing block -+ * operation is typically 14us for the worst case, build some slack -+ * here. -+ */ -+ usleep_range(100, 200); -+ return 0; -+} -+ -+static int brcmstb_reset_status(struct reset_ctl *rst) -+{ -+ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; -+ struct brcmstb_reset *priv = dev_get_priv(rst->dev); -+ -+ return readl_relaxed(priv->base + off + SW_INIT_STATUS) & -+ SW_INIT_BIT(rst->id); -+} -+ -+struct reset_ops brcmstb_reset_reset_ops = { -+ .rst_assert = brcmstb_reset_assert, -+ .rst_deassert = brcmstb_reset_deassert, -+ .rst_status = brcmstb_reset_status}; -+ -+static int brcmstb_reset_probe(struct udevice *dev) -+{ -+ struct brcmstb_reset *priv = dev_get_priv(dev); -+ -+ priv->base = dev_remap_addr(dev); -+ if (!priv->base) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static const struct udevice_id brcmstb_reset_ids[] = { -+ {.compatible = "brcm,brcmstb-reset"}, {/* sentinel */}}; -+ -+U_BOOT_DRIVER(brcmstb_reset) = { -+ .name = "brcmstb-reset", -+ .id = UCLASS_RESET, -+ .of_match = brcmstb_reset_ids, -+ .ops = &brcmstb_reset_reset_ops, -+ .probe = brcmstb_reset_probe, -+ .priv_auto = sizeof(struct brcmstb_reset), -+}; - -From patchwork Mon Jun 1 10:39:29 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2247317 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVpT3Zvdz1yCV - for ; Mon, 01 Jun 2026 20:40:01 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 0947E848A1; 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Mon, 1 Jun 2026 12:39:29 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 5/9] reset: Add RPi5 rescal reset facilities -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103929.751D668D09@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:29 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -A driver for Broadcom rescal reset controllers ported from -linux/drivers/reset/reset-brcmstb-rescal.c to U-Boot. - -Signed-off-by: Torsten Duwe -Co-authored-by: Oleksii Moisieiev -Tested-by: Pedro Falcato ---- - configs/rpi_arm64_defconfig | 1 + - drivers/reset/Kconfig | 8 +++ - drivers/reset/Makefile | 1 + - drivers/reset/reset-brcmstb-rescal.c | 103 +++++++++++++++++++++++++++ - 4 files changed, 113 insertions(+) - create mode 100644 drivers/reset/reset-brcmstb-rescal.c - -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 153d7ed301e..38af5029403 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -45,6 +45,7 @@ CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - CONFIG_RESET_BRCMSTB=y -+CONFIG_RESET_BRCMSTB_RESCAL=y - CONFIG_DM_RNG=y - CONFIG_RNG_IPROC200=y - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set -diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index 8f4c9e29baa..e6c23368428 100644 ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -72,6 +72,14 @@ config RESET_BRCMSTB - If you wish to use reset resources managed by the Broadcom - Reset Controller, say Y here. Otherwise, say N. - -+config RESET_BRCMSTB_RESCAL -+ depends on ARCH_BCM283X -+ bool "Generic Rescal Reset controller driver for Broadcom" -+ help -+ Support rescal reset controller on Broadcom. -+ If you wish to use reset resources managed by the Broadcom -+ Reset Controller, say Y here. Otherwise, say N. -+ - config RESET_UNIPHIER - bool "Reset controller driver for UniPhier SoCs" - depends on ARCH_UNIPHIER -diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index ebf3d7425a4..c7a9da3268d 100644 ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o - obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o - obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o - obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o -+obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o - obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o - obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o - obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c -new file mode 100644 -index 00000000000..fc8fcfa8b3f ---- /dev/null -+++ b/drivers/reset/reset-brcmstb-rescal.c -@@ -0,0 +1,103 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Broadcom STB generic reset controller -+ * -+ * Copyright (C) 2024 EPAM Systems -+ * Moved from linux kernel: -+ * Copyright (C) 2018-2020 Broadcom -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BRCM_RESCAL_START 0x0 -+#define BRCM_RESCAL_START_BIT BIT(0) -+#define BRCM_RESCAL_CTRL 0x4 -+#define BRCM_RESCAL_STATUS 0x8 -+#define BRCM_RESCAL_STATUS_BIT BIT(0) -+ -+struct brcm_rescal_reset { -+ void __iomem *base; -+}; -+ -+/* Also doubles a deassert */ -+static int brcm_rescal_reset_set(struct reset_ctl *rst) -+{ -+ struct brcm_rescal_reset *data = dev_get_priv(rst->dev); -+ void __iomem *base = data->base; -+ u32 reg; -+ int ret; -+ -+ reg = readl(base + BRCM_RESCAL_START); -+ writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); -+ reg = readl(base + BRCM_RESCAL_START); -+ if (!(reg & BRCM_RESCAL_START_BIT)) { -+ dev_err(rst->dev, "failed to start SATA/PCIe rescal\n"); -+ return -EIO; -+ } -+ -+ ret = readl_poll_timeout(base + BRCM_RESCAL_STATUS, reg, -+ (reg & BRCM_RESCAL_STATUS_BIT), 100); -+ if (ret) { -+ dev_err(rst->dev, "time out on SATA/PCIe rescal\n"); -+ return ret; -+ } -+ -+ reg = readl(base + BRCM_RESCAL_START); -+ writel(reg & ~BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); -+ -+ dev_dbg(rst->dev, "SATA/PCIe rescal success\n"); -+ return 0; -+} -+ -+/* A dummy function - deassert/reset does all the work */ -+static int brcm_rescal_reset_assert(struct reset_ctl *rst) -+{ -+ return 0; -+} -+ -+static int brcm_rescal_reset_xlate(struct reset_ctl *reset_ctl, -+ struct ofnode_phandle_args *args) -+{ -+ /* This is needed if #reset-cells == 0. */ -+ return 0; -+} -+ -+static const struct reset_ops brcm_rescal_reset_ops = { -+ .rst_deassert = brcm_rescal_reset_set, -+ .rst_assert = brcm_rescal_reset_assert, -+ .of_xlate = brcm_rescal_reset_xlate, -+}; -+ -+static int brcm_rescal_reset_probe(struct udevice *dev) -+{ -+ struct brcm_rescal_reset *data = dev_get_priv(dev); -+ -+ data->base = dev_remap_addr(dev); -+ if (!data->base) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static const struct udevice_id brcm_rescal_reset_of_match[] = { -+ {.compatible = "brcm,bcm7216-pcie-sata-rescal"}, -+ {}, -+}; -+ -+U_BOOT_DRIVER(brcmstb_reset_rescal) = { -+ .name = "brcmstb-reset-rescal", -+ .id = UCLASS_RESET, -+ .of_match = brcm_rescal_reset_of_match, -+ .ops = &brcm_rescal_reset_ops, -+ .probe = brcm_rescal_reset_probe, -+ .priv_auto = sizeof(struct brcm_rescal_reset), -+}; - -From patchwork Mon Jun 1 10:39:31 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2247318 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVph2NvWz1yDY - for ; Mon, 01 Jun 2026 20:40:12 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 3C481848B9; - Mon, 1 Jun 2026 12:39:36 +0200 (CEST) -Authentication-Results: phobos.denx.de; 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Mon, 1 Jun 2026 12:39:31 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 6/9] pci: brcmstb: Get and use bridge and rescal reset - properties -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103931.BD8CC68D0D@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:31 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -Check whether the device tree has nodes for the two reset controls and use -them if so. - -Signed-off-by: Torsten Duwe -Co-authored-by: Oleksii Moisieiev -Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong ---- - drivers/pci/pcie_brcmstb.c | 71 +++++++++++++++++++++++++++++++++++--- - 1 file changed, 66 insertions(+), 5 deletions(-) - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 5cb39dfd136..012b501078a 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - - /* PCIe parameters */ - #define BRCM_NUM_PCIE_OUT_WINS 4 -@@ -79,6 +80,8 @@ struct brcm_pcie { - - int gen; - bool ssc; -+ struct reset_ctl rescal; -+ struct reset_ctl bridge_reset; - const struct brcm_pcie_cfg_data *pcie_cfg; - }; - -@@ -143,14 +146,58 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) - writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); - } - --static void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) -+static int brcm_pcie_get_resets_dt(struct udevice *dev) - { -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ int ret; -+ -+ ret = reset_get_by_name(dev, "rescal", &pcie->rescal); -+ if (ret) { -+ printf("Unable to get rescal reset\n"); -+ return ret; -+ } -+ -+ ret = reset_get_by_name(dev, "bridge", &pcie->bridge_reset); -+ if (ret) -+ printf("Unable to get bridge reset\n"); -+ -+ return ret; -+} -+ -+static int brcm_pcie_do_reset(struct udevice *dev) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ int ret; -+ -+ ret = reset_deassert(&pcie->rescal); -+ if (ret) -+ printf("failed to deassert 'rescal'\n"); -+ return ret; -+} -+ -+static int brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) -+{ -+ int ret = 0; -+ -+ if (reset_valid(&pcie->bridge_reset)) -+ { -+ if (val) -+ ret = reset_assert(&pcie->bridge_reset); -+ else -+ ret = reset_deassert(&pcie->bridge_reset); -+ if (ret) -+ log_err("failed to %sassert bridge reset, err=%d\n", -+ val ? "" : "de", ret); -+ return ret; -+ } -+ - if (val) - setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], - RGR1_SW_INIT_1_INIT_MASK); - else - clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1], - RGR1_SW_INIT_1_INIT_MASK); -+ return 0; - } - - /** -@@ -405,16 +452,25 @@ static int brcm_pcie_probe(struct udevice *dev) - int num_out_wins = 0; - u64 rc_bar2_offset, rc_bar2_size; - unsigned int scb_size_val; -- int i, ret; -+ int i, ret = 0; - u16 nlw, cls, lnksta; - u32 tmp; - -+ /* -+ * Ensure rescal reset for BCM2712 is really disabled. -+ */ -+ if (pcie->pcie_cfg->type == BCM2712) -+ ret = brcm_pcie_do_reset(dev); -+ if (ret) -+ return ret; - /* - * Reset the bridge, assert the fundamental reset. Note for some SoCs, - * e.g. BCM7278, the fundamental reset should not be asserted here. - * This will need to be changed when support for other SoCs is added. - */ -- brcm_pcie_bridge_sw_init_set(pcie, 1); -+ ret = brcm_pcie_bridge_sw_init_set(pcie, 1); -+ if (ret) -+ return ret; - if (pcie->pcie_cfg->type != BCM2712) - pcie->pcie_cfg->perst_set(pcie, 1); - /* -@@ -424,8 +480,9 @@ static int brcm_pcie_probe(struct udevice *dev) - udelay(100); - - /* Take the bridge out of reset */ -- brcm_pcie_bridge_sw_init_set(pcie, 0); -- -+ ret = brcm_pcie_bridge_sw_init_set(pcie, 0); -+ if (ret) -+ return ret; - clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG], - PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); - -@@ -607,6 +664,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) - pcie->gen = max_link_speed; - - pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev); -+ -+ if (pcie->pcie_cfg->type == BCM2712) -+ return brcm_pcie_get_resets_dt(dev); -+ - return 0; - } - - -From patchwork Mon Jun 1 10:39:34 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2247319 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVpv2npJz1yDY - for ; Mon, 01 Jun 2026 20:40:23 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 4CB0084898; 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Mon, 1 Jun 2026 12:39:34 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 7/9] pci: brcmstb: Fix iBAR size calculation -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103934.5B8CC68D0E@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:34 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -Fix inbound window size calculation, like Linux commit 25a98c7270156. - -Signed-off-by: Torsten Duwe -Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong ---- - drivers/pci/pcie_brcmstb.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 012b501078a..164d8e2b7fe 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -101,8 +101,8 @@ static int brcm_pcie_encode_ibar_size(u64 size) - if (log2_in >= 12 && log2_in <= 15) - /* Covers 4KB to 32KB (inclusive) */ - return (log2_in - 12) + 0x1c; -- else if (log2_in >= 16 && log2_in <= 37) -- /* Covers 64KB to 32GB, (inclusive) */ -+ else if (log2_in >= 16 && log2_in <= 36) -+ /* Covers 64KB to 64GB, (inclusive) */ - return log2_in - 15; - - /* Something is awry so disable */ - -From patchwork Mon Jun 1 10:39:36 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2247320 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVq615M9z1yDY - for ; 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- dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id A1A3068BFE; Mon, 1 Jun 2026 12:39:36 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 8/9] pci: brcmstb: rework iBAR handling -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103936.A1A3068BFE@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:36 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -Rework the setup of inbound PCIe windows: use the convenience functions -from Linux kernel commit ae6476c6de187 to calculate the BAR offsets and -factor out the setup code into a separate function. - -The Linux kernel first allocates and populates an array of inbound_win[] -and sets the BARs from it later, while U-Boot does it all on the fly, -in one go, so the code is not 1:1 comparable. - -Signed-off-by: Torsten Duwe -Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong ---- - drivers/pci/pcie_brcmstb.c | 150 ++++++++++++++++++++++++++++++++----- - 1 file changed, 131 insertions(+), 19 deletions(-) - -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 164d8e2b7fe..624376fe235 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -50,6 +50,29 @@ - #define SSC_STATUS_PLL_LOCK_MASK 0x800 - #define SSC_STATUS_PLL_LOCK_SHIFT 11 - -+#define PCIE_RC_PL_PHY_CTL_15 0x184c -+#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 -+#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff -+ -+#define PCIE_MISC_UBUS_CTRL 0x40a4 -+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK BIT(13) -+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK BIT(19) -+#define PCIE_MISC_AXI_READ_ERROR_DATA 0x4170 -+#define PCIE_MISC_UBUS_TIMEOUT 0x40A8 -+#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c -+#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 -+#define PCIE_MISC_RC_BAR4_CONFIG_HI 0x40d8 -+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK 0xff -+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI 0x4110 -+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE 0x1 -+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK 0xfffff000 -+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO 0x410c -+ -+#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac -+#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP 0x40b4 -+#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0) -+#define MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 -+ - enum { - RGR1_SW_INIT_1, - PCIE_HARD_DEBUG, -@@ -441,17 +464,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, - writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); - } - -+static u32 brcm_bar_reg_offset(int bar) -+{ -+ if (bar <= 3) -+ return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); -+ else -+ return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); -+} -+ -+static u32 brcm_ubus_reg_offset(int bar) -+{ -+ if (bar <= 3) -+ return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); -+ else -+ return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4); -+} -+ -+/* -+ * Round size up to the next power of two, as required by -+ * brcm_pcie_encode_ibar_size(). If size is already a power of two -+ * fls64(size - 1) still gives the correct result because the hardware -+ * encodes the exponent, not the raw value. -+ */ -+static u64 brcm_ibar_round_size(u64 size) -+{ -+ return 1ULL << fls64(size - 1); -+} -+ -+static void brcm_pcie_set_inbound_windows(struct udevice *dev) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ void __iomem *base = pcie->base; -+ bool is_2712 = (pcie->pcie_cfg->type == BCM2712); -+ int i, ibar_no, ret; -+ u32 tmp; -+ -+ ibar_no = 0; -+ /* pre-2712 chips leave the first entry empty */ -+ if (pcie->pcie_cfg->type != BCM2712) -+ ibar_no++; -+ -+ /* program inbound windows from OF property "dma-regions" */ -+ for (i = 0; i < 7; i++, ibar_no++) { -+ u64 bar_cpu, bar_size, bar_pci; -+ struct pci_region region; -+ int ubus_bar_offset, rc_bar_offset; -+ -+ ret = pci_get_dma_regions(dev, ®ion, i); -+ if (ret) /* no region #i? Then we're done. */ -+ break; -+ ubus_bar_offset = brcm_ubus_reg_offset(ibar_no + 1); -+ rc_bar_offset = brcm_bar_reg_offset(ibar_no + 1); -+ -+ bar_pci = region.bus_start; -+ bar_cpu = region.phys_start; -+ bar_size = region.size; -+ -+ if (is_2712) { -+ /* BCM2712: BAR holds raw PCI address; UBUS remap -+ * registers supply the CPU-side translation. */ -+ tmp = lower_32_bits(bar_pci); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), -+ RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + rc_bar_offset); -+ writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4); -+ -+ tmp = lower_32_bits(bar_cpu) & -+ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; -+ tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE; -+ writel(tmp, base + ubus_bar_offset); -+ -+ tmp = upper_32_bits(bar_cpu) & -+ PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; -+ writel(tmp, base + ubus_bar_offset + 4); -+ } else { -+ /* Pre-BCM2712 (e.g. BCM2711 / RPi4): the BAR config -+ * register holds the offset (bus_start - phys_start), -+ * not the raw PCI address. The size must be rounded -+ * up to the next power of two before encoding. */ -+ u64 bar_offset = bar_pci - bar_cpu; -+ u64 bar_size_po2 = brcm_ibar_round_size(bar_size); -+ -+ tmp = lower_32_bits(bar_offset); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size_po2), -+ RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + rc_bar_offset); -+ writel(upper_32_bits(bar_offset), base + rc_bar_offset + 4); -+ /* UBUS remap registers are not used on pre-2712 hardware. */ -+ } -+ } -+} -+ - static int brcm_pcie_probe(struct udevice *dev) - { - struct udevice *ctlr = pci_get_controller(dev); - struct pci_controller *hose = dev_get_uclass_priv(ctlr); - struct brcm_pcie *pcie = dev_get_priv(dev); - void __iomem *base = pcie->base; -- struct pci_region region; - bool ssc_good = false; - int num_out_wins = 0; -- u64 rc_bar2_offset, rc_bar2_size; -- unsigned int scb_size_val; - int i, ret = 0; - u16 nlw, cls, lnksta; - u32 tmp; -@@ -496,23 +607,22 @@ static int brcm_pcie_probe(struct udevice *dev) - MISC_CTRL_CFG_READ_UR_MODE_MASK | - MISC_CTRL_MAX_BURST_SIZE_128); - -- pci_get_dma_regions(dev, ®ion, 0); -- rc_bar2_offset = region.bus_start - region.phys_start; -- rc_bar2_size = 1ULL << fls64(region.size - 1); -- -- tmp = lower_32_bits(rc_bar2_offset); -- u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), -- RC_BAR2_CONFIG_LO_SIZE_MASK); -- writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); -- writel(upper_32_bits(rc_bar2_offset), -- base + PCIE_MISC_RC_BAR2_CONFIG_HI); -- -- scb_size_val = rc_bar2_size ? -- ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ -- - tmp = readl(base + PCIE_MISC_MISC_CTRL); -- u32p_replace_bits(&tmp, scb_size_val, -- MISC_CTRL_SCB0_SIZE_MASK); -+ if (pcie->pcie_cfg->type == BCM2712) { -+ /* BCM2712: fixed 32GB SCB0 window */ -+ u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK); -+ } else { -+ /* Pre-BCM2712: size SCB0 to match the actual DMA region. -+ * rc_bar2_size must be a power of two; ilog2(size) - 15 -+ * gives the hardware encoding (e.g. 1GB -> 15). */ -+ struct pci_region region; -+ u64 rc_bar2_size; -+ -+ pci_get_dma_regions(dev, ®ion, 0); -+ rc_bar2_size = brcm_ibar_round_size(region.size); -+ u32p_replace_bits(&tmp, rc_bar2_size ? ilog2(rc_bar2_size) - 15 : 0xf, -+ MISC_CTRL_SCB0_SIZE_MASK); -+ } - writel(tmp, base + PCIE_MISC_MISC_CTRL); - - /* Disable the PCIe->GISB memory window (RC_BAR1) */ -@@ -529,6 +639,8 @@ static int brcm_pcie_probe(struct udevice *dev) - /* Clear any interrupts we find on boot */ - writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); - -+ brcm_pcie_set_inbound_windows(dev); -+ - if (pcie->gen) - brcm_pcie_set_gen(pcie, pcie->gen); - - -From patchwork Mon Jun 1 10:39:40 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2247321 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Mon, 1 Jun 2026 12:39:41 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=lst.de -Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de -Received: by verein.lst.de (Postfix, from userid 2005) - id 3EFB268C7B; Mon, 1 Jun 2026 12:39:40 +0200 (CEST) -In-Reply-To: <20260601103557.022EB68B05@verein.lst.de> -References: <20260601103557.022EB68B05@verein.lst.de> -Subject: [PATCH v5 9/9] pci: brcmstb: Adapt to AXI bridge -To: Peter Robinson , - Matthias Brugger -Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?= - =?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?= - =?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?= - =?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?= - =?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?= - =?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?= - =?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?= - =?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?= - =?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?= - =?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?= - =?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?= - =?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?= - =?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?= - =?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?= - =?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?= - =?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?= - =?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?= - =?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?= - =?unknown-8bit?q?=2Ede?= -Message-Id: <20260601103940.3EFB268C7B@verein.lst.de> -Date: Mon, 1 Jun 2026 12:39:40 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -Fix-ups for the BCM root complex when it is located behind an AXI -bridge and clocked with 54MHz. Some are from kernel commit -377bced88c326, some where picked by Oleksii off a now-stale older -branch. All reworked for the simpler setup code in U-Boot. - -Signed-off-by: Torsten Duwe -Co-authored-by: Oleksii Moisieiev -Tested-by: Pedro Falcato -Reviewed-by: Neil Armstrong ---- - .../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 + - drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++- - 2 files changed, 64 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -index 5171c593c72..c72b47e1b10 100644 ---- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h -@@ -54,6 +54,7 @@ - #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 - #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 - #define MISC_CTRL_MAX_BURST_SIZE_128 0x0 -+#define MISC_CTRL_MAX_BURST_SIZE_128_2712 0x100000 - #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 - - #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -index 624376fe235..1b03b0a7b05 100644 ---- a/drivers/pci/pcie_brcmstb.c -+++ b/drivers/pci/pcie_brcmstb.c -@@ -555,6 +555,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev) - } - } - -+static void brcm_pcie_munge_pll(struct brcm_pcie *pcie) -+{ -+ u32 tmp; -+ int ret, i; -+ u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; -+ u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; -+ -+ ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, -+ 0x1600); -+ for (i = 0; i < ARRAY_SIZE(regs); i++) { -+ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); -+ debug("PCIE MDIO pre_refclk 0x%02x = 0x%04x\n", -+ regs[i], tmp); -+ } -+ for (i = 0; i < ARRAY_SIZE(regs); i++) { -+ brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); -+ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); -+ debug("PCIE MDIO post_refclk 0x%02x = 0x%04x\n", -+ regs[i], tmp); -+ } -+ -+ udelay(200); -+} -+ - static int brcm_pcie_probe(struct udevice *dev) - { - struct udevice *ctlr = pci_get_controller(dev); -@@ -600,12 +624,27 @@ static int brcm_pcie_probe(struct udevice *dev) - /* Wait for SerDes to be stable */ - udelay(100); - -+ if (pcie->pcie_cfg->type == BCM2712) { -+ /* Allow a 54MHz (xosc) refclk source */ -+ brcm_pcie_munge_pll(pcie); -+ /* Fix for L1SS errata */ -+ tmp = readl(base + PCIE_RC_PL_PHY_CTL_15); -+ tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; -+ /* PM clock period is 18.52ns (round down) */ -+ tmp |= 0x12; -+ writel(tmp, base + PCIE_RC_PL_PHY_CTL_15); -+ } -+ -+ tmp = (pcie->pcie_cfg->type == BCM2712) ? -+ MISC_CTRL_MAX_BURST_SIZE_128_2712 : -+ MISC_CTRL_MAX_BURST_SIZE_128; - /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ - clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, - MISC_CTRL_MAX_BURST_SIZE_MASK, - MISC_CTRL_SCB_ACCESS_EN_MASK | - MISC_CTRL_CFG_READ_UR_MODE_MASK | -- MISC_CTRL_MAX_BURST_SIZE_128); -+ MISC_CTRL_PCIE_RCB_MPS_MODE_MASK | -+ tmp); - - tmp = readl(base + PCIE_MISC_MISC_CTRL); - if (pcie->pcie_cfg->type == BCM2712) { -@@ -625,6 +664,29 @@ static int brcm_pcie_probe(struct udevice *dev) - } - writel(tmp, base + PCIE_MISC_MISC_CTRL); - -+ if (pcie->pcie_cfg->type == BCM2712) { -+ /* Suppress AXI error responses and return 1s for read failures */ -+ tmp = readl(base + PCIE_MISC_UBUS_CTRL); -+ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK); -+ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK); -+ writel(tmp, base + PCIE_MISC_UBUS_CTRL); -+ writel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA); -+ -+ /* -+ * Adjust timeouts. The UBUS timeout also affects CRS -+ * completion retries, as the request will get terminated if -+ * either timeout expires, so both have to be a large value -+ * (in clocks of 750MHz). -+ * Set UBUS timeout to 250ms, then set RC config retry timeout -+ * to be ~240ms. -+ * -+ * Setting CRSVis=1 will stop the core from blocking on a CRS -+ * response, but does require the device to be well-behaved... -+ */ -+ writel(0xB2D0000, base + PCIE_MISC_UBUS_TIMEOUT); -+ writel(0xABA0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT); -+ } -+ - /* Disable the PCIe->GISB memory window (RC_BAR1) */ - clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, - RC_BAR1_CONFIG_LO_SIZE_MASK); diff --git a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch index 48bad44..67f0d6b 100644 --- a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch +++ b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch @@ -1,4 +1,4 @@ -From 06179e084181cbbc1e20121dc525621b77733bbc Mon Sep 17 00:00:00 2001 +From 9f926e07a9fc34d9c95fcc331867ee17d6a12105 Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Fri, 8 May 2026 17:42:39 +0200 Subject: [PATCH 1/3] core: Skip parent device nodes without a DT reference @@ -48,9 +48,9 @@ index d365204ba11..b6d00cf4714 100644 -- 2.54.0 -From 38978e38c1246972a318479a1e833d66f06e41be Mon Sep 17 00:00:00 2001 +From 960be63c0519239a2278cb5a6569398d0013f422 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Fri, 29 May 2026 13:38:27 +0100 +Date: Tue, 23 Jun 2026 10:55:17 +0100 Subject: [PATCH 2/3] nvme: Fix missing address translation for PCIe inbound access @@ -70,7 +70,7 @@ Signed-off-by: Peter Robinson 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c -index 0631b190b97..713f2b0b713 100644 +index 147a104149e..6f5f58e4088 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -12,6 +12,7 @@ @@ -81,9 +81,9 @@ index 0631b190b97..713f2b0b713 100644 #include #include #include -@@ -27,6 +28,13 @@ - #define IO_TIMEOUT 30 - #define MAX_PRP_POOL 512 +@@ -44,6 +45,13 @@ static inline void nvme_invalidate_cache_aligned(uintptr_t addr, int length) + invalidate_dcache_range(start_addr, end_addr); + } +/* + * Convert a memory address to the value needed by the PCI device to @@ -95,7 +95,7 @@ index 0631b190b97..713f2b0b713 100644 static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) { int timeout; -@@ -91,8 +99,8 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, +@@ -108,8 +116,8 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, i = 0; while (nprps) { if ((i == (prps_per_page - 1)) && nprps > 1) { @@ -106,7 +106,7 @@ index 0631b190b97..713f2b0b713 100644 i = 0; prp_pool = (u64 *)((uintptr_t)prp_pool + page_size); } -@@ -396,8 +404,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) +@@ -410,8 +418,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; writel(aqa, &dev->bar->aqa); @@ -117,7 +117,7 @@ index 0631b190b97..713f2b0b713 100644 result = nvme_enable_ctrl(dev); if (result) -@@ -423,7 +431,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, +@@ -437,7 +445,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, memset(&c, 0, sizeof(c)); c.create_cq.opcode = nvme_admin_create_cq; @@ -126,7 +126,7 @@ index 0631b190b97..713f2b0b713 100644 c.create_cq.cqid = cpu_to_le16(qid); c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); c.create_cq.cq_flags = cpu_to_le16(flags); -@@ -440,7 +448,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, +@@ -454,7 +462,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, memset(&c, 0, sizeof(c)); c.create_sq.opcode = nvme_admin_create_sq; @@ -135,7 +135,7 @@ index 0631b190b97..713f2b0b713 100644 c.create_sq.sqid = cpu_to_le16(qid); c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); c.create_sq.sq_flags = cpu_to_le16(flags); -@@ -461,14 +469,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, +@@ -476,14 +484,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, memset(&c, 0, sizeof(c)); c.identify.opcode = nvme_admin_identify; c.identify.nsid = cpu_to_le32(nsid); @@ -152,7 +152,7 @@ index 0631b190b97..713f2b0b713 100644 } c.identify.cns = cpu_to_le32(cns); -@@ -493,7 +501,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, +@@ -508,7 +516,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, memset(&c, 0, sizeof(c)); c.features.opcode = nvme_admin_get_features; c.features.nsid = cpu_to_le32(nsid); @@ -161,7 +161,7 @@ index 0631b190b97..713f2b0b713 100644 c.features.fid = cpu_to_le32(fid); ret = nvme_submit_admin_cmd(dev, &c, result); -@@ -519,7 +527,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, +@@ -534,7 +542,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, memset(&c, 0, sizeof(c)); c.features.opcode = nvme_admin_set_features; @@ -170,7 +170,7 @@ index 0631b190b97..713f2b0b713 100644 c.features.fid = cpu_to_le32(fid); c.features.dword11 = cpu_to_le32(dword11); -@@ -788,8 +796,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, +@@ -802,8 +810,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, c.rw.slba = cpu_to_le64(slba); slba += lbas; c.rw.length = cpu_to_le16(lbas - 1); @@ -184,7 +184,7 @@ index 0631b190b97..713f2b0b713 100644 -- 2.54.0 -From 0e9d37b398f25bcb05525910d515559c9090c0aa Mon Sep 17 00:00:00 2001 +From e4c3037baba91cf4c9330154e91ab5b7257de09f Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Fri, 8 May 2026 17:42:48 +0200 Subject: [PATCH 3/3] configs: enable NVMe @@ -199,10 +199,10 @@ Tested-by: Peter Robinson 1 file changed, 1 insertion(+) diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 69e8e72c5d7..acf44f44fc5 100644 +index cdcf05ea6db..5376a5e25ac 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig -@@ -41,6 +41,7 @@ CONFIG_MMC_SDHCI_SDMA=y +@@ -44,6 +44,7 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_MMC_SDHCI_BCMSTB=y CONFIG_BCMGENET=y diff --git a/Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch b/Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch deleted file mode 100644 index 3e9fce8..0000000 --- a/Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 8a88eb4883b16b84ad44db400ee2572966c2dd37 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Fri, 29 May 2026 13:11:06 +0100 -Subject: [PATCH] Revert "lmb: Reinstate access to memory above ram_top" - -This reverts commit a3075db94d49f415658bf7e961e1eae90d9abc33. ---- - lib/lmb.c | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git a/lib/lmb.c b/lib/lmb.c -index 8f12c6ad8e5..e2d9fe86c14 100644 ---- a/lib/lmb.c -+++ b/lib/lmb.c -@@ -611,6 +611,7 @@ static __maybe_unused void lmb_reserve_common_spl(void) - static void lmb_add_memory(void) - { - int i; -+ phys_addr_t bank_end; - phys_size_t size; - u64 ram_top = gd->ram_top; - struct bd_info *bd = gd->bd; -@@ -624,9 +625,23 @@ static void lmb_add_memory(void) - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size = bd->bi_dram[i].size; -+ bank_end = bd->bi_dram[i].start + size; - -- if (size) -+ if (size) { - lmb_add(bd->bi_dram[i].start, size); -+ -+ /* -+ * Reserve memory above ram_top as -+ * no-overwrite so that it cannot be -+ * allocated -+ */ -+ if (bd->bi_dram[i].start >= ram_top) -+ lmb_reserve(bd->bi_dram[i].start, size, -+ LMB_NOOVERWRITE); -+ else if (bank_end > ram_top) -+ lmb_reserve(ram_top, bank_end - ram_top, -+ LMB_NOOVERWRITE); -+ } - } - } - --- -2.54.0 - diff --git a/mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch b/mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch deleted file mode 100644 index ae37019..0000000 --- a/mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch +++ /dev/null @@ -1,167 +0,0 @@ -From patchwork Sat May 9 21:06:07 2026 -Content-Type: text/plain; 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- Sat, 09 May 2026 14:06:44 -0700 (PDT) -Received: from Liel.localdomain ([77.137.77.46]) - by smtp.gmail.com with ESMTPSA id - ffacd0b85a97d-45491f8d4c3sm13600391f8f.34.2026.05.09.14.06.43 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Sat, 09 May 2026 14:06:43 -0700 (PDT) -From: Liel@denx.de, Harel@denx.de, liel.harel@gmail.com -To: u-boot@lists.denx.de -Cc: Liel Harel , Matthias Brugger , - Peter Robinson , Peng Fan , - Jaehoon Chung , Tom Rini -Subject: [PATCH] mmc: bcm2835_sdhci: Parse generic MMC device tree properties -Date: Sun, 10 May 2026 00:06:07 +0300 -Message-ID: <20260509210607.51303-1-liel.harel@gmail.com> -X-Mailer: git-send-email 2.43.0 -MIME-Version: 1.0 -X-Mailman-Approved-At: Sun, 10 May 2026 03:42:13 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Liel Harel - -The bcm2835 SDHCI driver sets up the MMC host configuration via -sdhci_setup_cfg(), but does not parse generic MMC device tree -properties. - -As a result, properties such as bus-width are ignored. On Raspberry Pi -Compute Module 4, the eMMC node describes an 8-bit bus, but U-Boot -initialized the device as 4-bit. - -Call mmc_of_parse() before sdhci_setup_cfg() so that generic MMC -properties are folded into the host configuration before the MMC core -selects the bus width. - -Before this change, mmc info reported: - - Bus Speed: 52000000 - Bus Width: 4-bit - -After this change, mmc info reports: - - Bus Speed: 52000000 - Bus Width: 8-bit - -Tested on Raspberry Pi Compute Module 4 with onboard eMMC. - -Signed-off-by: Liel Harel ---- - drivers/mmc/bcm2835_sdhci.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c -index 655d9902dfa..efa4d14f5da 100644 ---- a/drivers/mmc/bcm2835_sdhci.c -+++ b/drivers/mmc/bcm2835_sdhci.c -@@ -219,6 +219,10 @@ static int bcm2835_sdhci_probe(struct udevice *dev) - host->mmc = &plat->mmc; - host->mmc->dev = dev; - -+ ret = mmc_of_parse(dev, &plat->cfg); -+ if (ret) -+ return ret; -+ - ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ); - if (ret) { - debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret); diff --git a/mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch b/mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch deleted file mode 100644 index bb7d1a9..0000000 --- a/mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch +++ /dev/null @@ -1,185 +0,0 @@ -From patchwork Tue May 12 12:24:35 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: =?utf-8?b?SmFuIMSMZXJtw6Fr?= -X-Patchwork-Id: 2236827 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - dkim=pass (2048-bit key; - secure) header.d=sairon.cz header.i=@sairon.cz header.a=rsa-sha256 - header.s=google header.b=QyEawGu/; - dkim-atps=neutral -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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[89.103.66.201]) - by smtp.gmail.com with ESMTPSA id - 5b1f17b1804b1-48e8e606020sm18361395e9.5.2026.05.12.05.25.06 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Tue, 12 May 2026 05:25:06 -0700 (PDT) -From: =?utf-8?b?SmFuIMSMZXJtw6Fr?= -To: u-boot@lists.denx.de -Cc: Thomas Fitzsimmons , Peng Fan , - Jaehoon Chung , Tom Rini , - Matthias Brugger , "Ivan T . Ivanov" , - =?utf-8?b?SmFuIMSMZXJtw6Fr?= -Subject: [PATCH] mmc: bcmstb: Fix non-removable check in bcm2712 init -Date: Tue, 12 May 2026 14:24:35 +0200 -Message-ID: <20260512122435.1118557-1-sairon@sairon.cz> -X-Mailer: git-send-email 2.54.0 -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -sdhci_brcmstb_init_2712() reads host->mmc->host_caps to decide whether -to force card-detect for a non-removable eMMC, or to route the CD signal -for a removable SD card. At the time this function runs from -sdhci_bcmstb_probe(), however, host->mmc->host_caps is still zero, that -field is only populated later by the MMC uclass, after the driver's -probe returns. mmc_of_parse() has already filled plat->cfg.host_caps -from the device tree by this point, so check that field instead. - -Without the fix, every BCM2712 SDHCI instance takes the else branch and -writes SDIO_CFG_SD_PIN_SEL = SDIO_CFG_SD_PIN_SEL_CARD (0x02), including -the non-removable eMMC on boards such as CM5 on Home Assistant Yellow. -The SDIO_CFG block lies outside the SDHCI core's reset scope, so this -value persists across SDHCI_RESET_ALL into the next stage. On the -BCM2712, having SD_PIN_SEL set to "SD" when the Linux kernel performs -its first set_power(MMC_POWER_UP) write racily prevents the SDHCI -POWER_ON bit from latching (see [1] for the whole backstory) - the -voltage bits stick but POWER_ON drops - which wedges the first CMD0 the -full 10 s software timeout. On Home Assistant Yellow this manifested as -a ~20 s eMMC probe delay on roughly one in two Linux boots when U-Boot -was the previous stage. Booting directly from the Pi firmware (no U-Boot -in between) left SD_PIN_SEL at its default and did not exhibit the race. - -Reading plat->cfg.host_caps lets init_2712 see the "non-removable" -property and take the correct branch, leaving SD_PIN_SEL untouched for -the eMMC. - -[1] https://github.com/home-assistant/operating-system/pull/3700#issuecomment-4430229511 - -Fixes: 10127cdbab64 ("mmc: bcmstb: Add support for bcm2712 SD controller") -Signed-off-by: Jan Čermák -Reviewed-by: Ivan T. Ivanov ---- - drivers/mmc/bcmstb_sdhci.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c -index 7bddbebb162..f27b84a6ee4 100644 ---- a/drivers/mmc/bcmstb_sdhci.c -+++ b/drivers/mmc/bcmstb_sdhci.c -@@ -56,7 +56,7 @@ struct sdhci_brcmstb_dev_priv { - - static int sdhci_brcmstb_init_2712(struct udevice *dev) - { -- struct sdhci_host *host = dev_get_priv(dev); -+ struct sdhci_bcmstb_plat *plat = dev_get_plat(dev); - void *cfg_regs; - u32 reg; - -@@ -65,8 +65,8 @@ static int sdhci_brcmstb_init_2712(struct udevice *dev) - if (!cfg_regs) - return -ENOENT; - -- if ((host->mmc->host_caps & MMC_CAP_NONREMOVABLE) || -- (host->mmc->host_caps & MMC_CAP_NEEDS_POLL)) { -+ if ((plat->cfg.host_caps & MMC_CAP_NONREMOVABLE) || -+ (plat->cfg.host_caps & MMC_CAP_NEEDS_POLL)) { - /* Force presence */ - reg = readl(cfg_regs + SDIO_CFG_CTRL); - reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; diff --git 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- u-boot@lists.denx.de -Cc: Peter Robinson -Subject: [PATCH] rpi_arm64: Enable MBEDTLS/LWIP/WGET and WGET_HTTPS -Date: Tue, 21 Apr 2026 15:11:38 +0100 -Message-ID: <20260421141156.359690-1-pbrobinson@gmail.com> -X-Mailer: git-send-email 2.53.0 -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -Enable LWIP and HTTPS on the Raspberry Pi arm64 platform to be able to -use it in the boot process. - -Signed-off-by: Peter Robinson -Reviewed-by: Matthias Brugger ---- - configs/rpi_arm64_defconfig | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 69e8e72c5d7..90048a418f6 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -11,6 +11,7 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 - CONFIG_PCI=y - CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y - CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -+CONFIG_EFI_HTTP_BOOT=y - CONFIG_BOOTSTD_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_FDT_SIMPLEFB=y -@@ -26,11 +27,13 @@ CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y - CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y -+CONFIG_CMD_SNTP=y -+CONFIG_WGET_HTTPS=y - CONFIG_CMD_EFIDEBUG=y - CONFIG_CMD_FS_UUID=y - CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" - CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y --CONFIG_TFTP_TSIZE=y -+CONFIG_NET_LWIP=y - CONFIG_DM_DMA=y - CONFIG_DFU_MMC=y - CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 -@@ -64,4 +67,5 @@ CONFIG_SYS_WHITE_ON_BLACK=y - CONFIG_VIDEO_BCM2835=y - CONFIG_CONSOLE_SCROLL_LINES=10 - CONFIG_PHYS_TO_BUS=y -+CONFIG_MBEDTLS_LIB=y - # CONFIG_HEXDUMP is not set diff --git a/sources b/sources index 9208a63..f5c0bc5 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.07-rc3.tar.bz2) = 1aef3d2c5c773244bbc3eb8f63543e84aa5a127c3dd58dabbb2714473f8233d299e610ddeb4e18f6c7b012ca8f3152688bc0ae3fcebc0867a7a7fae43018192d +SHA512 (u-boot-2026.07-rc5.tar.bz2) = b3cc2b46177dc7326f44ae856f07a5580aec03b0505fe9e6238028cc7d290beecf0f298f3145ed6b758af4a831fe588f236b7ebf20deed9206a84e535e73ffac diff --git a/uboot-tools.spec b/uboot-tools.spec index 6c1de18..f62d3da 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc3 +%global candidate rc5 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.07 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.4%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -35,8 +35,6 @@ Patch5: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch Patch6: uefi-enable-SetVariableRT-with-volotile-storage.patch # Enable UEFI HTTPS boot for all Fedora firmware Patch7: uefi-enable-https-boot-by-default.patch -# Upstream revert to fix boot on RPi -Patch8: Revert-lmb-Reinstate-access-to-memory-above-ram_top.patch # Device improvments # USB-PD improvements @@ -52,13 +50,8 @@ Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi Patch20: Fix-NVMe-not-only-on-Raspberry-Pi-5.patch -Patch21: ARM-RPi5-Enable-PCIe.patch -Patch22: rpi-enable-nvme.patch -Patch23: video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch -Patch24: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch -Patch25: mmc-bcm2835_sdhci-Parse-generic-MMC-device-tree-properties.patch -Patch26: rpi_arm64-Enable-MBEDTLS-LWIP-WGET-and-WGET_HTTPS.patch -Patch27: mmc-bcmstb-Fix-non-removable-check-in-bcm2712-init.patch +Patch21: rpi-enable-nvme.patch +Patch22: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch BuildRequires: bc BuildRequires: bison @@ -317,6 +310,12 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Jun 23 2026 Peter Robinson - 1:2026.07-0.4.rc5 +- Update to 2026.07 RC5 + +* Mon Jun 08 2026 Peter Robinson - 1:2026.07-0.3.rc4 +- Update to 2026.07 RC4 + * Fri May 29 2026 Peter Robinson - 1:2026.07-0.2.rc3 - Update to 2026.07 RC3 - Update U-Boot Project URL diff --git a/video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch b/video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch deleted file mode 100644 index f1fed33..0000000 --- a/video-arm-rpi-Add-brcm-bcm2712-hdmi0-compatible.patch +++ /dev/null @@ -1,152 +0,0 @@ -From patchwork Tue Apr 21 08:51:59 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Peter Robinson -X-Patchwork-Id: 2225594 -X-Patchwork-Delegate: pbrobinson@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: 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- (7.9.7.f.b.1.3.0.b.8.f.0.9.e.0.0.1.8.6.2.1.1.b.f.0.b.8.0.1.0.0.2.ip6.arpa. - [2001:8b0:fb11:2681:e9:f8b:31b:f797]) - by smtp.googlemail.com with ESMTPSA id - 5b1f17b1804b1-488fc18bccfsm319754095e9.8.2026.04.21.01.52.09 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Tue, 21 Apr 2026 01:52:09 -0700 (PDT) -From: Peter Robinson -To: Matthias Brugger , - u-boot@lists.denx.de -Cc: Peter Robinson -Subject: [PATCH] video: arm: rpi: Add brcm,bcm2712-hdmi0 compatible -Date: Tue, 21 Apr 2026 09:51:59 +0100 -Message-ID: <20260421085207.273703-1-pbrobinson@gmail.com> -X-Mailer: git-send-email 2.53.0 -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -The 'brcm,bcm2712-hdmi0' compatible string is used on RPi5. -There appears to be no change that impacts early boot output -on the display controller so add the RPi5 compatible string. - -Signed-off-by: Peter Robinson -Reviewed-by: Matthias Brugger ---- - drivers/video/bcm2835.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c -index 0c81e606622..0e0cc1979eb 100644 ---- a/drivers/video/bcm2835.c -+++ b/drivers/video/bcm2835.c -@@ -66,6 +66,7 @@ static int bcm2835_video_probe(struct udevice *dev) - static const struct udevice_id bcm2835_video_ids[] = { - { .compatible = "brcm,bcm2835-hdmi" }, - { .compatible = "brcm,bcm2711-hdmi0" }, -+ { .compatible = "brcm,bcm2712-hdmi0" }, - { .compatible = "brcm,bcm2708-fb" }, - #if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB) - { .compatible = "simple-framebuffer" }, From 0a5dac6b72e5d5563cd7fce4a1d73994f5d01c9a Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 23 Jun 2026 11:09:09 +0100 Subject: [PATCH 30/38] Build using openssl3 --- uboot-tools.spec | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index f62d3da..1e28f21 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -62,8 +62,8 @@ BuildRequires: gnutls-devel BuildRequires: libuuid-devel BuildRequires: make BuildRequires: ncurses-devel -BuildRequires: openssl-devel -BuildRequires: openssl-devel-engine +BuildRequires: openssl3-devel +BuildRequires: openssl3-devel-engine BuildRequires: perl-interpreter BuildRequires: python3-devel BuildRequires: python3-setuptools From edc90bc98acd74a744d49d523a86f260aa20708e Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 24 Jun 2026 13:33:49 +0100 Subject: [PATCH 31/38] Add openssl version conditionals --- uboot-tools.spec | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/uboot-tools.spec b/uboot-tools.spec index 1e28f21..570e75c 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -62,8 +62,13 @@ BuildRequires: gnutls-devel BuildRequires: libuuid-devel BuildRequires: make BuildRequires: ncurses-devel +%if 0%{?fedora} > 44 BuildRequires: openssl3-devel BuildRequires: openssl3-devel-engine +%else +BuildRequires: openssl-devel +BuildRequires: openssl-devel-engine +%endif BuildRequires: perl-interpreter BuildRequires: python3-devel BuildRequires: python3-setuptools From 9b96c029d85a3327582b27f18959ed8ccb638973 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 7 Jul 2026 07:33:54 +0100 Subject: [PATCH 32/38] Update to 2026.07 GA --- Fix-NVMe-not-only-on-Raspberry-Pi-5.patch | 687 +++++++++++++++++++--- rpi-enable-nvme.patch | 26 - uboot-tools.spec | 10 +- 3 files changed, 611 insertions(+), 112 deletions(-) delete mode 100644 rpi-enable-nvme.patch diff --git a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch index 67f0d6b..62f87ed 100644 --- a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch +++ b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch @@ -1,8 +1,84 @@ -From 9f926e07a9fc34d9c95fcc331867ee17d6a12105 Mon Sep 17 00:00:00 2001 -From: Torsten Duwe -Date: Fri, 8 May 2026 17:42:39 +0200 -Subject: [PATCH 1/3] core: Skip parent device nodes without a DT reference +From patchwork Mon Jul 6 17:21:47 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2265604 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) + (No client certificate requested) + by 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phobos.denx.de (Postfix) with ESMTPS id 9F24C846B4 + for ; Mon, 6 Jul 2026 19:21:49 +0200 (CEST) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id C934268B05; Mon, 6 Jul 2026 19:21:47 +0200 (CEST) +In-Reply-To: <20260706172028.C148E68BEB@verein.lst.de> +References: <20260706172028.C148E68BEB@verein.lst.de> +Subject: [PATCH v2 1/4] core: Skip parent device nodes without a DT reference when looking for dma-ranges +To: Neil Armstrong , + Andrew Goodbody , Bin Meng , + Simon Glass +Cc: Tom Rini , Matthias Brugger , + Peter Robinson , + Mattijs Korpershoek , + Marek Vasut , + Heiko Schocher , Svyatoslav Ryhel , + "Lucien.Jheng" , Rasmus Villemoes , + Martin Schwan , + "Markus Schneider-Pargmann (TI.com)" , + Prashant Kamble , + Denis Mukhin , Sughosh Ganu , + u-boot@lists.denx.de +Message-Id: <20260706172147.C934268B05@verein.lst.de> +Date: Mon, 6 Jul 2026 19:21:47 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe If a device node got created dynamically, there is no guarantee that the parent node has an associated device tree node which could specify dma @@ -45,35 +121,292 @@ index d365204ba11..b6d00cf4714 100644 return 0; /* --- -2.54.0 -From 960be63c0519239a2278cb5a6569398d0013f422 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 23 Jun 2026 10:55:17 +0100 -Subject: [PATCH 2/3] nvme: Fix missing address translation for PCIe inbound +From patchwork Mon Jul 6 17:21:50 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2265605 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gvB481pfXz1xqc + for ; Tue, 07 Jul 2026 03:22:00 +1000 (AEST) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 9A59684994; + Mon, 6 Jul 2026 19:21:55 +0200 (CEST) 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verein.lst.de (Postfix, from userid 2005) + id 464E868BEB; Mon, 6 Jul 2026 19:21:50 +0200 (CEST) +In-Reply-To: <20260706172028.C148E68BEB@verein.lst.de> +References: <20260706172028.C148E68BEB@verein.lst.de> +Subject: [PATCH v2 2/4] test: Add a unit test in phys_to_bus for dynamically + created device nodes +To: Neil Armstrong , + Andrew Goodbody , Bin Meng , + Simon Glass +Cc: Tom Rini , Matthias Brugger , + Peter Robinson , + Mattijs Korpershoek , + Marek Vasut , + Heiko Schocher , Svyatoslav Ryhel , + "Lucien.Jheng" , Rasmus Villemoes , + Martin Schwan , + "Markus Schneider-Pargmann (TI.com)" , + Prashant Kamble , + Denis Mukhin , Sughosh Ganu , + u-boot@lists.denx.de +Message-Id: <20260706172150.464E868BEB@verein.lst.de> +Date: Mon, 6 Jul 2026 19:21:50 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe + +In order to test whether device_get_dma_constraints() is now able to skip +device nodes without a DT association, temporarily remove those on 2 newly- +created nodes. + +Signed-off-by: Torsten Duwe +--- + +This test indeed makes a different whether the previous change is +applied or not, but *only* reliably for the non-flat-tree case (!?). +On the flat tree, it always fails after (reverse) applying it. + +Either the previous patch is incomplete, or, more likely, the test +assumptions here are not all valid. Suggestions welcome (especially +how to create device nodes from a device tree without a reference to +their origin ;-) + +--- + arch/sandbox/dts/test.dts | 9 +++++++++ + test/dm/phys2bus.c | 25 ++++++++++++++++++++++++- + 2 files changed, 33 insertions(+), 1 deletion(-) + +diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts +index 0887de4333b..1d92e85c739 100644 +--- a/arch/sandbox/dts/test.dts ++++ b/arch/sandbox/dts/test.dts +@@ -656,6 +656,15 @@ + subnode@0 { + compatible = "denx,u-boot-fdt-test"; + }; ++ bus@7 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "denx,u-boot-test-bus"; ++ ++ subnode@8 { ++ compatible = "denx,u-boot-fdt-test"; ++ }; ++ }; + }; + + mmio-bus@1 { +diff --git a/test/dm/phys2bus.c b/test/dm/phys2bus.c +index 67f33904943..858ed5410e2 100644 +--- a/test/dm/phys2bus.c ++++ b/test/dm/phys2bus.c +@@ -15,7 +15,8 @@ + + static int dm_test_phys_to_bus(struct unit_test_state *uts) + { +- struct udevice *dev; ++ struct udevice *dev, *pdev; ++ ofnode psave, nsave; + ofnode node; + + node = ofnode_path("/mmio-bus@0"); +@@ -31,6 +32,29 @@ static int dm_test_phys_to_bus(struct unit_test_state *uts) + ut_asserteq_addr((void*)0x1003ffffULL, (void*)dev_phys_to_bus(dev, 0x3ffff)); + ut_asserteq_addr((void*)0x3ffffULL, (void*)(ulong)dev_bus_to_phys(dev, 0x1003ffff)); + ++#if CONFIG_IS_ENABLED(OF_REAL) ++ /* dma-ranges are on the grandparent bus node, ++ * OF nodes neither here nor at parent ++ */ ++ node = ofnode_path("/mmio-bus@0/bus@7"); ++ ut_assert(ofnode_valid(node)); ++ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_BUS, node, &pdev)); ++ ++ /* pretend the devices were discovered dynamically and have no OF node */ ++ psave = pdev->node_; ++ pdev->node_.np = NULL; ++ node = ofnode_path("/mmio-bus@0/bus@7/subnode@8"); ++ ut_assert(ofnode_valid(node)); ++ nsave = dev->node_; ++ dev->node_.np = NULL; ++ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_FDT, node, &dev)); ++ ++ ut_asserteq_addr((void *)0x1003ffffULL, (void *)dev_phys_to_bus(dev, 0x3ffff)); ++ ut_asserteq_addr((void *)0x3ffffULL, (void *)(ulong)dev_bus_to_phys(dev, 0x1003ffff)); ++ ++ pdev->node_ = psave; ++ dev->node_ = nsave; ++#endif + return 0; + } + DM_TEST(dm_test_phys_to_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT); + +From patchwork Mon Jul 6 17:21:52 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2265606 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4gvB4H70Bdz1xqc + for ; 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+ dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id 5257168BFE; Mon, 6 Jul 2026 19:21:52 +0200 (CEST) +In-Reply-To: <20260706172028.C148E68BEB@verein.lst.de> +References: <20260706172028.C148E68BEB@verein.lst.de> +Subject: [PATCH v2 3/4] nvme: Fix missing address translation for PCIe inbound access +To: Neil Armstrong , + Andrew Goodbody , Bin Meng , + Simon Glass +Cc: Tom Rini , Matthias Brugger , + Peter Robinson , + Mattijs Korpershoek , + Marek Vasut , + Heiko Schocher , Svyatoslav Ryhel , + "Lucien.Jheng" , Rasmus Villemoes , + Martin Schwan , + "Markus Schneider-Pargmann (TI.com)" , + Prashant Kamble , + Denis Mukhin , Sughosh Ganu , + u-boot@lists.denx.de +Message-Id: <20260706172152.5257168BFE@verein.lst.de> +Date: Mon, 6 Jul 2026 19:21:52 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +From: Torsten Duwe U-Boot currently does not account for PCIe bridges with a non-zero inbound access offset when talking NVMe, it only works on platforms where this offset happens to be zero. This patch enhances the NVMe driver with the ability to also handle -these cases. +these cases. It also removes the unused function nvme_get_features(). Signed-off-by: Torsten Duwe Reviewed-by: Peter Robinson Tested-by: Peter Robinson -Signed-off-by: Peter Robinson --- - drivers/nvme/nvme.c | 32 ++++++++++++++++++++------------ - 1 file changed, 20 insertions(+), 12 deletions(-) +I tried to consistently use uintptr_t when doing arithmetic on pointers +and dma_addr_t to hold, well, DMA addresses ;) + +nvme_get_features mentions it's unused; so far it causes fruitless +maintenance work and causes dead extra bytes in das U-Boot binary. +It hasn't been neccessary for 9 years; one can revive it from git +once needed. + +--- + drivers/nvme/nvme.c | 71 +++++++++++++++++---------------------------- + drivers/nvme/nvme.h | 3 ++ + 2 files changed, 29 insertions(+), 45 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c -index 147a104149e..6f5f58e4088 100644 +index 147a104149e..54284c0242b 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c -@@ -12,6 +12,7 @@ +@@ -8,10 +8,10 @@ + #include + #include + #include +-#include #include #include #include @@ -81,127 +414,320 @@ index 147a104149e..6f5f58e4088 100644 #include #include #include -@@ -44,6 +45,13 @@ static inline void nvme_invalidate_cache_aligned(uintptr_t addr, int length) - invalidate_dcache_range(start_addr, end_addr); - } +@@ -101,6 +101,8 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + printf("Error: malloc prp_pool fail\n"); + return -ENOMEM; + } ++ dev->prp_pool_dma = dev_phys_to_bus(dev->udev, ++ (uintptr_t)dev->prp_pool); + dev->prp_entry_num = num_pages * (prps_per_page - 1) + 1; + } -+/* -+ * Convert a memory address to the value needed by the PCI device to -+ * access the given location, taking into account inbound window -+ * translations of PCI bridges: -+ */ -+#define DEV_ADDR(a) dev_phys_to_bus(dev->udev, (a)) -+ - static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) - { - int timeout; -@@ -108,8 +116,8 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, +@@ -108,8 +110,10 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, i = 0; while (nprps) { if ((i == (prps_per_page - 1)) && nprps > 1) { - *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + - page_size); -+ *(prp_pool + i) = cpu_to_le64(DEV_ADDR((ulong)prp_pool + -+ page_size)); ++ dma_addr_t prp_pool_dma = ++ dev_phys_to_bus(dev->udev, (uintptr_t)prp_pool); ++ *(prp_pool + i) = cpu_to_le64(prp_pool_dma + ++ page_size); i = 0; prp_pool = (u64 *)((uintptr_t)prp_pool + page_size); } -@@ -410,8 +418,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) +@@ -117,7 +121,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + dma_addr += page_size; + nprps--; + } +- *prp2 = (ulong)dev->prp_pool; ++ *prp2 = dev->prp_pool_dma; + + flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool + + num_pages * page_size); +@@ -258,11 +262,15 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, + nvmeq->cqes = (void *)memalign(4096, NVME_CQ_ALLOCATION); + if (!nvmeq->cqes) + goto free_nvmeq; ++ nvmeq->cq_dma_addr = dev_phys_to_bus(dev->udev, ++ (uintptr_t)nvmeq->cqes); + memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth)); + + nvmeq->sq_cmds = (void *)memalign(4096, NVME_SQ_SIZE(depth)); + if (!nvmeq->sq_cmds) + goto free_queue; ++ nvmeq->sq_dma_addr = dev_phys_to_bus(dev->udev, ++ (uintptr_t)nvmeq->sq_cmds); + memset((void *)nvmeq->sq_cmds, 0, NVME_SQ_SIZE(depth)); + + nvmeq->dev = dev; +@@ -410,8 +416,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; writel(aqa, &dev->bar->aqa); - nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); - nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); -+ nvme_writeq(DEV_ADDR((ulong)nvmeq->sq_cmds), &dev->bar->asq); -+ nvme_writeq(DEV_ADDR((ulong)nvmeq->cqes), &dev->bar->acq); ++ nvme_writeq(nvmeq->sq_dma_addr, &dev->bar->asq); ++ nvme_writeq(nvmeq->cq_dma_addr, &dev->bar->acq); result = nvme_enable_ctrl(dev); if (result) -@@ -437,7 +445,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, +@@ -437,7 +443,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, memset(&c, 0, sizeof(c)); c.create_cq.opcode = nvme_admin_create_cq; - c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); -+ c.create_cq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->cqes)); ++ c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); c.create_cq.cqid = cpu_to_le16(qid); c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); c.create_cq.cq_flags = cpu_to_le16(flags); -@@ -454,7 +462,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, +@@ -454,7 +460,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, memset(&c, 0, sizeof(c)); c.create_sq.opcode = nvme_admin_create_sq; - c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); -+ c.create_sq.prp1 = cpu_to_le64(DEV_ADDR((ulong)nvmeq->sq_cmds)); ++ c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); c.create_sq.sqid = cpu_to_le16(qid); c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); c.create_sq.sq_flags = cpu_to_le16(flags); -@@ -476,14 +484,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, - memset(&c, 0, sizeof(c)); - c.identify.opcode = nvme_admin_identify; - c.identify.nsid = cpu_to_le32(nsid); -- c.identify.prp1 = cpu_to_le64(dma_addr); -+ c.identify.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); +@@ -464,13 +470,13 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, + } - length -= (page_size - offset); - if (length <= 0) { - c.identify.prp2 = 0; - } else { - dma_addr += (page_size - offset); -- c.identify.prp2 = cpu_to_le64(dma_addr); -+ c.identify.prp2 = cpu_to_le64(DEV_ADDR(dma_addr)); - } + int nvme_identify(struct nvme_dev *dev, unsigned nsid, +- unsigned cns, dma_addr_t dma_addr) ++ unsigned cns, dma_addr_t cpu_addr) + { + struct nvme_command c; + u32 page_size = dev->page_size; ++ dma_addr_t dma_addr = dev_phys_to_bus(dev->udev, cpu_addr); + int offset = dma_addr & (page_size - 1); + int length = sizeof(struct nvme_id_ctrl); +- dma_addr_t orig_dma_addr = dma_addr; + int ret; + + memset(&c, 0, sizeof(c)); +@@ -488,49 +494,22 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, c.identify.cns = cpu_to_le32(cns); -@@ -508,7 +516,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, - memset(&c, 0, sizeof(c)); - c.features.opcode = nvme_admin_get_features; - c.features.nsid = cpu_to_le32(nsid); -- c.features.prp1 = cpu_to_le64(dma_addr); -+ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); - c.features.fid = cpu_to_le32(fid); - ret = nvme_submit_admin_cmd(dev, &c, result); -@@ -534,7 +542,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, +- nvme_invalidate_cache_aligned((uintptr_t)orig_dma_addr, ++ nvme_invalidate_cache_aligned((uintptr_t)cpu_addr, + sizeof(struct nvme_id_ctrl)); + + ret = nvme_submit_admin_cmd(dev, &c, NULL); + if (!ret) +- nvme_invalidate_cache_aligned((uintptr_t)orig_dma_addr, ++ nvme_invalidate_cache_aligned((uintptr_t)cpu_addr, + sizeof(struct nvme_id_ctrl)); + + return ret; + } + +-int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, +- dma_addr_t dma_addr, u32 *result) +-{ +- struct nvme_command c; +- int ret; +- +- memset(&c, 0, sizeof(c)); +- c.features.opcode = nvme_admin_get_features; +- c.features.nsid = cpu_to_le32(nsid); +- c.features.prp1 = cpu_to_le64(dma_addr); +- c.features.fid = cpu_to_le32(fid); +- +- ret = nvme_submit_admin_cmd(dev, &c, result); +- +- /* +- * TODO: Add some cache invalidation when a DMA buffer is involved +- * in the request, here and before the command gets submitted. The +- * buffer size varies by feature, also some features use a different +- * field in the command packet to hold the buffer address. +- * Section 5.21.1 (Set Features command) in the NVMe specification +- * details the buffer requirements for each feature. +- * +- * At the moment there is no user of this function. +- */ +- +- return ret; +-} +- + int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, +- dma_addr_t dma_addr, u32 *result) ++ dma_addr_t cpu_addr, u32 *result) + { + struct nvme_command c; ++ dma_addr_t dma_addr = dev_phys_to_bus(dev->udev, cpu_addr); memset(&c, 0, sizeof(c)); c.features.opcode = nvme_admin_set_features; -- c.features.prp1 = cpu_to_le64(dma_addr); -+ c.features.prp1 = cpu_to_le64(DEV_ADDR(dma_addr)); - c.features.fid = cpu_to_le32(fid); - c.features.dword11 = cpu_to_le32(dword11); +@@ -769,7 +748,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + u64 prp2; + u64 total_len = blkcnt << desc->log2blksz; + u64 temp_len = total_len; +- uintptr_t temp_buffer = (uintptr_t)buffer; ++ uintptr_t dma_addr = dev_phys_to_bus(udev, (uintptr_t)buffer); -@@ -802,8 +810,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + u64 slba = blknr; + u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); +@@ -797,19 +776,19 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + } + + if (nvme_setup_prps(dev, &prp2, +- lbas << ns->lba_shift, temp_buffer)) ++ lbas << ns->lba_shift, dma_addr)) + return -EIO; c.rw.slba = cpu_to_le64(slba); slba += lbas; c.rw.length = cpu_to_le16(lbas - 1); - c.rw.prp1 = cpu_to_le64(temp_buffer); -- c.rw.prp2 = cpu_to_le64(prp2); -+ c.rw.prp1 = cpu_to_le64(DEV_ADDR(temp_buffer)); -+ c.rw.prp2 = cpu_to_le64(DEV_ADDR(prp2)); ++ c.rw.prp1 = cpu_to_le64(dma_addr); + c.rw.prp2 = cpu_to_le64(prp2); status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], &c, NULL, IO_TIMEOUT); if (status) --- -2.54.0 + break; + temp_len -= (u32)lbas << ns->lba_shift; +- temp_buffer += lbas << ns->lba_shift; ++ dma_addr += lbas << ns->lba_shift; + } + + if (read) +@@ -884,6 +863,8 @@ int nvme_init(struct udevice *udev) + printf("Error: %s: Out of memory!\n", udev->name); + goto free_queue; + } ++ ++ ndev->prp_pool_dma = dev_phys_to_bus(udev, (uintptr_t)ndev->prp_pool); + ndev->prp_entry_num = MAX_PRP_POOL >> 3; + + ret = nvme_setup_io_queues(ndev); +diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h +index bc1d612dde4..7c6ed4d9b55 100644 +--- a/drivers/nvme/nvme.h ++++ b/drivers/nvme/nvme.h +@@ -619,6 +619,7 @@ struct nvme_dev { + u32 page_size; + u8 vwc; + u64 *prp_pool; ++ uintptr_t prp_pool_dma; + u32 prp_entry_num; + u32 nn; + }; +@@ -637,7 +638,9 @@ enum nvme_queue_id { + struct nvme_queue { + struct nvme_dev *dev; + struct nvme_command *sq_cmds; ++ dma_addr_t sq_dma_addr; + struct nvme_completion *cqes; ++ dma_addr_t cq_dma_addr; + u32 __iomem *q_db; + u16 q_depth; + s16 cq_vector; + +From patchwork Mon Jul 6 17:21:54 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Torsten Duwe +X-Patchwork-Id: 2265607 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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Mon, 6 Jul 2026 19:21:56 +0200 (CEST) +Authentication-Results: phobos.denx.de; + dmarc=fail (p=none dis=none) header.from=lst.de +Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de +Received: by verein.lst.de (Postfix, from userid 2005) + id B506B68CFE; Mon, 6 Jul 2026 19:21:54 +0200 (CEST) +In-Reply-To: <20260706172028.C148E68BEB@verein.lst.de> +References: <20260706172028.C148E68BEB@verein.lst.de> +Subject: [PATCH v2 4/4] configs: enable NVMe +To: Neil Armstrong , + Andrew Goodbody , Bin Meng , + Simon Glass +Cc: Tom Rini , Matthias Brugger , + Peter Robinson , + Mattijs Korpershoek , + Marek Vasut , + Heiko Schocher , Svyatoslav Ryhel , + "Lucien.Jheng" , Rasmus Villemoes , + Martin Schwan , + "Markus Schneider-Pargmann (TI.com)" , + Prashant Kamble , + Denis Mukhin , Sughosh Ganu , + u-boot@lists.denx.de +Message-Id: <20260706172154.B506B68CFE@verein.lst.de> +Date: Mon, 6 Jul 2026 19:21:54 +0200 (CEST) +From: duwe@lst.de (Torsten Duwe) +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean -From e4c3037baba91cf4c9330154e91ab5b7257de09f Mon Sep 17 00:00:00 2001 From: Torsten Duwe -Date: Fri, 8 May 2026 17:42:48 +0200 -Subject: [PATCH 3/3] configs: enable NVMe -Enable NVMe in the Raspberry Pi 64-Bit default config +Enable NVMe in the Raspberry Pi 64-Bit default config and scan for devices. Signed-off-by: Torsten Duwe Reviewed-by: Peter Robinson Tested-by: Peter Robinson --- - configs/rpi_arm64_defconfig | 1 + - 1 file changed, 1 insertion(+) + configs/rpi_arm64_defconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index cdcf05ea6db..5376a5e25ac 100644 +index cdcf05ea6db..fb0fdce1d7f 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig +@@ -16,7 +16,7 @@ CONFIG_BOOTSTD_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_FDT_SIMPLEFB=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="pci enum; usb start;" ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_SYS_PBSIZE=1049 + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set @@ -44,6 +44,7 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_MMC_SDHCI_BCMSTB=y @@ -210,6 +736,3 @@ index cdcf05ea6db..5376a5e25ac 100644 CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set --- -2.54.0 - diff --git a/rpi-enable-nvme.patch b/rpi-enable-nvme.patch deleted file mode 100644 index 52a1153..0000000 --- a/rpi-enable-nvme.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 94d8dfad9b381cd914fd11b2c6286084dd46b7a9 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sun, 29 Mar 2026 20:28:41 +0100 -Subject: [PATCH] rpi: enable nvme - -Signed-off-by: Peter Robinson ---- - configs/rpi_arm64_defconfig | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 38af5029403..ed4ae6ff522 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -15,7 +15,7 @@ CONFIG_BOOTSTD_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_FDT_SIMPLEFB=y - CONFIG_USE_PREBOOT=y --CONFIG_PREBOOT="pci enum; usb start;" -+CONFIG_PREBOOT="pci enum; usb start; nvme scan;" - CONFIG_SYS_PBSIZE=1049 - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set --- -2.54.0 - diff --git a/uboot-tools.spec b/uboot-tools.spec index 570e75c..704d499 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc5 +#global candidate rc0 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.07 -Release: 0.4%{?candidate:.%{candidate}}%{?dist} +Release: 1%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -50,8 +50,7 @@ Patch15: JetsonTX2-Fix-upstream-device-tree-naming.patch Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi Patch20: Fix-NVMe-not-only-on-Raspberry-Pi-5.patch -Patch21: rpi-enable-nvme.patch -Patch22: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch +Patch21: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch BuildRequires: bc BuildRequires: bison @@ -315,6 +314,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Tue Jul 07 2026 Peter Robinson - 1:2026.07-1 +- Update to 2026.07 GA + * Tue Jun 23 2026 Peter Robinson - 1:2026.07-0.4.rc5 - Update to 2026.07 RC5 From f3fed69d41fcf8672982208af847151c13ec98af Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 7 Jul 2026 09:11:01 +0100 Subject: [PATCH 33/38] Upload 2026.07 --- sources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sources b/sources index f5c0bc5..c76f13d 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.07-rc5.tar.bz2) = b3cc2b46177dc7326f44ae856f07a5580aec03b0505fe9e6238028cc7d290beecf0f298f3145ed6b758af4a831fe588f236b7ebf20deed9206a84e535e73ffac +SHA512 (u-boot-2026.07.tar.bz2) = 1292e1c15b75fde569efd1f983aa38e8db2e8b10b19de964886c4e80988922263bb862f5eb3b39f2051c5b28f43958f40b1f0e5c036de7fd862dc30b603cde5d From 00625a8b409e7926ea83f9db82a476dad5659dce Mon Sep 17 00:00:00 2001 From: Fedora Release Engineering Date: Fri, 17 Jul 2026 08:05:04 +0000 Subject: [PATCH 34/38] Rebuilt for https://fedoraproject.org/wiki/Fedora_45_Mass_Rebuild --- uboot-tools.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 704d499..24d2b11 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.07 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -314,6 +314,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Fri Jul 17 2026 Fedora Release Engineering - 1:2026.07-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_45_Mass_Rebuild + * Tue Jul 07 2026 Peter Robinson - 1:2026.07-1 - Update to 2026.07 GA From 8b33a3c4fee41f247e1934eb201320a945a8b855 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 30 Jul 2026 15:20:44 +0100 Subject: [PATCH 35/38] 2026.10 RC1 --- sources | 2 +- uboot-tools.spec | 15 +++++++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/sources b/sources index c76f13d..97f53d1 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2026.07.tar.bz2) = 1292e1c15b75fde569efd1f983aa38e8db2e8b10b19de964886c4e80988922263bb862f5eb3b39f2051c5b28f43958f40b1f0e5c036de7fd862dc30b603cde5d +SHA512 (u-boot-v2026.10-rc1.tar.bz2) = 0f0ac15caf6b430cd4d3e1dfa48b55c7e3de05eb8b81cd42308b250b7221c9ddd179e1b575ba1313ed2eb349263606efab13bbfa9dd983792a597ba8f6426919 diff --git a/uboot-tools.spec b/uboot-tools.spec index 24d2b11..e3d1c8b 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -#global candidate rc0 +%global candidate rc1 %if 0%{?rhel} %bcond_with toolsonly %else @@ -9,15 +9,15 @@ %global opensbi opensbi Name: uboot-tools -Version: 2026.07 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Version: 2026.10 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. License: GPL-2.0-or-later AND LicenseRef-Callaway-BSD AND LGPL-2.1-or-later AND LGPL-2.0-or-later URL: https://u-boot-project.org/ ExcludeArch: s390x -Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 +Source0: https://git.u-boot-project.org/u-boot/u-boot/-/archive/v%{version}%{?candidate:-%{candidate}}/u-boot-v%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: aarch64-boards Source2: riscv64-boards Source3: x86_64-boards @@ -41,7 +41,6 @@ Patch7: uefi-enable-https-boot-by-default.patch Patch10: USB-PD-TCPM-improvements.patch # Rockchips improvements Patch11: rockchip-Enable-preboot-start-for-pci-usb.patch -Patch12: rockchip-rk3568-nanopi-r5-Drop-duplicated-extra-sdhc.patch Patch13: rockchip-rk356x-Stop-overriding-sdhci-mmc-aliases.patch # Jetson fixes Patch14: p3450-fix-board.patch @@ -122,7 +121,7 @@ U-Boot firmware binaries for x86_64 boards %endif %prep -%autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} +%autosetup -p1 -n u-boot-v%{version}%{?candidate:-%{candidate}} cp %SOURCE1 %SOURCE2 %SOURCE3 . @@ -314,6 +313,10 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Thu Jul 30 2026 Peter Robinson - 1:2026.10-0.1.rc1 +- Update to 2026.10 RC1 +- Update source URL + * Fri Jul 17 2026 Fedora Release Engineering - 1:2026.07-2 - Rebuilt for https://fedoraproject.org/wiki/Fedora_45_Mass_Rebuild From 8f57e9bff641f4fa3d12d374fc4e44c61b51ef3f Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 12 Aug 2026 14:21:44 +0100 Subject: [PATCH 36/38] 2026.10 RC2 --- Fix-NVMe-not-only-on-Raspberry-Pi-5.patch | 333 ------------------ ...der-partition-and-set-boot_partition.patch | 256 ++++++++++++++ sources | 2 +- uboot-tools.spec | 8 +- 4 files changed, 263 insertions(+), 336 deletions(-) create mode 100644 rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch diff --git a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch index 62f87ed..a52ce84 100644 --- a/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch +++ b/Fix-NVMe-not-only-on-Raspberry-Pi-5.patch @@ -291,339 +291,6 @@ index 67f33904943..858ed5410e2 100644 } DM_TEST(dm_test_phys_to_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT); -From patchwork Mon Jul 6 17:21:52 2026 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Torsten Duwe -X-Patchwork-Id: 2265606 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Authentication-Results: legolas.ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384) - (No client certificate requested) - by legolas.ozlabs.org (Postfix) with ESMTPS id 4gvB4H70Bdz1xqc - for ; Tue, 07 Jul 2026 03:22:07 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 00AF0849BA; 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Mon, 6 Jul 2026 19:21:52 +0200 (CEST) -In-Reply-To: <20260706172028.C148E68BEB@verein.lst.de> -References: <20260706172028.C148E68BEB@verein.lst.de> -Subject: [PATCH v2 3/4] nvme: Fix missing address translation for PCIe inbound - access -To: Neil Armstrong , - Andrew Goodbody , Bin Meng , - Simon Glass -Cc: Tom Rini , Matthias Brugger , - Peter Robinson , - Mattijs Korpershoek , - Marek Vasut , - Heiko Schocher , Svyatoslav Ryhel , - "Lucien.Jheng" , Rasmus Villemoes , - Martin Schwan , - "Markus Schneider-Pargmann (TI.com)" , - Prashant Kamble , - Denis Mukhin , Sughosh Ganu , - u-boot@lists.denx.de -Message-Id: <20260706172152.5257168BFE@verein.lst.de> -Date: Mon, 6 Jul 2026 19:21:52 +0200 (CEST) -From: duwe@lst.de (Torsten Duwe) -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de -X-Virus-Status: Clean - -From: Torsten Duwe - -U-Boot currently does not account for PCIe bridges with a non-zero -inbound access offset when talking NVMe, it only works on platforms -where this offset happens to be zero. - -This patch enhances the NVMe driver with the ability to also handle -these cases. It also removes the unused function nvme_get_features(). - -Signed-off-by: Torsten Duwe -Reviewed-by: Peter Robinson -Tested-by: Peter Robinson ---- -I tried to consistently use uintptr_t when doing arithmetic on pointers -and dma_addr_t to hold, well, DMA addresses ;) - -nvme_get_features mentions it's unused; so far it causes fruitless -maintenance work and causes dead extra bytes in das U-Boot binary. -It hasn't been neccessary for 9 years; one can revive it from git -once needed. - ---- - drivers/nvme/nvme.c | 71 +++++++++++++++++---------------------------- - drivers/nvme/nvme.h | 3 ++ - 2 files changed, 29 insertions(+), 45 deletions(-) - -diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c -index 147a104149e..54284c0242b 100644 ---- a/drivers/nvme/nvme.c -+++ b/drivers/nvme/nvme.c -@@ -8,10 +8,10 @@ - #include - #include - #include --#include - #include - #include - #include -+#include - #include - #include - #include -@@ -101,6 +101,8 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, - printf("Error: malloc prp_pool fail\n"); - return -ENOMEM; - } -+ dev->prp_pool_dma = dev_phys_to_bus(dev->udev, -+ (uintptr_t)dev->prp_pool); - dev->prp_entry_num = num_pages * (prps_per_page - 1) + 1; - } - -@@ -108,8 +110,10 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, - i = 0; - while (nprps) { - if ((i == (prps_per_page - 1)) && nprps > 1) { -- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + -- page_size); -+ dma_addr_t prp_pool_dma = -+ dev_phys_to_bus(dev->udev, (uintptr_t)prp_pool); -+ *(prp_pool + i) = cpu_to_le64(prp_pool_dma + -+ page_size); - i = 0; - prp_pool = (u64 *)((uintptr_t)prp_pool + page_size); - } -@@ -117,7 +121,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, - dma_addr += page_size; - nprps--; - } -- *prp2 = (ulong)dev->prp_pool; -+ *prp2 = dev->prp_pool_dma; - - flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool + - num_pages * page_size); -@@ -258,11 +262,15 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, - nvmeq->cqes = (void *)memalign(4096, NVME_CQ_ALLOCATION); - if (!nvmeq->cqes) - goto free_nvmeq; -+ nvmeq->cq_dma_addr = dev_phys_to_bus(dev->udev, -+ (uintptr_t)nvmeq->cqes); - memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth)); - - nvmeq->sq_cmds = (void *)memalign(4096, NVME_SQ_SIZE(depth)); - if (!nvmeq->sq_cmds) - goto free_queue; -+ nvmeq->sq_dma_addr = dev_phys_to_bus(dev->udev, -+ (uintptr_t)nvmeq->sq_cmds); - memset((void *)nvmeq->sq_cmds, 0, NVME_SQ_SIZE(depth)); - - nvmeq->dev = dev; -@@ -410,8 +416,8 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) - dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; - - writel(aqa, &dev->bar->aqa); -- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); -- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); -+ nvme_writeq(nvmeq->sq_dma_addr, &dev->bar->asq); -+ nvme_writeq(nvmeq->cq_dma_addr, &dev->bar->acq); - - result = nvme_enable_ctrl(dev); - if (result) -@@ -437,7 +443,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, - - memset(&c, 0, sizeof(c)); - c.create_cq.opcode = nvme_admin_create_cq; -- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); -+ c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); - c.create_cq.cqid = cpu_to_le16(qid); - c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); - c.create_cq.cq_flags = cpu_to_le16(flags); -@@ -454,7 +460,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, - - memset(&c, 0, sizeof(c)); - c.create_sq.opcode = nvme_admin_create_sq; -- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); -+ c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); - c.create_sq.sqid = cpu_to_le16(qid); - c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); - c.create_sq.sq_flags = cpu_to_le16(flags); -@@ -464,13 +470,13 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, - } - - int nvme_identify(struct nvme_dev *dev, unsigned nsid, -- unsigned cns, dma_addr_t dma_addr) -+ unsigned cns, dma_addr_t cpu_addr) - { - struct nvme_command c; - u32 page_size = dev->page_size; -+ dma_addr_t dma_addr = dev_phys_to_bus(dev->udev, cpu_addr); - int offset = dma_addr & (page_size - 1); - int length = sizeof(struct nvme_id_ctrl); -- dma_addr_t orig_dma_addr = dma_addr; - int ret; - - memset(&c, 0, sizeof(c)); -@@ -488,49 +494,22 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, - - c.identify.cns = cpu_to_le32(cns); - -- nvme_invalidate_cache_aligned((uintptr_t)orig_dma_addr, -+ nvme_invalidate_cache_aligned((uintptr_t)cpu_addr, - sizeof(struct nvme_id_ctrl)); - - ret = nvme_submit_admin_cmd(dev, &c, NULL); - if (!ret) -- nvme_invalidate_cache_aligned((uintptr_t)orig_dma_addr, -+ nvme_invalidate_cache_aligned((uintptr_t)cpu_addr, - sizeof(struct nvme_id_ctrl)); - - return ret; - } - --int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, -- dma_addr_t dma_addr, u32 *result) --{ -- struct nvme_command c; -- int ret; -- -- memset(&c, 0, sizeof(c)); -- c.features.opcode = nvme_admin_get_features; -- c.features.nsid = cpu_to_le32(nsid); -- c.features.prp1 = cpu_to_le64(dma_addr); -- c.features.fid = cpu_to_le32(fid); -- -- ret = nvme_submit_admin_cmd(dev, &c, result); -- -- /* -- * TODO: Add some cache invalidation when a DMA buffer is involved -- * in the request, here and before the command gets submitted. The -- * buffer size varies by feature, also some features use a different -- * field in the command packet to hold the buffer address. -- * Section 5.21.1 (Set Features command) in the NVMe specification -- * details the buffer requirements for each feature. -- * -- * At the moment there is no user of this function. -- */ -- -- return ret; --} -- - int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, -- dma_addr_t dma_addr, u32 *result) -+ dma_addr_t cpu_addr, u32 *result) - { - struct nvme_command c; -+ dma_addr_t dma_addr = dev_phys_to_bus(dev->udev, cpu_addr); - - memset(&c, 0, sizeof(c)); - c.features.opcode = nvme_admin_set_features; -@@ -769,7 +748,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, - u64 prp2; - u64 total_len = blkcnt << desc->log2blksz; - u64 temp_len = total_len; -- uintptr_t temp_buffer = (uintptr_t)buffer; -+ uintptr_t dma_addr = dev_phys_to_bus(udev, (uintptr_t)buffer); - - u64 slba = blknr; - u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); -@@ -797,19 +776,19 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, - } - - if (nvme_setup_prps(dev, &prp2, -- lbas << ns->lba_shift, temp_buffer)) -+ lbas << ns->lba_shift, dma_addr)) - return -EIO; - c.rw.slba = cpu_to_le64(slba); - slba += lbas; - c.rw.length = cpu_to_le16(lbas - 1); -- c.rw.prp1 = cpu_to_le64(temp_buffer); -+ c.rw.prp1 = cpu_to_le64(dma_addr); - c.rw.prp2 = cpu_to_le64(prp2); - status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], - &c, NULL, IO_TIMEOUT); - if (status) - break; - temp_len -= (u32)lbas << ns->lba_shift; -- temp_buffer += lbas << ns->lba_shift; -+ dma_addr += lbas << ns->lba_shift; - } - - if (read) -@@ -884,6 +863,8 @@ int nvme_init(struct udevice *udev) - printf("Error: %s: Out of memory!\n", udev->name); - goto free_queue; - } -+ -+ ndev->prp_pool_dma = dev_phys_to_bus(udev, (uintptr_t)ndev->prp_pool); - ndev->prp_entry_num = MAX_PRP_POOL >> 3; - - ret = nvme_setup_io_queues(ndev); -diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h -index bc1d612dde4..7c6ed4d9b55 100644 ---- a/drivers/nvme/nvme.h -+++ b/drivers/nvme/nvme.h -@@ -619,6 +619,7 @@ struct nvme_dev { - u32 page_size; - u8 vwc; - u64 *prp_pool; -+ uintptr_t prp_pool_dma; - u32 prp_entry_num; - u32 nn; - }; -@@ -637,7 +638,9 @@ enum nvme_queue_id { - struct nvme_queue { - struct nvme_dev *dev; - struct nvme_command *sq_cmds; -+ dma_addr_t sq_dma_addr; - struct nvme_completion *cqes; -+ dma_addr_t cq_dma_addr; - u32 __iomem *q_db; - u16 q_depth; - s16 cq_vector; - From patchwork Mon Jul 6 17:21:54 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 diff --git a/rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch b/rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch new file mode 100644 index 0000000..6d54fa7 --- /dev/null +++ b/rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch @@ -0,0 +1,256 @@ +From patchwork Tue Aug 4 13:39:15 2026 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gregor Herburger +X-Patchwork-Id: 2280865 +X-Patchwork-Delegate: pbrobinson@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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After boot the +firmware sets 'partition' property in /chosen/bootloader. + +Copy the /chosen/bootloader node to the device tree. + +Set the env variable boot_partition accordingly to allow boards to +create a bootcmd based on the boot partition. + +Reviewed-by: Matthias Brugger +Signed-off-by: Gregor Herburger +--- +Changes in v3: +- Copy the complete '/chosen/bootloader' node instead of only the + partition property +- Link to v2: https://patch.msgid.link/20260803-tryboot2-v2-1-30c071f2ee15@linutronix.de + +Changes in v2: +- update Reviewed-by tag +--- + board/raspberrypi/rpi/rpi.c | 51 +++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 51 insertions(+) + + +--- +base-commit: baa64b2f892890f00a377eac4a3e685472bb56b5 +change-id: 20260803-tryboot2-8c5221376e5a + +Best regards, +-- +Gregor Herburger + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index 1da5df92351c..ba8a2c1ba4cf 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -480,6 +480,20 @@ static void set_serial_number(void) + env_set("serial#", serial_string); + } + ++static void set_boot_partition_fdt(void) ++{ ++ void *fdtp = (void *)gd->fdt_blob; ++ u32 partition; ++ ++ partition = fdt_getprop_u32_default(fdtp, "/chosen/bootloader", "partition", 1); ++ if (!partition) { ++ printf("Failed to the get partition property.\n"); ++ return; ++ } ++ ++ env_set_ulong("boot_partition", partition); ++} ++ + int misc_init_r(void) + { + set_fdt_addr(); +@@ -489,6 +503,7 @@ int misc_init_r(void) + set_board_info(); + #endif + set_serial_number(); ++ set_boot_partition_fdt(); + + return 0; + } +@@ -579,6 +594,39 @@ int board_fdt_blob_setup(void **fdtp) + return 0; + } + ++int copy_node_all_properties(void *dst, void *src, const char *path, const char *node) ++{ ++ int src_parent, dst_parent; ++ int src_node, dst_node; ++ int prop; ++ int len; ++ ++ src_parent = fdt_path_offset(src, path); ++ dst_parent = fdt_path_offset(dst, path); ++ if (src_parent < 0 || dst_parent < 0) ++ return -1; ++ ++ src_node = fdt_subnode_offset(src, src_parent, node); ++ if (src_node < 0) ++ return -1; ++ ++ dst_node = fdt_find_or_add_subnode(dst, dst_parent, node); ++ if (dst_node < 0) ++ return -1; ++ ++ fdt_for_each_property_offset(prop, src, src_node) { ++ const char *name; ++ const void *value = fdt_getprop_by_offset(src, prop, &name, &len); ++ ++ if (!value || !name) ++ continue; ++ ++ fdt_setprop(dst, dst_node, name, value, len); ++ } ++ ++ return 0; ++} ++ + int copy_property(void *dst, void *src, char *path, char *property) + { + int dst_offset, src_offset; +@@ -641,6 +689,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) + + /* copy uart clk as provided by the firmware */ + copy_property(fdt, fw_fdt, "/clocks/clk-uart", "clock-frequency"); ++ ++ /* Copy the bootloader node */ ++ copy_node_all_properties(fdt, fw_fdt, "/chosen", "bootloader"); + } + + int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/sources b/sources index 97f53d1..60f076d 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-v2026.10-rc1.tar.bz2) = 0f0ac15caf6b430cd4d3e1dfa48b55c7e3de05eb8b81cd42308b250b7221c9ddd179e1b575ba1313ed2eb349263606efab13bbfa9dd983792a597ba8f6426919 +SHA512 (u-boot-v2026.10-rc2.tar.bz2) = 96963ced3958d40ebd523db7a7949cbaae264b0d3ae6220287045ff9d15c9b7a54351e89415117e36f981a9316c1c6ebbd1403ec322fcf5e5fb9f93ac6c64aee diff --git a/uboot-tools.spec b/uboot-tools.spec index e3d1c8b..5c59be4 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc1 +%global candidate rc2 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.10 -Release: 0.1%{?candidate:.%{candidate}}%{?dist} +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -50,6 +50,7 @@ Patch16: Allwinner-fix-booting-on-a-number-of-devices.patch # RPi Patch20: Fix-NVMe-not-only-on-Raspberry-Pi-5.patch Patch21: raspberrypi-Add-quirk-for-RPi5-2Gb-rev-1.0.patch +Patch22: rpi-copy-chosen-bootloader-partition-and-set-boot_partition.patch BuildRequires: bc BuildRequires: bison @@ -313,6 +314,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Wed Aug 12 2026 Peter Robinson - 1:2026.10-0.2.rc2 +- Update to 2026.10 RC2 + * Thu Jul 30 2026 Peter Robinson - 1:2026.10-0.1.rc1 - Update to 2026.10 RC1 - Update source URL From d4df103e5c0e45535ca4903c08dc6f43bf0d5e31 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 13 Aug 2026 14:56:06 +0100 Subject: [PATCH 37/38] Add upstream patch for SWIG 4.5 builds --- ...d-SWIG-Python-2-compatibility-macros.patch | 234 ++++++++++++++++++ uboot-tools.spec | 2 + 2 files changed, 236 insertions(+) create mode 100644 pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch diff --git a/pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch b/pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch new file mode 100644 index 0000000..43f321f --- /dev/null +++ b/pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch @@ -0,0 +1,234 @@ +From patchwork Tue Aug 11 13:34:33 2026 +Content-Type: text/plain; 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+ dmarc=none (p=none dis=none) + header.from=est.tech +X-Mailman-Original-Authentication-Results: phobos.denx.de; spf=pass + smtp.mailfrom=jaipaul.cheernam@est.tech +X-Mailman-Original-Authentication-Results: phobos.denx.de; + dkim=pass (2048-bit key; + unprotected) header.d=est.tech header.i=@est.tech header.b="pqeWauqz"; + dkim-atps=neutral +X-Mailman-Original-Authentication-Results: dkim=none (message not signed) + header.d=none;dmarc=none action=none header.from=est.tech; +X-BeenThere: u-boot@lists.u-boot-project.org +X-Mailman-Version: 2.1.30 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.u-boot-project.org +Sender: "U-Boot" + +SWIG 4.5.0 removed Python 2 compatibility macros (PyInt_*, PyString_*) +from its runtime header pyhead.swg (see commit 79f7a2b7cb7d). Replace +them with their Python 3 C API equivalents: + +- PyString_FromString -> PyUnicode_FromString +- PyString_AsString -> PyBytes_AsString +- PyInt_AsLong -> PyLong_AsLong + +The replacements are safe since the macros were already aliased to +these exact functions in SWIG's Python 3 code path. + +This is a backport of dtc commit 5008d1d6a356 ("pylibfdt: Replace +removed SWIG Python 2 compatibility macros"). + +Signed-off-by: Jaipaul Cheernam +Reviewed-by: Jérémie Dautheribes +Tested-by: Jérémie Dautheribes +Signed-off-by: Peter Robinson +Reviewed-by: Peter Robinson +--- + scripts/dtc/pylibfdt/libfdt.i_shipped | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped +index e4659489..326a15c7 100644 +--- a/scripts/dtc/pylibfdt/libfdt.i_shipped ++++ b/scripts/dtc/pylibfdt/libfdt.i_shipped +@@ -1033,7 +1033,7 @@ typedef uint32_t fdt32_t; + PyObject *buff; + + if ($1) { +- resultobj = PyString_FromString( ++ resultobj = PyUnicode_FromString( + fdt_string(fdt1, fdt32_to_cpu($1->nameoff))); + buff = PyByteArray_FromStringAndSize( + (const char *)($1 + 1), fdt32_to_cpu($1->len)); +@@ -1064,13 +1064,13 @@ typedef uint32_t fdt32_t; + } + $1 = PyBytes_AsString($input); + %#else +- $1 = PyString_AsString($input); /* char *str */ ++ $1 = PyBytes_AsString($input); /* char *str */ + %#endif + } + + /* typemaps used for fdt_next_node() */ + %typemap(in, numinputs=1) int *depth (int depth) { +- depth = (int) PyInt_AsLong($input); ++ depth = (int) PyLong_AsLong($input); + $1 = &depth; + } + diff --git a/uboot-tools.spec b/uboot-tools.spec index 5c59be4..afe362a 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -35,6 +35,8 @@ Patch5: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch Patch6: uefi-enable-SetVariableRT-with-volotile-storage.patch # Enable UEFI HTTPS boot for all Fedora firmware Patch7: uefi-enable-https-boot-by-default.patch +# Upstream SWIG 4.5 fix. +Patch8: pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch # Device improvments # USB-PD improvements From e9007fae5e24248e1a7b728de70b57a5fc022e77 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 27 Aug 2026 14:33:04 +0100 Subject: [PATCH 38/38] 2026.10 RC3 --- ...d-SWIG-Python-2-compatibility-macros.patch | 234 ------------------ sources | 2 +- uboot-tools.spec | 9 +- 3 files changed, 6 insertions(+), 239 deletions(-) delete mode 100644 pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch diff --git a/pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch b/pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch deleted file mode 100644 index 43f321f..0000000 --- a/pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch +++ /dev/null @@ -1,234 +0,0 @@ -From patchwork Tue Aug 11 13:34:33 2026 -Content-Type: text/plain; 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- dmarc=none (p=none dis=none) - header.from=est.tech -X-Mailman-Original-Authentication-Results: phobos.denx.de; spf=pass - smtp.mailfrom=jaipaul.cheernam@est.tech -X-Mailman-Original-Authentication-Results: phobos.denx.de; - dkim=pass (2048-bit key; - unprotected) header.d=est.tech header.i=@est.tech header.b="pqeWauqz"; - dkim-atps=neutral -X-Mailman-Original-Authentication-Results: dkim=none (message not signed) - header.d=none;dmarc=none action=none header.from=est.tech; -X-BeenThere: u-boot@lists.u-boot-project.org -X-Mailman-Version: 2.1.30 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.u-boot-project.org -Sender: "U-Boot" - -SWIG 4.5.0 removed Python 2 compatibility macros (PyInt_*, PyString_*) -from its runtime header pyhead.swg (see commit 79f7a2b7cb7d). Replace -them with their Python 3 C API equivalents: - -- PyString_FromString -> PyUnicode_FromString -- PyString_AsString -> PyBytes_AsString -- PyInt_AsLong -> PyLong_AsLong - -The replacements are safe since the macros were already aliased to -these exact functions in SWIG's Python 3 code path. - -This is a backport of dtc commit 5008d1d6a356 ("pylibfdt: Replace -removed SWIG Python 2 compatibility macros"). - -Signed-off-by: Jaipaul Cheernam -Reviewed-by: Jérémie Dautheribes -Tested-by: Jérémie Dautheribes -Signed-off-by: Peter Robinson -Reviewed-by: Peter Robinson ---- - scripts/dtc/pylibfdt/libfdt.i_shipped | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped -index e4659489..326a15c7 100644 ---- a/scripts/dtc/pylibfdt/libfdt.i_shipped -+++ b/scripts/dtc/pylibfdt/libfdt.i_shipped -@@ -1033,7 +1033,7 @@ typedef uint32_t fdt32_t; - PyObject *buff; - - if ($1) { -- resultobj = PyString_FromString( -+ resultobj = PyUnicode_FromString( - fdt_string(fdt1, fdt32_to_cpu($1->nameoff))); - buff = PyByteArray_FromStringAndSize( - (const char *)($1 + 1), fdt32_to_cpu($1->len)); -@@ -1064,13 +1064,13 @@ typedef uint32_t fdt32_t; - } - $1 = PyBytes_AsString($input); - %#else -- $1 = PyString_AsString($input); /* char *str */ -+ $1 = PyBytes_AsString($input); /* char *str */ - %#endif - } - - /* typemaps used for fdt_next_node() */ - %typemap(in, numinputs=1) int *depth (int depth) { -- depth = (int) PyInt_AsLong($input); -+ depth = (int) PyLong_AsLong($input); - $1 = &depth; - } - diff --git a/sources b/sources index 60f076d..08618e7 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-v2026.10-rc2.tar.bz2) = 96963ced3958d40ebd523db7a7949cbaae264b0d3ae6220287045ff9d15c9b7a54351e89415117e36f981a9316c1c6ebbd1403ec322fcf5e5fb9f93ac6c64aee +SHA512 (u-boot-v2026.10-rc3.tar.bz2) = e993f5d78a1ac0eb11f00e3730ff23eb880e206036f78c3eb74852b846a23d59111b4b07f4ced2c88c61a8c1627036c3cc32717c0efcf819376c5cd0a34183d2 diff --git a/uboot-tools.spec b/uboot-tools.spec index afe362a..056cc94 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -%global candidate rc2 +%global candidate rc3 %if 0%{?rhel} %bcond_with toolsonly %else @@ -10,7 +10,7 @@ Name: uboot-tools Version: 2026.10 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.3%{?candidate:.%{candidate}}%{?dist} Epoch: 1 Summary: U-Boot utilities # Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. @@ -35,8 +35,6 @@ Patch5: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch Patch6: uefi-enable-SetVariableRT-with-volotile-storage.patch # Enable UEFI HTTPS boot for all Fedora firmware Patch7: uefi-enable-https-boot-by-default.patch -# Upstream SWIG 4.5 fix. -Patch8: pylibfdt-Replace-removed-SWIG-Python-2-compatibility-macros.patch # Device improvments # USB-PD improvements @@ -316,6 +314,9 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} %endif %changelog +* Thu Aug 27 2026 Peter Robinson - 1:2026.10-0.3.rc3 +- Update to 2026.10 RC3 + * Wed Aug 12 2026 Peter Robinson - 1:2026.10-0.2.rc2 - Update to 2026.10 RC2