Only enable CCWARN on arm64 and amd64

- Resolves: rhbz#2378999

Upstream tag: v5.040
Upstream commit: 51cdf52d

Commit authored by Packit automation (https://packit.dev/)

.gitignore

@@ -12,3 +12,4 @@ verilator-3.803.tgz
 /verilator-5.032.tar.gz
 /verilator-5.034.tar.gz
 /verilator-5.036.tar.gz
+/verilator-5.040.tar.gz

README.packit

@@ -1,3 +1,3 @@
 This repository is maintained by packit.
 https://packit.dev/
-The file was generated using packit 1.6.0.post1.dev2+gd5a7662a.
+The file was generated using packit 1.11.0.post1.dev7+gfdcdf3a32.

sources

@@ -1 +1 @@
-SHA512 (verilator-5.036.tar.gz) = ce80620f690eb1fc688bbf2d15bb1a559e733ed2183c1c1b890d55a5ec9e803aa065d1f46f92a6552cccb939115814ec3359b4a3f17b514c644d1ad7060a5bc3
+SHA512 (verilator-5.040.tar.gz) = 3997791963305f4556a8f3b87e050eba5ad9952c0eb041c5ac981276ef385219e5c162a01e1ec966e5e814a334caa4e92f8e939e9cfbc068b30935f5ee6e9804

verilator.spec

@@ -1,6 +1,12 @@
 # Universal build flags
 %bcond longtests 0
+
+# Only enable extended warnings on supported platforms
+%ifarch x86_64 aarch64
 %bcond ccwarn 1
+%else
+%bcond ccwarn 0
+%endif
 
 # tcmalloc and z3 are not available on EL
 %if 0%{?rhel}%{?centos}
@@ -16,7 +22,7 @@
 %bcond mold 0
 
 Name:           verilator
-Version:        5.036
+Version:        5.040
 Release:        %autorelease
 Summary:        A fast simulator for synthesizable Verilog
 License:        LGPL-3.0-only OR Artistic-2.0