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4 commits

Author SHA1 Message Date
Fedora Release Engineering
3627877d01 dist-git conversion 2010-07-29 15:13:19 +00:00
Bill Nottingham
9b87ea7f69 Fix typo that causes a failure to update the common directory. (releng
#2781)
2009-11-26 01:15:31 +00:00
Chitlesh GOORAH
454110f07d new package 2009-10-10 19:53:17 +00:00
6c6f22cf49 Initialize branch F-11 for wb_builder 2009-10-06 21:29:05 +00:00
7 changed files with 276 additions and 21 deletions

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1
.gitignore vendored Normal file
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@ -0,0 +1 @@
wb_builder-1.0.3.tar.gz

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@ -1,21 +0,0 @@
# Makefile for source rpm: wb_builder
# $Id$
NAME := wb_builder
SPECFILE = $(firstword $(wildcard *.spec))
define find-makefile-common
for d in common ../common ../../common ; do if [ -f $$d/Makefile.common ] ; then if [ -f $$d/CVS/Root -a -w $$/Makefile.common ] ; then cd $$d ; cvs -Q update ; fi ; echo "$$d/Makefile.common" ; break ; fi ; done
endef
MAKEFILE_COMMON := $(shell $(find-makefile-common))
ifeq ($(MAKEFILE_COMMON),)
# attept a checkout
define checkout-makefile-common
test -f CVS/Root && { cvs -Q -d $$(cat CVS/Root) checkout common && echo "common/Makefile.common" ; } || { echo "ERROR: I can't figure out how to checkout the 'common' module." ; exit -1 ; } >&2
endef
MAKEFILE_COMMON := $(shell $(checkout-makefile-common))
endif
include $(MAKEFILE_COMMON)

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@ -0,0 +1 @@
9bad12675121a7d09467ad847b79b539 wb_builder-1.0.3.tar.gz

95
wb_builder-args.patch Normal file
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@ -0,0 +1,95 @@
--- wishbone.pl 2009-08-30 11:36:15.520240129 +0200
+++ wishbone.pl_mod 2009-09-03 07:01:29.148541129 +0200
@@ -191,6 +191,7 @@
};
sub read_defines {
+my $arg = @ARGV;
$priority=0;
$masters=0;
$slaves=0;
@@ -225,10 +226,10 @@
if ($a =~ /^(interconnect)( *)(=)( *)(crossbarswitch|sharedbus)(;?)$/) {
$interconnect = $5; }
- if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($*)/) {
+ if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($arg)/) {
$signal_groups = $5; };
- if ($a =~ /^(use_cyc_sel)( *)(=)( *)([0-1])(;?)($*)/) {
+ if ($a =~ /^(use_cyc_sel)( *)(=)( *)([0-1])(;?)($arg)/) {
$use_cyc_sel = $5; };
if ($a =~ /^(mux_type)( *)(=)( *)(mux|andor|tristate)(;?)$/) {
@@ -237,7 +238,7 @@
if ($a =~ /^(optimize)( *)(=)( *)(speed|area);?$/) {
$optimize = $5; };
- if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits|granularity)( *)(=)( *)([0-9]+)(;?)($*)/) {
+ if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits|granularity)( *)(=)( *)([0-9]+)(;?)($arg)/) {
$dat_size = $5 if $1 eq 'dat_size';
$adr_size = $5 if $1 eq 'adr_size';
$tgd_bits = $5 if $1 eq 'tgd_bits';
@@ -246,20 +247,20 @@
$granularity = $5 if $1 eq 'granularity';
};
- if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($*)/) {
+ if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($arg)/) {
if ($3 eq "tga"){$rename_tga=$7};
if ($3 eq "tgc"){$rename_tgc=$7};
if ($3 eq "tgd"){$rename_tgd=$7};
};
# master port setup
- if ($a =~ /^(master)( *)([A-Za-z0-9_-]+)($*)/) {
+ if ($a =~ /^(master)( *)([A-Za-z0-9_-]+)($arg)/) {
if($1 eq "master") {
master_init($3);
};
$a = <FILE>;
- until ($a =~ /^(end master)($*)/) {
- if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($*)/) {
+ until ($a =~ /^(end master)($arg)/) {
+ if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($arg)/) {
$master[$masters]{"$2"}=$7;
if (($2 eq "rty_i") && ($7 == 1)) {
$rty_i++; };
@@ -273,23 +274,23 @@
if ($2 eq "priority") {
$priority += $7; };
}; #end if
- if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
+ if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($arg)/) {
$master[$masters]{"$2"}=$6; };
# priority for crossbarswitch
- if ($a =~ /^( *)(priority)(_)([0-9a-zA-Z_]*)( *)(=)( *)([0-9]*)(;?)($*)/) {
+ if ($a =~ /^( *)(priority)(_)([0-9a-zA-Z_]*)( *)(=)( *)([0-9]*)(;?)($arg)/) {
$master[$masters]{("priority_"."$4")}=$8; };
$a = <FILE>;
};
};
# slave port setup
- if ($a =~ /^(slave)( *)([A-Za-z0-9_-]+)($*)/) {
+ if ($a =~ /^(slave)( *)([A-Za-z0-9_-]+)($arg)/) {
if ($1 eq "slave") {
slave_init($3);
};
$a = <FILE>;
- until ($a =~ /^(end slave)($*)/) {
- if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3|cyc_i)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($*)/) {
+ until ($a =~ /^(end slave)($arg)/) {
+ if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3|cyc_i)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($arg)/) {
$slave[$slaves]{"$2"}=$7;
if (($2 eq "rty_o") && ($7 == 1)) {
$rty_o++; };
@@ -300,7 +301,7 @@
if (($2 eq "tga_i") && ($7 == 1)) {
$tga_i++; };
}; #end if
- if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
+ if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($arg)/) {
$slave[$slaves]{"$2"}=$6; };
$a = <FILE>;
};

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@ -0,0 +1,95 @@
--- wishbone.pl~ 2006-11-28 01:22:43.000000000 +0530
+++ wishbone.pl 2009-08-29 22:32:53.684609104 +0530
@@ -66,21 +66,24 @@
use Time::Local;
use Getopt::Long;
+use strict;
+use warnings;
+
# description: users manual
my $version='1.0.3';
my $infile = "wishbone.defines";
-my $outfile = wb;
+my $outfile = "wb";
my $a;
my $i=0;
my $j=0;
# default settings
-my $syscon=syscon;
-my $intercon=intercon;
+my $syscon="syscon";
+my $intercon="intercon";
my $target="generic";
-my $hdl=vhdl;
+my $hdl="vhdl";
my $ext=".vhd";
my $signal_groups=0;
my $comment="--";
@@ -121,7 +124,24 @@
my $amp=0;
my $asp=0;
my $del=0;
-my $i;
+#my $i;
+
+my @master;
+my @slave;
+my $frame;
+my $c;
+my $am;
+my $ind;
+my $tmp;
+my $depend;
+my $l;
+my $only_master;
+my $k;
+my $noGUI;
+my $genHeader;
+my $help;
+my $file = "";
+my $tmp1;
# open input file
#if (open(FILE,"<$file")) {
@@ -804,7 +824,8 @@
};
sub generate_defines {
- open(OUTFILE,"> $_[0]") or die "could not open $infile for writing";
+ $infile = $_[0];
+ open(OUTFILE,">$infile") or die "could not open $infile for writing";
printf OUTFILE "# Generated by PERL program wishbone.pl.\n";
printf OUTFILE "# File used as input for wishbone arbiter generation\n";
$tmp=localtime(time);
@@ -884,13 +905,13 @@
printf OUTFILE "%s\n%s Wishbone slaves:\n",$comment,$comment;
for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE "%s %s\n",$comment,$slave[$i]{"wbs"};
- if ($slave[$i]{"size"} ne ffffffff) {
+ if ($slave[$i]{"size"} ne "ffffffff") {
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr"},$slave[$i]{"size"}};
- if ($slave[$i]{"size1"} ne ffffffff) {
+ if ($slave[$i]{"size1"} ne "ffffffff") {
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr1"},$slave[$i]{"size1"}};
- if ($slave[$i]{"size2"} ne ffffffff) {
+ if ($slave[$i]{"size2"} ne "ffffffff") {
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr2"},$slave[$i]{"size2"}};
- if ($slave[$i]{"size3"} ne ffffffff) {
+ if ($slave[$i]{"size3"} ne "ffffffff") {
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr3"},$slave[$i]{"size3"}};
};
print OUTFILE "$comment---------------------------------------------------------------------------------------\n";
@@ -1933,7 +1954,8 @@
sub gen_optional{
my ($sig_name,$n_o,$n_i)=@_;
- my $i,$j;
+ my $i;
+ my $j;
return if ($n_o == 0) && ($n_i == 0);
print OUTFILE " -- $sig_name Slave -> Master [Optional]\n";

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wb_builder.spec Normal file
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@ -0,0 +1,84 @@
Name: wb_builder
Version: 1.0.3
Release: 2%{?dist}
Summary: Wishbone Bus Builder
Group: Applications/Engineering
License: GPLv2
URL: http://sourceforge.net/projects/fpgalibre/
Source0: http://download.sourceforge.net/sourceforge/fpgalibre/%{name}-%{version}.tar.gz
BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
# fixes some Perl strict warnings and errors
Patch0: wb_builder-strict-warnings.patch
Patch1: wb_builder-args.patch
BuildArch: noarch
%description
This package includes a HDL generator from a text description or via
GUI input for the Wishbone Bus.
The Wishbone Bus is an open source hardware computer bus intended
to let the parts of an integrated circuit communicate with each other.
The aim is to allow the connection of differing cores to each other
inside of a chip. The Wishbone Bus is used by many designs in the
OpenCores project.
%prep
%setup -q
%patch0 -p0 -b .perl-warnings
%patch1 -p0 -b .perl-args
# ---- Filtering Requires: ----
# In the perl script, "use IEEE.std_logic_1164.all" is meant
# to generate VHDL code and not for Perl
cat << \EOF > %{name}-req
#!/bin/sh
%{__perl_requires} $* |\
sed -e '/perl(IEEE.std_logic_1164.all)/d'
EOF
%global __perl_requires %{_builddir}/%{name}-%{version}/%{name}-req
chmod +x %{__perl_requires}
# ------------------------------------------
#fixing rpmlint warnings: file-not-utf8
for f in LEEME.txt README.txt ;
do
iconv -f iso8859-1 -t utf-8 $f > $f.conv
mv -f $f.conv $f
done
%build
%install
%{__rm} -rf %{buildroot}
install -d %{buildroot}%{_bindir}
install -pm 0755 wishbone.pl %{buildroot}%{_bindir}/wishbonebuilder
%clean
%{__rm} -rf %{buildroot}
%files
%defattr(-,root,root,-)
%doc LEEME.txt LICENSE README.txt users_manual.pdf
%{_bindir}/wishbonebuilder
%changelog
* Sun Aug 30 2009 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 1.0.3-2
- Added patch from Shakthi Kannan
- Patched broken arguments
* Sat Apr 25 2009 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 1.0.3-1
- Initial Package