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4 commits
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|---|---|---|---|
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3627877d01 | ||
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9b87ea7f69 | ||
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454110f07d | ||
| 6c6f22cf49 |
7 changed files with 276 additions and 21 deletions
1
.gitignore
vendored
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1
.gitignore
vendored
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@ -0,0 +1 @@
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wb_builder-1.0.3.tar.gz
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21
Makefile
21
Makefile
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@ -1,21 +0,0 @@
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# Makefile for source rpm: wb_builder
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# $Id$
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NAME := wb_builder
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SPECFILE = $(firstword $(wildcard *.spec))
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define find-makefile-common
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for d in common ../common ../../common ; do if [ -f $$d/Makefile.common ] ; then if [ -f $$d/CVS/Root -a -w $$/Makefile.common ] ; then cd $$d ; cvs -Q update ; fi ; echo "$$d/Makefile.common" ; break ; fi ; done
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endef
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MAKEFILE_COMMON := $(shell $(find-makefile-common))
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ifeq ($(MAKEFILE_COMMON),)
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# attept a checkout
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define checkout-makefile-common
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test -f CVS/Root && { cvs -Q -d $$(cat CVS/Root) checkout common && echo "common/Makefile.common" ; } || { echo "ERROR: I can't figure out how to checkout the 'common' module." ; exit -1 ; } >&2
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endef
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MAKEFILE_COMMON := $(shell $(checkout-makefile-common))
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endif
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include $(MAKEFILE_COMMON)
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1
sources
1
sources
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@ -0,0 +1 @@
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9bad12675121a7d09467ad847b79b539 wb_builder-1.0.3.tar.gz
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95
wb_builder-args.patch
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95
wb_builder-args.patch
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@ -0,0 +1,95 @@
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--- wishbone.pl 2009-08-30 11:36:15.520240129 +0200
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+++ wishbone.pl_mod 2009-09-03 07:01:29.148541129 +0200
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@@ -191,6 +191,7 @@
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};
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sub read_defines {
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+my $arg = @ARGV;
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$priority=0;
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$masters=0;
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$slaves=0;
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@@ -225,10 +226,10 @@
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if ($a =~ /^(interconnect)( *)(=)( *)(crossbarswitch|sharedbus)(;?)$/) {
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$interconnect = $5; }
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- if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($*)/) {
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+ if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($arg)/) {
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$signal_groups = $5; };
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- if ($a =~ /^(use_cyc_sel)( *)(=)( *)([0-1])(;?)($*)/) {
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+ if ($a =~ /^(use_cyc_sel)( *)(=)( *)([0-1])(;?)($arg)/) {
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$use_cyc_sel = $5; };
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if ($a =~ /^(mux_type)( *)(=)( *)(mux|andor|tristate)(;?)$/) {
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@@ -237,7 +238,7 @@
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if ($a =~ /^(optimize)( *)(=)( *)(speed|area);?$/) {
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$optimize = $5; };
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- if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits|granularity)( *)(=)( *)([0-9]+)(;?)($*)/) {
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+ if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits|granularity)( *)(=)( *)([0-9]+)(;?)($arg)/) {
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$dat_size = $5 if $1 eq 'dat_size';
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$adr_size = $5 if $1 eq 'adr_size';
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$tgd_bits = $5 if $1 eq 'tgd_bits';
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@@ -246,20 +247,20 @@
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$granularity = $5 if $1 eq 'granularity';
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};
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- if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($*)/) {
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+ if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($arg)/) {
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if ($3 eq "tga"){$rename_tga=$7};
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if ($3 eq "tgc"){$rename_tgc=$7};
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if ($3 eq "tgd"){$rename_tgd=$7};
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};
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# master port setup
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- if ($a =~ /^(master)( *)([A-Za-z0-9_-]+)($*)/) {
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+ if ($a =~ /^(master)( *)([A-Za-z0-9_-]+)($arg)/) {
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if($1 eq "master") {
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master_init($3);
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};
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$a = <FILE>;
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- until ($a =~ /^(end master)($*)/) {
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- if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($*)/) {
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+ until ($a =~ /^(end master)($arg)/) {
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+ if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($arg)/) {
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$master[$masters]{"$2"}=$7;
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if (($2 eq "rty_i") && ($7 == 1)) {
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$rty_i++; };
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@@ -273,23 +274,23 @@
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if ($2 eq "priority") {
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$priority += $7; };
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}; #end if
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- if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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+ if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($arg)/) {
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$master[$masters]{"$2"}=$6; };
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# priority for crossbarswitch
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- if ($a =~ /^( *)(priority)(_)([0-9a-zA-Z_]*)( *)(=)( *)([0-9]*)(;?)($*)/) {
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+ if ($a =~ /^( *)(priority)(_)([0-9a-zA-Z_]*)( *)(=)( *)([0-9]*)(;?)($arg)/) {
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$master[$masters]{("priority_"."$4")}=$8; };
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$a = <FILE>;
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};
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};
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# slave port setup
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- if ($a =~ /^(slave)( *)([A-Za-z0-9_-]+)($*)/) {
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+ if ($a =~ /^(slave)( *)([A-Za-z0-9_-]+)($arg)/) {
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if ($1 eq "slave") {
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slave_init($3);
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};
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$a = <FILE>;
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- until ($a =~ /^(end slave)($*)/) {
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- if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3|cyc_i)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($*)/) {
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+ until ($a =~ /^(end slave)($arg)/) {
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+ if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3|cyc_i)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($arg)/) {
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$slave[$slaves]{"$2"}=$7;
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if (($2 eq "rty_o") && ($7 == 1)) {
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$rty_o++; };
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@@ -300,7 +301,7 @@
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if (($2 eq "tga_i") && ($7 == 1)) {
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$tga_i++; };
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}; #end if
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- if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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+ if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($arg)/) {
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$slave[$slaves]{"$2"}=$6; };
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$a = <FILE>;
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};
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95
wb_builder-strict-warnings.patch
Normal file
95
wb_builder-strict-warnings.patch
Normal file
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@ -0,0 +1,95 @@
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--- wishbone.pl~ 2006-11-28 01:22:43.000000000 +0530
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+++ wishbone.pl 2009-08-29 22:32:53.684609104 +0530
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@@ -66,21 +66,24 @@
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use Time::Local;
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use Getopt::Long;
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+use strict;
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+use warnings;
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+
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# description: users manual
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my $version='1.0.3';
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my $infile = "wishbone.defines";
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-my $outfile = wb;
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+my $outfile = "wb";
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my $a;
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my $i=0;
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my $j=0;
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# default settings
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-my $syscon=syscon;
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-my $intercon=intercon;
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+my $syscon="syscon";
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+my $intercon="intercon";
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my $target="generic";
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-my $hdl=vhdl;
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+my $hdl="vhdl";
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my $ext=".vhd";
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my $signal_groups=0;
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my $comment="--";
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@@ -121,7 +124,24 @@
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my $amp=0;
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my $asp=0;
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my $del=0;
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-my $i;
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+#my $i;
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+
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+my @master;
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+my @slave;
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+my $frame;
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+my $c;
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+my $am;
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+my $ind;
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+my $tmp;
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+my $depend;
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+my $l;
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+my $only_master;
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+my $k;
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+my $noGUI;
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+my $genHeader;
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+my $help;
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+my $file = "";
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+my $tmp1;
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# open input file
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#if (open(FILE,"<$file")) {
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@@ -804,7 +824,8 @@
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};
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sub generate_defines {
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- open(OUTFILE,"> $_[0]") or die "could not open $infile for writing";
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+ $infile = $_[0];
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+ open(OUTFILE,">$infile") or die "could not open $infile for writing";
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printf OUTFILE "# Generated by PERL program wishbone.pl.\n";
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printf OUTFILE "# File used as input for wishbone arbiter generation\n";
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$tmp=localtime(time);
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@@ -884,13 +905,13 @@
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printf OUTFILE "%s\n%s Wishbone slaves:\n",$comment,$comment;
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for ($i=1; $i <= $slaves; $i++) {
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printf OUTFILE "%s %s\n",$comment,$slave[$i]{"wbs"};
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- if ($slave[$i]{"size"} ne ffffffff) {
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+ if ($slave[$i]{"size"} ne "ffffffff") {
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printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr"},$slave[$i]{"size"}};
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- if ($slave[$i]{"size1"} ne ffffffff) {
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+ if ($slave[$i]{"size1"} ne "ffffffff") {
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printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr1"},$slave[$i]{"size1"}};
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- if ($slave[$i]{"size2"} ne ffffffff) {
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+ if ($slave[$i]{"size2"} ne "ffffffff") {
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printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr2"},$slave[$i]{"size2"}};
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- if ($slave[$i]{"size3"} ne ffffffff) {
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+ if ($slave[$i]{"size3"} ne "ffffffff") {
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printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr3"},$slave[$i]{"size3"}};
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};
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print OUTFILE "$comment---------------------------------------------------------------------------------------\n";
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@@ -1933,7 +1954,8 @@
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sub gen_optional{
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my ($sig_name,$n_o,$n_i)=@_;
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- my $i,$j;
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+ my $i;
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+ my $j;
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return if ($n_o == 0) && ($n_i == 0);
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print OUTFILE " -- $sig_name Slave -> Master [Optional]\n";
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84
wb_builder.spec
Normal file
84
wb_builder.spec
Normal file
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@ -0,0 +1,84 @@
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Name: wb_builder
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Version: 1.0.3
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Release: 2%{?dist}
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Summary: Wishbone Bus Builder
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Group: Applications/Engineering
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License: GPLv2
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URL: http://sourceforge.net/projects/fpgalibre/
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Source0: http://download.sourceforge.net/sourceforge/fpgalibre/%{name}-%{version}.tar.gz
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BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
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# fixes some Perl strict warnings and errors
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Patch0: wb_builder-strict-warnings.patch
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Patch1: wb_builder-args.patch
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BuildArch: noarch
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%description
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This package includes a HDL generator from a text description or via
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GUI input for the Wishbone Bus.
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The Wishbone Bus is an open source hardware computer bus intended
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to let the parts of an integrated circuit communicate with each other.
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The aim is to allow the connection of differing cores to each other
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inside of a chip. The Wishbone Bus is used by many designs in the
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OpenCores project.
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%prep
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%setup -q
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%patch0 -p0 -b .perl-warnings
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%patch1 -p0 -b .perl-args
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# ---- Filtering Requires: ----
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# In the perl script, "use IEEE.std_logic_1164.all" is meant
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# to generate VHDL code and not for Perl
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cat << \EOF > %{name}-req
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#!/bin/sh
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%{__perl_requires} $* |\
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sed -e '/perl(IEEE.std_logic_1164.all)/d'
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EOF
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%global __perl_requires %{_builddir}/%{name}-%{version}/%{name}-req
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chmod +x %{__perl_requires}
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# ------------------------------------------
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#fixing rpmlint warnings: file-not-utf8
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for f in LEEME.txt README.txt ;
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do
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iconv -f iso8859-1 -t utf-8 $f > $f.conv
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mv -f $f.conv $f
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done
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%build
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%install
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%{__rm} -rf %{buildroot}
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install -d %{buildroot}%{_bindir}
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install -pm 0755 wishbone.pl %{buildroot}%{_bindir}/wishbonebuilder
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%clean
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%{__rm} -rf %{buildroot}
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%files
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%defattr(-,root,root,-)
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%doc LEEME.txt LICENSE README.txt users_manual.pdf
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%{_bindir}/wishbonebuilder
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%changelog
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* Sun Aug 30 2009 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 1.0.3-2
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- Added patch from Shakthi Kannan
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- Patched broken arguments
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* Sat Apr 25 2009 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 1.0.3-1
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- Initial Package
|
||||
Loading…
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