Fix up changelog for build

Signed-off-by: Justin M. Forbes <jforbes@fedoraproject.org>

0001-Correct-warning-with-gcc9.patch

@@ -1,35 +0,0 @@
-From 0de1315ee843713bafb9a59bc040a024f688c62a Mon Sep 17 00:00:00 2001
-From: Laura Abbott <labbott@redhat.com>
-Date: Wed, 23 Jan 2019 13:56:47 +0100
-Subject: [PATCH] Correct warning with gcc9
-
-Suggested from Arnd
-
-Signed-off-by: Laura Abbott <labbott@redhat.com>
----
- include/linux/module.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/include/linux/module.h b/include/linux/module.h
-index 8fa38d3e7538..f2a24b59cca4 100644
---- a/include/linux/module.h
-+++ b/include/linux/module.h
-@@ -129,13 +129,13 @@ extern void cleanup_module(void);
- #define module_init(initfn)					\
- 	static inline initcall_t __maybe_unused __inittest(void)		\
- 	{ return initfn; }					\
--	int init_module(void) __attribute__((alias(#initfn)));
-+	int init_module(void) __attribute__((cold, alias(#initfn)));
- 
- /* This is only required if you want to be unloadable. */
- #define module_exit(exitfn)					\
- 	static inline exitcall_t __maybe_unused __exittest(void)		\
- 	{ return exitfn; }					\
--	void cleanup_module(void) __attribute__((alias(#exitfn)));
-+	void cleanup_module(void) __attribute__((cold, alias(#exitfn)));
- 
- #endif
- 
--- 
-2.20.1
-

0001-Drop-that-for-now.patch

@@ -14,7 +14,7 @@ index f5b1d0d168e0..5f31107b22d1 100644
 @@ -430,7 +430,7 @@ KBUILD_AFLAGS   := -D__ASSEMBLY__ -fno-PIE
  KBUILD_CFLAGS   := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs \
  		   -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE \
- 		   -Werror-implicit-function-declaration -Werror=implicit-int \
+ 		   -Werror=implicit-function-declaration -Werror=implicit-int \
 -		   -Wno-format-security \
 +		   -Wno-format-security -Wno-address-of-packed-member \
  		   -std=gnu89

0001-drm-i915-Serialise-i915_active_acquire-with-__active.patch

@@ -0,0 +1,79 @@
+From bbca083de291a03ffe1a1eb0832a0d74f8b64898 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Thu, 5 Dec 2019 18:33:32 +0000
+Subject: [PATCH] drm/i915: Serialise i915_active_acquire() with
+ __active_retire()
+
+As __active_retire() does it's final atomic_dec() under the
+ref->tree_lock spinlock, in order to prevent ourselves from reusing the
+ref->cache and ref->tree as they are being destroyed, we need to
+serialise with the retirement during i915_active_acquire().
+
+[  +0.000005] kernel BUG at drivers/gpu/drm/i915/i915_active.c:157!
+[  +0.000011] invalid opcode: 0000 [#1] SMP
+[  +0.000004] CPU: 7 PID: 188 Comm: kworker/u16:4 Not tainted 5.4.0-rc8-03070-gac5e57322614 #89
+[  +0.000002] Hardware name: Razer Razer Blade Stealth 13 Late 2019/LY320, BIOS 1.02 09/10/2019
+[  +0.000082] Workqueue: events_unbound active_work [i915]
+[  +0.000059] RIP: 0010:__active_retire+0x115/0x120 [i915]
+[  +0.000003] Code: 75 28 48 8b 3d 8c 6e 1a 00 48 89 ee e8 e4 5f a5 c0 48 8b 44 24 10 65 48 33 04 25 28 00 00 00 75 0f 48 83 c4 18 5b 5d 41 5c c3 <0f> 0b 0f 0b 0f 0b e8 a0 90 87 c0 0f 1f 44 00 00 48 8b 3d 54 6e 1a
+[  +0.000002] RSP: 0018:ffffb833003f7e48 EFLAGS: 00010286
+[  +0.000003] RAX: ffff8d6e8d726d00 RBX: ffff8d6f9db4e840 RCX: 0000000000000000
+[  +0.000001] RDX: ffffffff82605930 RSI: ffff8d6f9adc4908 RDI: ffff8d6e96cefe28
+[  +0.000002] RBP: ffff8d6e96cefe00 R08: 0000000000000000 R09: ffff8d6f9ffe9a50
+[  +0.000002] R10: 0000000000000048 R11: 0000000000000018 R12: ffff8d6f9adc4930
+[  +0.000001] R13: ffff8d6f9e04fb00 R14: 0000000000000000 R15: ffff8d6f9adc4988
+[  +0.000002] FS:  0000000000000000(0000) GS:ffff8d6f9ffc0000(0000) knlGS:0000000000000000
+[  +0.000002] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[  +0.000002] CR2: 000055eb5a34cf10 CR3: 000000018d609002 CR4: 0000000000760ee0
+[  +0.000002] PKRU: 55555554
+[  +0.000001] Call Trace:
+[  +0.000010]  process_one_work+0x1aa/0x350
+[  +0.000004]  worker_thread+0x4d/0x3a0
+[  +0.000004]  kthread+0xfb/0x130
+[  +0.000004]  ? process_one_work+0x350/0x350
+[  +0.000003]  ? kthread_park+0x90/0x90
+[  +0.000005]  ret_from_fork+0x1f/0x40
+
+Reported-by: Kenneth Graunke <kenneth@whitecape.org>
+Fixes: c9ad602feabe ("drm/i915: Split i915_active.mutex into an irq-safe spinlock for the rbtree")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Cc: Kenneth Graunke <kenneth@whitecape.org>
+Cc: Matthew Auld <matthew.auld@intel.com>
+Tested-by: Kenneth Graunke <kenneth@whitecape.org>
+Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20191205183332.801237-1-chris@chris-wilson.co.uk
+---
+ drivers/gpu/drm/i915/i915_active.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
+index e3fcec4834c2..3d0edde84705 100644
+--- a/drivers/gpu/drm/i915/i915_active.c
++++ b/drivers/gpu/drm/i915/i915_active.c
+@@ -91,10 +91,9 @@ static void debug_active_init(struct i915_active *ref)
+
+ static void debug_active_activate(struct i915_active *ref)
+ {
+-	spin_lock_irq(&ref->tree_lock);
++	lockdep_assert_held(&ref->tree_lock);
+ 	if (!atomic_read(&ref->count)) /* before the first inc */
+ 		debug_object_activate(ref, &active_debug_desc);
+-	spin_unlock_irq(&ref->tree_lock);
+ }
+
+ static void debug_active_deactivate(struct i915_active *ref)
+@@ -419,8 +418,10 @@ int i915_active_acquire(struct i915_active *ref)
+ 	if (!atomic_read(&ref->count) && ref->active)
+ 		err = ref->active(ref);
+ 	if (!err) {
++		spin_lock_irq(&ref->tree_lock); /* vs __active_retire() */
+ 		debug_active_activate(ref);
+ 		atomic_inc(&ref->count);
++		spin_unlock_irq(&ref->tree_lock);
+ 	}
+
+ 	mutex_unlock(&ref->mutex);
+-- 
+2.24.1
+

0001-iio-Use-event-header-from-kernel-tree.patch

@@ -1,64 +0,0 @@
-From 0eadbb65c0026fb4eec89c54f6b48a0febd87f92 Mon Sep 17 00:00:00 2001
-From: Laura Abbott <labbott@redhat.com>
-Date: Fri, 9 Sep 2016 08:19:17 -0700
-Subject: [PATCH] iio: Use type header from kernel tree
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-To: Jonathan Cameron <jic23@kernel.org>
-To: Hartmut Knaack <knaack.h@gmx.de>
-To: Lars-Peter Clausen <lars@metafoo.de>
-To: Peter Meerwald-Stadler <pmeerw@pmeerw.net>
-Cc: linux-iio@vger.kernel.org
-Cc: linux-kernel@vger.kernel.org
-
-
-The iio tools have been updated as new event types have been added to
-the kernel. The tools currently use the standard system headers which
-means that the system may not have the newest defintitions. This leads
-to build failures when building newer tools on older hosts:
-
-gcc -Wall -g -D_GNU_SOURCE   -c -o iio_event_monitor.o
-iio_event_monitor.c
-iio_event_monitor.c:59:3: error: ‘IIO_UVINDEX’ undeclared here (not in a
-function)
-  [IIO_UVINDEX] = "uvindex",
-   ^~~~~~~~~~~
-iio_event_monitor.c:59:3: error: array index in initializer not of
-integer type
-iio_event_monitor.c:59:3: note: (near initialization for
-‘iio_chan_type_name_spec’)
-iio_event_monitor.c:97:3: error: ‘IIO_MOD_LIGHT_UV’ undeclared here (not
-in a function)
-  [IIO_MOD_LIGHT_UV] = "uv",
-   ^~~~~~~~~~~~~~~~
-iio_event_monitor.c:97:3: error: array index in initializer not of
-integer type
-iio_event_monitor.c:97:3: note: (near initialization for
-‘iio_modifier_names’)
-<builtin>: recipe for target 'iio_event_monitor.o' failed
-
-Switch to using the header from the kernel tree to ensure the newest
-defintions are always picked up.
-
-Signed-off-by: Laura Abbott <labbott@redhat.com>
----
- tools/iio/iio_event_monitor.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/tools/iio/iio_event_monitor.c b/tools/iio/iio_event_monitor.c
-index d9b7e0f..f02523d 100644
---- a/tools/iio/iio_event_monitor.c
-+++ b/tools/iio/iio_event_monitor.c
-@@ -26,7 +26,7 @@
- #include <sys/ioctl.h>
- #include "iio_utils.h"
- #include <linux/iio/events.h>
--#include <linux/iio/types.h>
-+#include "../../include/uapi/linux/iio/types.h"
- 
- static const char * const iio_chan_type_name_spec[] = {
- 	[IIO_VOLTAGE] = "voltage",
--- 
-2.7.4
-

0001-mm-kmemleak-skip-late_init-if-not-skip-disable.patch

@@ -0,0 +1,71 @@
+From 14d329da03ea1145efce866b127b10ea6390b5e1 Mon Sep 17 00:00:00 2001
+From: Murphy Zhou <jencce.kernel@gmail.com>
+Date: Sun, 29 Sep 2019 17:56:59 +0800
+Subject: [PATCH] mm/kmemleak: skip late_init if not skip disable
+
+Now if DEFAULT_OFF set to y, kmemleak_init will start the cleanup_work
+workqueue. Then late_init call will set kmemleak_initialized to 1, the
+cleaup workqueue will try to do cleanup, triggering:
+
+[24.738773] ==================================================================
+[24.742784] BUG: KASAN: global-out-of-bounds in __kmemleak_do_cleanup+0x166/0x180
+[24.744144] Key type ._fscrypt registered
+[24.745680] Read of size 8 at addr ffffffff88746c90 by task kworker/3:1/171
+[24.745687]
+[24.745697] CPU: 3 PID: 171 Comm: kworker/3:1 Not tainted 5.3.0-v5.3-12475-gcbafe18 #1
+[24.745701] Hardware name: Red Hat KVM, BIOS 0.5.1 01/01/2011
+[24.745710] Workqueue: events kmemleak_do_cleanup
+[24.745717] Call Trace:
+[24.745736]  dump_stack+0x7c/0xc0
+[24.745755]  print_address_description.constprop.4+0x1f/0x300
+[24.751562] Key type .fscrypt registered
+[24.754370]  __kasan_report.cold.8+0x76/0xb2
+[24.754388]  ? __kmemleak_do_cleanup+0x166/0x180
+[24.754407]  kasan_report+0xe/0x20
+[24.778543]  __kmemleak_do_cleanup+0x166/0x180
+[24.780795]  process_one_work+0x919/0x17d0
+[24.782929]  ? pwq_dec_nr_in_flight+0x320/0x320
+[24.785092]  worker_thread+0x87/0xb40
+[24.786948]  ? __kthread_parkme+0xc3/0x190
+[24.789217]  ? process_one_work+0x17d0/0x17d0
+[24.791414]  kthread+0x333/0x3f0
+[24.793031]  ? kthread_create_worker_on_cpu+0xc0/0xc0
+[24.795473]  ret_from_fork+0x3a/0x50
+[24.797303]
+[24.798091] The buggy address belongs to the variable:
+[24.800634]  mem_pool_free_count+0x10/0x40
+[24.802656]
+[24.803434] Memory state around the buggy address:
+[24.805793]  ffffffff88746b80: 04 fa fa fa fa fa fa fa 00 00 00 00 00 00 00 00
+[24.809177]  ffffffff88746c00: 00 fa fa fa fa fa fa fa 00 00 fa fa fa fa fa fa
+[24.812407] >ffffffff88746c80: 04 fa fa fa fa fa fa fa 00 00 fa fa fa fa fa fa
+[24.815638]                          ^
+[24.817372]  ffffffff88746d00: 00 00 fa fa fa fa fa fa 00 00 00 00 00 00 00 00
+[24.820740]  ffffffff88746d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+[24.824021] ==================================================================
+
+Fixes: c5665868183f ("mm: kmemleak: use the memory pool for early allocations")
+Signed-off-by: Murphy Zhou <jencce.kernel@gmail.com>
+---
+ mm/kmemleak.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/mm/kmemleak.c b/mm/kmemleak.c
+index 03a8d84badad..b9baf617fe35 100644
+--- a/mm/kmemleak.c
++++ b/mm/kmemleak.c
+@@ -1946,6 +1946,11 @@ void __init kmemleak_init(void)
+  */
+ static int __init kmemleak_late_init(void)
+ {
++	if (!kmemleak_skip_disable) {
++		kmemleak_disable();
++		return 0;
++	}
++
+ 	kmemleak_initialized = 1;
+ 
+ 	debugfs_create_file("kmemleak", 0644, NULL, NULL, &kmemleak_fops);
+-- 
+2.21.0
+

0001-platform-x86-sony-laptop-SNC-calls-should-handle-BUF.patch

@@ -0,0 +1,114 @@
+From 47828d22539f76c8c9dcf2a55f18ea3a8039d8ef Mon Sep 17 00:00:00 2001
+From: Mattia Dongili <malattia@linux.it>
+Date: Fri, 8 May 2020 09:14:04 +0900
+Subject: [PATCH] platform/x86: sony-laptop: SNC calls should handle BUFFER
+ types
+
+After commit 6d232b29cfce ("ACPICA: Dispatcher: always generate buffer
+objects for ASL create_field() operator") ACPICA creates buffers even
+when new fields are small enough to fit into an integer.
+Many SNC calls counted on the old behaviour.
+Since sony-laptop already handles the INTEGER/BUFFER case in
+sony_nc_buffer_call, switch sony_nc_int_call to use its more generic
+function instead.
+
+Fixes: 6d232b29cfce ("ACPICA: Dispatcher: always generate buffer objects for ASL create_field() operator")
+Reported-by: Dominik Mierzejewski <dominik@greysector.net>
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=207491
+Reported-by: William Bader <williambader@hotmail.com>
+Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1830150
+Signed-off-by: Mattia Dongili <malattia@linux.it>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+---
+ drivers/platform/x86/sony-laptop.c | 53 +++++++++++++-----------------
+ 1 file changed, 23 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c
+index 51309f7ceede..6932cd11e660 100644
+--- a/drivers/platform/x86/sony-laptop.c
++++ b/drivers/platform/x86/sony-laptop.c
+@@ -757,33 +757,6 @@ static union acpi_object *__call_snc_method(acpi_handle handle, char *method,
+ 	return result;
+ }
+ 
+-static int sony_nc_int_call(acpi_handle handle, char *name, int *value,
+-		int *result)
+-{
+-	union acpi_object *object = NULL;
+-	if (value) {
+-		u64 v = *value;
+-		object = __call_snc_method(handle, name, &v);
+-	} else
+-		object = __call_snc_method(handle, name, NULL);
+-
+-	if (!object)
+-		return -EINVAL;
+-
+-	if (object->type != ACPI_TYPE_INTEGER) {
+-		pr_warn("Invalid acpi_object: expected 0x%x got 0x%x\n",
+-				ACPI_TYPE_INTEGER, object->type);
+-		kfree(object);
+-		return -EINVAL;
+-	}
+-
+-	if (result)
+-		*result = object->integer.value;
+-
+-	kfree(object);
+-	return 0;
+-}
+-
+ #define MIN(a, b)	(a > b ? b : a)
+ static int sony_nc_buffer_call(acpi_handle handle, char *name, u64 *value,
+ 		void *buffer, size_t buflen)
+@@ -795,17 +768,20 @@ static int sony_nc_buffer_call(acpi_handle handle, char *name, u64 *value,
+ 	if (!object)
+ 		return -EINVAL;
+ 
+-	if (object->type == ACPI_TYPE_BUFFER) {
++	if (!buffer) {
++		/* do nothing */
++	} else if (object->type == ACPI_TYPE_BUFFER) {
+ 		len = MIN(buflen, object->buffer.length);
++		memset(buffer, 0, buflen);
+ 		memcpy(buffer, object->buffer.pointer, len);
+ 
+ 	} else if (object->type == ACPI_TYPE_INTEGER) {
+ 		len = MIN(buflen, sizeof(object->integer.value));
++		memset(buffer, 0, buflen);
+ 		memcpy(buffer, &object->integer.value, len);
+ 
+ 	} else {
+-		pr_warn("Invalid acpi_object: expected 0x%x got 0x%x\n",
+-				ACPI_TYPE_BUFFER, object->type);
++		pr_warn("Unexpected acpi_object: 0x%x\n", object->type);
+ 		ret = -EINVAL;
+ 	}
+ 
+@@ -813,6 +789,23 @@ static int sony_nc_buffer_call(acpi_handle handle, char *name, u64 *value,
+ 	return ret;
+ }
+ 
++static int sony_nc_int_call(acpi_handle handle, char *name, int *value, int
++		*result)
++{
++	int ret;
++
++	if (value) {
++		u64 v = *value;
++
++		ret = sony_nc_buffer_call(handle, name, &v, result,
++				sizeof(*result));
++	} else {
++		ret =  sony_nc_buffer_call(handle, name, NULL, result,
++				sizeof(*result));
++	}
++	return ret;
++}
++
+ struct sony_nc_handles {
+ 	u16 cap[0x10];
+ 	struct device_attribute devattr;
+-- 
+2.26.2
+

0001-pwm-lpss-Fix-get_state-runtime-pm-reference-handling.patch

@@ -0,0 +1,100 @@
+From 3666fb55d53fb40f75ec4d665416fed1a714ef09 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Tue, 12 May 2020 00:39:24 +0200
+Subject: [PATCH] pwm: lpss: Fix get_state runtime-pm reference handling
+
+Before commit cfc4c189bc70 ("pwm: Read initial hardware state at request
+time"), a driver's get_state callback would get called once per PWM from
+pwmchip_add().
+
+pwm-lpss' runtime-pm code was relying on this, getting a runtime-pm ref for
+PWMs which are enabled at probe time from within its get_state callback,
+before enabling runtime-pm.
+
+The change to calling get_state at request time causes a number of
+problems:
+
+1. PWMs enabled at probe time may get runtime suspended before they are
+requested, causing e.g. a LCD backlight controlled by the PWM to turn off.
+
+2. When the request happens when the PWM has been runtime suspended, the
+ctrl register will read all 1 / 0xffffffff, causing get_state to store
+bogus values in the pwm_state.
+
+3. get_state was using an async pm_runtime_get() call, because it assumed
+that runtime-pm has not been enabled yet. If shortly after the request an
+apply call is made, then the pwm_lpss_is_updating() check may trigger
+because the resume triggered by the pm_runtime_get() call is not complete
+yet, so the ctrl register still reads all 1 / 0xffffffff.
+
+This commit fixes these issues by moving the initial pm_runtime_get() call
+for PWMs which are enabled at probe time to the pwm_lpss_probe() function;
+and by making get_state take a runtime-pm ref before reading the ctrl reg.
+
+BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1828927
+Fixes: cfc4c189bc70 ("pwm: Read initial hardware state at request time")
+Cc: stable@vger.kernel.org
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Upstream Status: https://lore.kernel.org/linux-acpi/5f15f6bc-8650-d86e-893f-0d41557c57c7@redhat.com/
+---
+ drivers/pwm/pwm-lpss.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
+index 75bbfe5f3bc2..9d965ffe66d1 100644
+--- a/drivers/pwm/pwm-lpss.c
++++ b/drivers/pwm/pwm-lpss.c
+@@ -158,7 +158,6 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	return 0;
+ }
+ 
+-/* This function gets called once from pwmchip_add to get the initial state */
+ static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ 			       struct pwm_state *state)
+ {
+@@ -167,6 +166,8 @@ static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	unsigned long long base_unit, freq, on_time_div;
+ 	u32 ctrl;
+ 
++	pm_runtime_get_sync(chip->dev);
++
+ 	base_unit_range = BIT(lpwm->info->base_unit_bits);
+ 
+ 	ctrl = pwm_lpss_read(pwm);
+@@ -187,8 +188,7 @@ static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	state->polarity = PWM_POLARITY_NORMAL;
+ 	state->enabled = !!(ctrl & PWM_ENABLE);
+ 
+-	if (state->enabled)
+-		pm_runtime_get(chip->dev);
++	pm_runtime_put(chip->dev);
+ }
+ 
+ static const struct pwm_ops pwm_lpss_ops = {
+@@ -202,7 +202,8 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
+ {
+ 	struct pwm_lpss_chip *lpwm;
+ 	unsigned long c;
+-	int ret;
++	int i, ret;
++	u32 ctrl;
+ 
+ 	if (WARN_ON(info->npwm > MAX_PWMS))
+ 		return ERR_PTR(-ENODEV);
+@@ -232,6 +233,12 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
+ 		return ERR_PTR(ret);
+ 	}
+ 
++	for (i = 0; i < lpwm->info->npwm; i++) {
++		ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
++		if (ctrl & PWM_ENABLE)
++			pm_runtime_get(dev);
++	}
++
+ 	return lpwm;
+ }
+ EXPORT_SYMBOL_GPL(pwm_lpss_probe);
+-- 
+2.26.2
+

0001-s390-jump_label-Correct-asm-contraint.patch

@@ -1,63 +0,0 @@
-From b0b46a5b622fdbe69207675c5d50b77cb8ae43b7 Mon Sep 17 00:00:00 2001
-From: Heiko Carstens <heiko.carstens@de.ibm.com>
-Date: Tue, 5 Feb 2019 13:43:49 +0100
-Subject: [PATCH] s390/jump_label: Correct asm contraint
-
-On Tue, Jan 29, 2019 at 08:25:58AM +0100, Laura Abbott wrote:
-> On 1/23/19 5:24 AM, Heiko Carstens wrote:
-> >On Wed, Jan 23, 2019 at 01:55:13PM +0100, Laura Abbott wrote:
-> >>There's a build failure with gcc9:
-> >>
-> >>  ./arch/s390/include/asm/jump_label.h: Assembler messages:
-> >>  ./arch/s390/include/asm/jump_label.h:23: Error: bad expression
-> >>  ./arch/s390/include/asm/jump_label.h:23: Error: junk at end of line, first unrecognized character is `r'
-> >>  make[1]: *** [scripts/Makefile.build:277: init/main.o] Error 1
-...
-> I've had to turn off s390 in Fedora until this gets fixed :(
-
-Laura, the patch below should fix this (temporarily). If possible,
-could you give it a try? It seems to work for me.
-
-rom 4067027c2ccc8d3f1dc3bb19fe2d00da0c65bcd8 Mon Sep 17 00:00:00 2001
-From: Heiko Carstens <heiko.carstens@de.ibm.com>
-Date: Tue, 5 Feb 2019 13:21:56 +0100
-Subject: [PATCH] s390: disable section anchors
-
-Disable section anchors to allow to compile with the current gcc 9
-experimental version. The section anchors is a new feature for s390
-with gcc 9, however it breaks our current usage of the 'X' constraint
-within the asm goto construct within our jump label implementation.
-
-Fixing this seems to be non-trivial, therefore (hopefully) temporarily
-disable section anchors. We will hopefully have a better solution
-before gcc 9 is released, so that this can be removed again.
-
-Reported-by: Laura Abbott <labbott@redhat.com>
-Suggested-by: Ilya Leoshkevich <iii@linux.ibm.com>
-Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
----
- arch/s390/Makefile | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/s390/Makefile b/arch/s390/Makefile
-index e21053e5e0da..1eac75bc3a29 100644
---- a/arch/s390/Makefile
-+++ b/arch/s390/Makefile
-@@ -62,6 +62,14 @@ cflags-y += -Wa,-I$(srctree)/arch/$(ARCH)/include
- #
- cflags-$(CONFIG_FRAME_POINTER) += -fno-optimize-sibling-calls
- 
-+#
-+# Disable section anchors. This gcc 9 feature currently breaks the 'X'
-+# constraint like it is used in the asm goto construct.
-+#
-+ifeq ($(call cc-option-yn,-fno-section-anchors),y)
-+cflags-y += -fno-section-anchors
-+endif
-+
- ifeq ($(call cc-option-yn,-mpacked-stack),y)
- cflags-$(CONFIG_PACK_STACK)  += -mpacked-stack -D__PACK_STACK
- aflags-$(CONFIG_PACK_STACK)  += -D__PACK_STACK
--- 
-2.20.1
-

0001-xfs-add-agf-freeblocks-verify-in-xfs_agf_verify.patch

@@ -0,0 +1,107 @@
+From d0c7feaf87678371c2c09b3709400be416b2dc62 Mon Sep 17 00:00:00 2001
+From: Zheng Bin <zhengbin13@huawei.com>
+Date: Fri, 21 Feb 2020 07:38:20 -0800
+Subject: [PATCH] xfs: add agf freeblocks verify in xfs_agf_verify
+
+We recently used fuzz(hydra) to test XFS and automatically generate
+tmp.img(XFS v5 format, but some metadata is wrong)
+
+xfs_repair information(just one AG):
+agf_freeblks 0, counted 3224 in ag 0
+agf_longest 536874136, counted 3224 in ag 0
+sb_fdblocks 613, counted 3228
+
+Test as follows:
+mount tmp.img tmpdir
+cp file1M tmpdir
+sync
+
+In 4.19-stable, sync will stuck, the reason is:
+xfs_mountfs
+  xfs_check_summary_counts
+    if ((!xfs_sb_version_haslazysbcount(&mp->m_sb) ||
+       XFS_LAST_UNMOUNT_WAS_CLEAN(mp)) &&
+       !xfs_fs_has_sickness(mp, XFS_SICK_FS_COUNTERS))
+	return 0;  -->just return, incore sb_fdblocks still be 613
+    xfs_initialize_perag_data
+
+cp file1M tmpdir -->ok(write file to pagecache)
+sync -->stuck(write pagecache to disk)
+xfs_map_blocks
+  xfs_iomap_write_allocate
+    while (count_fsb != 0) {
+      nimaps = 0;
+      while (nimaps == 0) { --> endless loop
+         nimaps = 1;
+         xfs_bmapi_write(..., &nimaps) --> nimaps becomes 0 again
+xfs_bmapi_write
+  xfs_bmap_alloc
+    xfs_bmap_btalloc
+      xfs_alloc_vextent
+        xfs_alloc_fix_freelist
+          xfs_alloc_space_available -->fail(agf_freeblks is 0)
+
+In linux-next, sync not stuck, cause commit c2b3164320b5 ("xfs:
+use the latest extent at writeback delalloc conversion time") remove
+the above while, dmesg is as follows:
+[   55.250114] XFS (loop0): page discard on page ffffea0008bc7380, inode 0x1b0c, offset 0.
+
+Users do not know why this page is discard, the better soultion is:
+1. Like xfs_repair, make sure sb_fdblocks is equal to counted
+(xfs_initialize_perag_data did this, who is not called at this mount)
+2. Add agf verify, if fail, will tell users to repair
+
+This patch use the second soultion.
+
+Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
+Signed-off-by: Ren Xudong <renxudong1@huawei.com>
+Reviewed-by: Darrick J. Wong <darrick.wong@oracle.com>
+Signed-off-by: Darrick J. Wong <darrick.wong@oracle.com>
+---
+ fs/xfs/libxfs/xfs_alloc.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/fs/xfs/libxfs/xfs_alloc.c b/fs/xfs/libxfs/xfs_alloc.c
+index d8053bc96c4d..183dc2587092 100644
+--- a/fs/xfs/libxfs/xfs_alloc.c
++++ b/fs/xfs/libxfs/xfs_alloc.c
+@@ -2858,6 +2858,13 @@ xfs_agf_verify(
+ 	      be32_to_cpu(agf->agf_flcount) <= xfs_agfl_size(mp)))
+ 		return __this_address;
+
++	if (be32_to_cpu(agf->agf_length) > mp->m_sb.sb_dblocks)
++		return __this_address;
++
++	if (be32_to_cpu(agf->agf_freeblks) < be32_to_cpu(agf->agf_longest) ||
++	    be32_to_cpu(agf->agf_freeblks) > be32_to_cpu(agf->agf_length))
++		return __this_address;
++
+ 	if (be32_to_cpu(agf->agf_levels[XFS_BTNUM_BNO]) < 1 ||
+ 	    be32_to_cpu(agf->agf_levels[XFS_BTNUM_CNT]) < 1 ||
+ 	    be32_to_cpu(agf->agf_levels[XFS_BTNUM_BNO]) > XFS_BTREE_MAXLEVELS ||
+@@ -2869,6 +2876,10 @@ xfs_agf_verify(
+ 	     be32_to_cpu(agf->agf_levels[XFS_BTNUM_RMAP]) > XFS_BTREE_MAXLEVELS))
+ 		return __this_address;
+
++	if (xfs_sb_version_hasrmapbt(&mp->m_sb) &&
++	    be32_to_cpu(agf->agf_rmap_blocks) > be32_to_cpu(agf->agf_length))
++		return __this_address;
++
+ 	/*
+ 	 * during growfs operations, the perag is not fully initialised,
+ 	 * so we can't use it for any useful checking. growfs ensures we can't
+@@ -2882,6 +2893,11 @@ xfs_agf_verify(
+ 	    be32_to_cpu(agf->agf_btreeblks) > be32_to_cpu(agf->agf_length))
+ 		return __this_address;
+
++	if (xfs_sb_version_hasreflink(&mp->m_sb) &&
++	    be32_to_cpu(agf->agf_refcount_blocks) >
++	    be32_to_cpu(agf->agf_length))
++		return __this_address;
++
+ 	if (xfs_sb_version_hasreflink(&mp->m_sb) &&
+ 	    (be32_to_cpu(agf->agf_refcount_level) < 1 ||
+ 	     be32_to_cpu(agf->agf_refcount_level) > XFS_BTREE_MAXLEVELS))
+-- 
+2.26.2
+

0002-Add-efi_status_to_str-and-rework-efi_status_to_err.patch

@@ -39,9 +39,9 @@ index 557a47829d0..e8f9c7d84e9 100644
 --- a/drivers/firmware/efi/efi.c
 +++ b/drivers/firmware/efi/efi.c
 @@ -31,6 +31,7 @@
- #include <linux/acpi.h>
  #include <linux/ucs2_string.h>
  #include <linux/memblock.h>
+ #include <linux/security.h>
 +#include <linux/bsearch.h>
  
  #include <asm/early_ioremap.h>
@@ -177,7 +177,7 @@ index 557a47829d0..e8f9c7d84e9 100644
 +	return found->description;
  }
  
- bool efi_is_table_address(unsigned long phys_addr)
+ static DEFINE_SPINLOCK(efi_mem_reserve_persistent_lock);
 -- 
 2.15.0
 

0003-Make-get_cert_list-use-efi_status_to_str-to-print-er.patch

@@ -1,38 +1,39 @@
-From 520e902d864930e2d4f329983d9ae9781a24231f Mon Sep 17 00:00:00 2001
+From 46daeedffe98b489014dcdcf14c89438362de7eb Mon Sep 17 00:00:00 2001
 From: Peter Jones <pjones@redhat.com>
 Date: Mon, 2 Oct 2017 18:18:30 -0400
-Subject: [PATCH 3/3] Make get_cert_list() use efi_status_to_str() to print
- error messages.
+Subject: [PATCH] Make get_cert_list() use efi_status_to_str() to print error
+ messages.
 
 Signed-off-by: Peter Jones <pjones@redhat.com>
+Signed-off-by: Jeremy Cline <jcline@redhat.com>
 ---
  security/integrity/platform_certs/load_uefi.c | 6 ++++--
  1 file changed, 4 insertions(+), 2 deletions(-)
 
 diff --git a/security/integrity/platform_certs/load_uefi.c b/security/integrity/platform_certs/load_uefi.c
-index 9ef34c44fd1..13a2826715d 100644
+index f0c908241966..4e783f6c6cfb 100644
 --- a/security/integrity/platform_certs/load_uefi.c
 +++ b/security/integrity/platform_certs/load_uefi.c
-@@ -51,7 +51,8 @@ static __init int get_cert_list(efi_char16_t *name, efi_guid_t *guid,
- 	}
+@@ -46,7 +46,8 @@ static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid,
+ 		return NULL;
  
- 	if (status != EFI_BUFFER_TOO_SMALL) {
--		pr_err("Couldn't get size: 0x%lx\n", status);
+ 	if (*status != EFI_BUFFER_TOO_SMALL) {
+-		pr_err("Couldn't get size: 0x%lx\n", *status);
 +		pr_err("Couldn't get size: %s (0x%lx)\n",
-+		       efi_status_to_str(status), status);
- 		return efi_status_to_err(status);
++		       efi_status_to_str(*status), *status);
+ 		return NULL;
  	}
  
-@@ -64,7 +65,8 @@ static __init int get_cert_list(efi_char16_t *name, efi_guid_t *guid,
- 	status = efi.get_variable(name, guid, NULL, &lsize, db);
- 	if (status != EFI_SUCCESS) {
+@@ -57,7 +58,8 @@ static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid,
+ 	*status = efi.get_variable(name, guid, NULL, &lsize, db);
+ 	if (*status != EFI_SUCCESS) {
  		kfree(db);
--		pr_err("Error reading db var: 0x%lx\n", status);
+-		pr_err("Error reading db var: 0x%lx\n", *status);
 +		pr_err("Error reading db var: %s (0x%lx)\n",
-+		       efi_status_to_str(status), status);
- 		return efi_status_to_err(status);
++		       efi_status_to_str(*status), *status);
+ 		return NULL;
  	}
  
 -- 
-2.15.0
+2.24.1
 

ARM-dts-bcm2711-Move-emmc2-into-its-own-bus.patch

@@ -0,0 +1,168 @@
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+X-Patchwork-Id: 11420129
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+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+To: Rob Herring <robh+dt@kernel.org>,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Subject: [PATCH v2] ARM: dts: bcm2711: Move emmc2 into its own bus
+Date: Wed,  4 Mar 2020 14:24:37 +0100
+Message-Id: <20200304132437.20164-1-nsaenzjulienne@suse.de>
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+Cc: devicetree@vger.kernel.org, f.fainelli@gmail.com, phil@raspberrypi.org,
+ linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com,
+ linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org
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+
+Depending on bcm2711's revision its emmc2 controller might have
+different DMA constraints. Raspberry Pi 4's firmware will take care of
+updating those, but only if a certain alias is found in the device tree.
+So, move emmc2 into its own bus, so as not to pollute other devices with
+dma-ranges changes and create the emmc2bus alias.
+
+Based in Phil ELwell's downstream implementation.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+
+Changes since v1:
+ - Add comment in dt
+ - Fix commit title
+
+ arch/arm/boot/dts/bcm2711-rpi-4-b.dts |  1 +
+ arch/arm/boot/dts/bcm2711.dtsi        | 25 ++++++++++++++++++++-----
+ 2 files changed, 21 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+index 1d4b589fe233..e26ea9006378 100644
+--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
++++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+@@ -20,6 +20,7 @@ memory@0 {
+ 	};
+ 
+ 	aliases {
++		emmc2bus = &emmc2bus;
+ 		ethernet0 = &genet;
+ 		pcie0 = &pcie0;
+ 	};
+diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
+index d1e684d0acfd..a91cf68e3c4c 100644
+--- a/arch/arm/boot/dts/bcm2711.dtsi
++++ b/arch/arm/boot/dts/bcm2711.dtsi
+@@ -241,17 +241,32 @@ pwm1: pwm@7e20c800 {
+ 			status = "disabled";
+ 		};
+ 
++		hvs@7e400000 {
++			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++		};
++	};
++
++	/*
++	 * emmc2 has different DMA constraints based on SoC revisions. It was
++	 * moved into its own bus, so as for RPi4's firmware to update them.
++	 * The firmware will find whether the emmc2bus alias is defined, and if
++	 * so, it'll edit the dma-ranges property below accordingly.
++	 */
++	emmc2bus: emmc2bus {
++		compatible = "simple-bus";
++		#address-cells = <2>;
++		#size-cells = <1>;
++
++		ranges = <0x0 0x7e000000  0x0 0xfe000000  0x01800000>;
++		dma-ranges = <0x0 0xc0000000  0x0 0x00000000  0x40000000>;
++
+ 		emmc2: emmc2@7e340000 {
+ 			compatible = "brcm,bcm2711-emmc2";
+-			reg = <0x7e340000 0x100>;
++			reg = <0x0 0x7e340000 0x100>;
+ 			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&clocks BCM2711_CLOCK_EMMC2>;
+ 			status = "disabled";
+ 		};
+-
+-		hvs@7e400000 {
+-			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+-		};
+ 	};
+ 
+ 	arm-pmu {

ARM-fix-__get_user_check-in-case-uaccess_-calls-are-not-inlined.patch

@@ -0,0 +1,143 @@
+From patchwork Mon Sep 30 05:59:25 2019
+Content-Type: text/plain; charset="utf-8"
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+X-Patchwork-Submitter: Masahiro Yamada <yamada.masahiro@socionext.com>
+X-Patchwork-Id: 1132459
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+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+To: linux-arm-kernel@lists.infradead.org,
+        Russell King <rmk+kernel@armlinux.org.uk>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>,
+        Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>,
+        Nick Desaulniers <ndesaulniers@google.com>,
+        Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+        Masahiro Yamada <yamada.masahiro@socionext.com>,
+        Julien Thierry <julien.thierry.kdev@gmail.com>,
+        Russell King <linux@armlinux.org.uk>,
+        Stefan Agner <stefan@agner.ch>,
+        Thomas Gleixner <tglx@linutronix.de>,
+        Vincent Whitchurch <vincent.whitchurch@axis.com>,
+        linux-kernel@vger.kernel.org
+Subject: [PATCH] ARM: fix __get_user_check() in case uaccess_* calls are not
+ inlined
+Date: Mon, 30 Sep 2019 14:59:25 +0900
+Message-Id: <20190930055925.25842-1-yamada.masahiro@socionext.com>
+X-Mailer: git-send-email 2.17.1
+Sender: linux-kernel-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-kernel.vger.kernel.org>
+X-Mailing-List: linux-kernel@vger.kernel.org
+
+KernelCI reports that bcm2835_defconfig is no longer booting since
+commit ac7c3e4ff401 ("compiler: enable CONFIG_OPTIMIZE_INLINING
+forcibly"):
+
+  https://lkml.org/lkml/2019/9/26/825
+
+I also received a regression report from Nicolas Saenz Julienne:
+
+  https://lkml.org/lkml/2019/9/27/263
+
+This problem has cropped up on arch/arm/config/bcm2835_defconfig
+because it enables CONFIG_CC_OPTIMIZE_FOR_SIZE. The compiler tends
+to prefer not inlining functions with -Os. I was able to reproduce
+it with other boards and defconfig files by manually enabling
+CONFIG_CC_OPTIMIZE_FOR_SIZE.
+
+The __get_user_check() specifically uses r0, r1, r2 registers.
+So, uaccess_save_and_enable() and uaccess_restore() must be inlined
+in order to avoid those registers being overwritten in the callees.
+
+Prior to commit 9012d011660e ("compiler: allow all arches to enable
+CONFIG_OPTIMIZE_INLINING"), the 'inline' marker was always enough for
+inlining functions, except on x86.
+
+Since that commit, all architectures can enable CONFIG_OPTIMIZE_INLINING.
+So, __always_inline is now the only guaranteed way of forcible inlining.
+
+I want to keep as much compiler's freedom as possible about the inlining
+decision. So, I changed the function call order instead of adding
+__always_inline around.
+
+Call uaccess_save_and_enable() before assigning the __p ("r0"), and
+uaccess_restore() after evacuating the __e ("r0").
+
+Fixes: 9012d011660e ("compiler: allow all arches to enable CONFIG_OPTIMIZE_INLINING")
+Reported-by: "kernelci.org bot" <bot@kernelci.org>
+Reported-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+
+ arch/arm/include/asm/uaccess.h | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
+index 303248e5b990..559f252d7e3c 100644
+--- a/arch/arm/include/asm/uaccess.h
++++ b/arch/arm/include/asm/uaccess.h
+@@ -191,11 +191,12 @@ extern int __get_user_64t_4(void *);
+ #define __get_user_check(x, p)						\
+ 	({								\
+ 		unsigned long __limit = current_thread_info()->addr_limit - 1; \
++		unsigned int __ua_flags = uaccess_save_and_enable();	\
+ 		register typeof(*(p)) __user *__p asm("r0") = (p);	\
+ 		register __inttype(x) __r2 asm("r2");			\
+ 		register unsigned long __l asm("r1") = __limit;		\
+ 		register int __e asm("r0");				\
+-		unsigned int __ua_flags = uaccess_save_and_enable();	\
++		unsigned int __err;					\
+ 		switch (sizeof(*(__p))) {				\
+ 		case 1:							\
+ 			if (sizeof((x)) >= 8)				\
+@@ -223,9 +224,10 @@ extern int __get_user_64t_4(void *);
+ 			break;						\
+ 		default: __e = __get_user_bad(); break;			\
+ 		}							\
+-		uaccess_restore(__ua_flags);				\
++		__err = __e;						\
+ 		x = (typeof(*(p))) __r2;				\
+-		__e;							\
++		uaccess_restore(__ua_flags);				\
++		__err;							\
+ 	})
+ 
+ #define get_user(x, p)							\

ARM64-Tegra-fixes.patch

@@ -0,0 +1,477 @@
+From patchwork Mon Feb 24 14:34:33 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
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+X-Patchwork-Submitter: Jon Hunter <jonathanh@nvidia.com>
+X-Patchwork-Id: 1243145
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+ id <B5e53df090001>; Mon, 24 Feb 2020 06:34:50 -0800
+From: Jon Hunter <jonathanh@nvidia.com>
+To: Thierry Reding <thierry.reding@gmail.com>
+CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
+ Jon Hunter <jonathanh@nvidia.com>, <stable@vger.kernel.org>
+Subject: [PATCH 1/4] ARM64: Tegra: Enable I2C controller for EEPROM
+Date: Mon, 24 Feb 2020 14:34:33 +0000
+Message-ID: <20200224143436.5438-1-jonathanh@nvidia.com>
+X-Mailer: git-send-email 2.17.1
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+
+Commit a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1
+module") populated the EEPROM on the Jetson TX1 module, but did not
+enable the corresponding I2C controller. Enable the I2C controller so
+that this EEPROM can be accessed.
+
+Fixes: a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1 module")
+
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+---
+ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+index cb58f79deb48..95b1a6e76e6e 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+@@ -265,6 +265,8 @@
+ 	};
+ 
+ 	i2c@7000c500 {
++		status = "okay";
++
+ 		/* module ID EEPROM */
+ 		eeprom@50 {
+ 			compatible = "atmel,24c02";
+
+From patchwork Mon Feb 24 14:34:34 2020
+Content-Type: text/plain; charset="utf-8"
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+From: Jon Hunter <jonathanh@nvidia.com>
+To: Thierry Reding <thierry.reding@gmail.com>
+CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
+ Jon Hunter <jonathanh@nvidia.com>
+Subject: [PATCH 2/4] ARM64: tegra: Add EEPROM supplies
+Date: Mon, 24 Feb 2020 14:34:34 +0000
+Message-ID: <20200224143436.5438-2-jonathanh@nvidia.com>
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+
+The following warning is observed on Jetson TX1, Jetson Nano and Jetson
+TX2 platforms because the supply regulators are not specified for the
+EEPROMs.
+
+ WARNING KERN at24 0-0050: 0-0050 supply vcc not found, using dummy regulator
+ WARNING KERN at24 0-0057: 0-0057 supply vcc not found, using dummy regulator
+
+For both of these platforms the EEPROM is powered by the main 1.8V
+supply rail and so populate the supply for these devices to fix these
+warnings.
+
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+---
+ arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 1 +
+ arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi     | 1 +
+ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi     | 1 +
+ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 +
+ arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 ++
+ 5 files changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+index d7628f5afb85..961b1be0c56b 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+@@ -226,6 +226,7 @@
+ 			compatible = "atmel,24c02";
+ 			reg = <0x57>;
+ 
++			vcc-supply = <&vdd_1v8>;
+ 			address-bits = <8>;
+ 			page-size = <8>;
+ 			size = <256>;
+diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+index 947744d0f04c..da96de04d003 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+@@ -171,6 +171,7 @@
+ 			compatible = "atmel,24c02";
+ 			reg = <0x50>;
+ 
++			vcc-supply = <&vdd_1v8>;
+ 			address-bits = <8>;
+ 			page-size = <8>;
+ 			size = <256>;
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+index 95b1a6e76e6e..f87d2437d11c 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+@@ -272,6 +272,7 @@
+ 			compatible = "atmel,24c02";
+ 			reg = <0x50>;
+ 
++			vcc-supply = <&vdd_1v8>;
+ 			address-bits = <8>;
+ 			page-size = <8>;
+ 			size = <256>;
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+index a3cafe39ba4c..c70a610f8e3a 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+@@ -85,6 +85,7 @@
+ 			compatible = "atmel,24c02";
+ 			reg = <0x57>;
+ 
++			vcc-supply = <&vdd_1v8>;
+ 			address-bits = <8>;
+ 			page-size = <8>;
+ 			size = <256>;
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+index 848afd855da6..21ed1756b889 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+@@ -114,6 +114,7 @@
+ 			compatible = "atmel,24c02";
+ 			reg = <0x50>;
+ 
++			vcc-supply = <&vdd_1v8>;
+ 			address-bits = <8>;
+ 			page-size = <8>;
+ 			size = <256>;
+@@ -124,6 +125,7 @@
+ 			compatible = "atmel,24c02";
+ 			reg = <0x57>;
+ 
++			vcc-supply = <&vdd_1v8>;
+ 			address-bits = <8>;
+ 			page-size = <8>;
+ 			size = <256>;
+
+From patchwork Mon Feb 24 14:34:35 2020
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+X-Patchwork-Id: 1243147
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+ id <B5e53df110000>; Mon, 24 Feb 2020 06:34:58 -0800
+From: Jon Hunter <jonathanh@nvidia.com>
+To: Thierry Reding <thierry.reding@gmail.com>
+CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
+ Jon Hunter <jonathanh@nvidia.com>, <stable@vger.kernel.org>
+Subject: [PATCH 3/4] ARM64: tegra: Fix Tegra186 SOR supply
+Date: Mon, 24 Feb 2020 14:34:35 +0000
+Message-ID: <20200224143436.5438-3-jonathanh@nvidia.com>
+X-Mailer: git-send-email 2.17.1
+In-Reply-To: <20200224143436.5438-1-jonathanh@nvidia.com>
+References: <20200224143436.5438-1-jonathanh@nvidia.com>
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+
+The following warning is observed on the Jetson TX2 platform ...
+
+ WARNING KERN tegra-sor 15540000.sor: 15540000.sor supply \
+              vdd-hdmi-dp-pll not found, using dummy regulator
+
+The problem is caused because the regulator for the SOR device is
+missing the '-supply' suffix in Device-Tree. Therefore, add the
+'-supply' suffix to fix this warning.
+
+Fixes: 3fdfaf8718fa arm64: tegra: Enable DP support on Jetson TX2
+
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+---
+ arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+index 961b1be0c56b..1af7f9ffb7b6 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+@@ -278,7 +278,7 @@
+ 			status = "okay";
+ 
+ 			avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
+-			vdd-hdmi-dp-pll = <&vdd_1v8_ap>;
++			vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
+ 
+ 			nvidia,dpaux = <&dpaux>;
+ 		};
+
+From patchwork Mon Feb 24 14:34:36 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
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+X-Patchwork-Submitter: Jon Hunter <jonathanh@nvidia.com>
+X-Patchwork-Id: 1243148
+Return-Path: <linux-tegra-owner@vger.kernel.org>
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+ id <B5e53df140006>; Mon, 24 Feb 2020 06:35:01 -0800
+From: Jon Hunter <jonathanh@nvidia.com>
+To: Thierry Reding <thierry.reding@gmail.com>
+CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
+ Jon Hunter <jonathanh@nvidia.com>
+Subject: [PATCH 4/4] ARM64: tegra: Populate LP8557 backlight regulator
+Date: Mon, 24 Feb 2020 14:34:36 +0000
+Message-ID: <20200224143436.5438-4-jonathanh@nvidia.com>
+X-Mailer: git-send-email 2.17.1
+In-Reply-To: <20200224143436.5438-1-jonathanh@nvidia.com>
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+
+The following warning is observed on Jetson TX1 platform because the
+supply regulator is not specified for the backlight.
+
+ WARNING KERN lp855x 0-002c: 0-002c supply power not found, using dummy regulator
+
+The backlight supply is provided by the 3.3V SYS rail and so add this
+as the supply for the backlight.
+
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+---
+ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+index c70a610f8e3a..ea0e1efa6973 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+@@ -56,6 +56,7 @@
+ 		backlight: backlight@2c {
+ 			compatible = "ti,lp8557";
+ 			reg = <0x2c>;
++			power-supply = <&vdd_3v3_sys>;
+ 
+ 			dev-ctrl = /bits/ 8 <0x80>;
+ 			init-brt = /bits/ 8 <0xff>;

Add-option-to-automatically-enforce-module-signature.patch

@@ -1,217 +0,0 @@
-From 6b6203b92cfb457a0669a9c87a29b360405bffc6 Mon Sep 17 00:00:00 2001
-From: Matthew Garrett <matthew.garrett@nebula.com>
-Date: Fri, 9 Aug 2013 18:36:30 -0400
-Subject: [PATCH 10/20] Add option to automatically enforce module signatures
- when in Secure Boot mode
-
-UEFI Secure Boot provides a mechanism for ensuring that the firmware will
-only load signed bootloaders and kernels. Certain use cases may also
-require that all kernel modules also be signed. Add a configuration option
-that enforces this automatically when enabled.
-
-Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com>
----
- Documentation/x86/zero-page.txt       |  2 ++
- arch/x86/Kconfig                      | 11 ++++++
- arch/x86/boot/compressed/eboot.c      | 66 +++++++++++++++++++++++++++++++++++
- arch/x86/include/uapi/asm/bootparam.h |  3 +-
- arch/x86/kernel/setup.c               |  6 ++++
- include/linux/module.h                |  6 ++++
- kernel/module.c                       |  7 ++++
- 7 files changed, 100 insertions(+), 1 deletion(-)
-
-diff --git a/Documentation/x86/zero-page.txt b/Documentation/x86/zero-page.txt
-index 95a4d34af3fd..b8527c6b7646 100644
---- a/Documentation/x86/zero-page.txt
-+++ b/Documentation/x86/zero-page.txt
-@@ -31,6 +31,8 @@ Offset	Proto	Name		Meaning
- 1E9/001	ALL	eddbuf_entries	Number of entries in eddbuf (below)
- 1EA/001	ALL	edd_mbr_sig_buf_entries	Number of entries in edd_mbr_sig_buffer
- 				(below)
-+1EB/001	ALL     kbd_status      Numlock is enabled
-+1EC/001	ALL     secure_boot	Secure boot is enabled in the firmware
- 1EF/001	ALL	sentinel	Used to detect broken bootloaders
- 290/040	ALL	edd_mbr_sig_buffer EDD MBR signatures
- 2D0/A00	ALL	e820_map	E820 memory map table
-diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
-index bada636d1065..d666ef8b616c 100644
---- a/arch/x86/Kconfig
-+++ b/arch/x86/Kconfig
-@@ -1786,6 +1786,17 @@ config EFI_MIXED
- 
- 	   If unsure, say N.
- 
-+config EFI_SECURE_BOOT_SIG_ENFORCE
-+	def_bool n
-+	depends on EFI
-+	prompt "Force module signing when UEFI Secure Boot is enabled"
-+	---help---
-+	  UEFI Secure Boot provides a mechanism for ensuring that the
-+	  firmware will only load signed bootloaders and kernels. Certain
-+	  use cases may also require that all kernel modules also be signed.
-+	  Say Y here to automatically enable module signature enforcement
-+	  when a system boots with UEFI Secure Boot enabled.
-+
- config SECCOMP
- 	def_bool y
- 	prompt "Enable seccomp to safely compute untrusted bytecode"
-diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
-index cc69e37548db..ebc85c1eefd6 100644
---- a/arch/x86/boot/compressed/eboot.c
-+++ b/arch/x86/boot/compressed/eboot.c
-@@ -12,6 +12,7 @@
- #include <asm/efi.h>
- #include <asm/setup.h>
- #include <asm/desc.h>
-+#include <asm/bootparam_utils.h>
- 
- #include "../string.h"
- #include "eboot.h"
-@@ -537,6 +538,67 @@ static void setup_efi_pci(struct boot_params *params)
- 	efi_call_early(free_pool, pci_handle);
- }
- 
-+static int get_secure_boot(void)
-+{
-+	u8 sb, setup;
-+	unsigned long datasize = sizeof(sb);
-+	efi_guid_t var_guid = EFI_GLOBAL_VARIABLE_GUID;
-+	efi_status_t status;
-+
-+	status = efi_early->call((unsigned long)sys_table->runtime->get_variable,
-+				L"SecureBoot", &var_guid, NULL, &datasize, &sb);
-+
-+	if (status != EFI_SUCCESS)
-+		return 0;
-+
-+	if (sb == 0)
-+		return 0;
-+
-+
-+	status = efi_early->call((unsigned long)sys_table->runtime->get_variable,
-+				L"SetupMode", &var_guid, NULL, &datasize,
-+				&setup);
-+
-+	if (status != EFI_SUCCESS)
-+		return 0;
-+
-+	if (setup == 1)
-+		return 0;
-+
-+	return 1;
-+}
-+
-+
-+/*
-+ * See if we have Graphics Output Protocol
-+ */
-+static efi_status_t setup_gop(struct screen_info *si, efi_guid_t *proto,
-+			      unsigned long size)
-+{
-+	efi_status_t status;
-+	void **gop_handle = NULL;
-+
-+	status = efi_call_early(allocate_pool, EFI_LOADER_DATA,
-+				size, (void **)&gop_handle);
-+	if (status != EFI_SUCCESS)
-+		return status;
-+
-+	status = efi_call_early(locate_handle,
-+				EFI_LOCATE_BY_PROTOCOL,
-+				proto, NULL, &size, gop_handle);
-+	if (status != EFI_SUCCESS)
-+		goto free_handle;
-+
-+	if (efi_early->is64)
-+		status = setup_gop64(si, proto, size, gop_handle);
-+	else
-+		status = setup_gop32(si, proto, size, gop_handle);
-+
-+free_handle:
-+	efi_call_early(free_pool, gop_handle);
-+	return status;
-+}
-+
- static efi_status_t
- setup_uga32(void **uga_handle, unsigned long size, u32 *width, u32 *height)
- {
-@@ -1094,6 +1156,10 @@ struct boot_params *efi_main(struct efi_config *c,
- 	else
- 		setup_boot_services32(efi_early);
- 
-+	sanitize_boot_params(boot_params);
-+
-+	boot_params->secure_boot = get_secure_boot();
-+
- 	setup_graphics(boot_params);
- 
- 	setup_efi_pci(boot_params);
-diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
-index c18ce67495fa..2b3e5427097b 100644
---- a/arch/x86/include/uapi/asm/bootparam.h
-+++ b/arch/x86/include/uapi/asm/bootparam.h
-@@ -134,7 +134,8 @@ struct boot_params {
- 	__u8  eddbuf_entries;				/* 0x1e9 */
- 	__u8  edd_mbr_sig_buf_entries;			/* 0x1ea */
- 	__u8  kbd_status;				/* 0x1eb */
--	__u8  _pad5[3];					/* 0x1ec */
-+	__u8  secure_boot;				/* 0x1ec */
-+	__u8  _pad5[2];					/* 0x1ed */
- 	/*
- 	 * The sentinel is set to a nonzero value (0xff) in header.S.
- 	 *
-diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
-index bbfbca5fea0c..d40e961753c9 100644
---- a/arch/x86/kernel/setup.c
-+++ b/arch/x86/kernel/setup.c
-@@ -1160,6 +1160,12 @@ void __init setup_arch(char **cmdline_p)
- 
- 	io_delay_init();
- 
-+#ifdef CONFIG_EFI_SECURE_BOOT_SIG_ENFORCE
-+	if (boot_params.secure_boot) {
-+		enforce_signed_modules();
-+	}
-+#endif
-+
- 	/*
- 	 * Parse the ACPI tables for possible boot-time SMP configuration.
- 	 */
-diff --git a/include/linux/module.h b/include/linux/module.h
-index 05bd6c989a0c..32327704e18d 100644
---- a/include/linux/module.h
-+++ b/include/linux/module.h
-@@ -260,6 +260,12 @@ extern const typeof(name) __mod_##type##__##name##_device_table		\
- 
- struct notifier_block;
- 
-+#ifdef CONFIG_MODULE_SIG
-+extern void enforce_signed_modules(void);
-+#else
-+static inline void enforce_signed_modules(void) {};
-+#endif
-+
- #ifdef CONFIG_MODULES
- 
- extern int modules_disabled; /* for sysctl */
-diff --git a/kernel/module.c b/kernel/module.c
-index cb864505d020..cb1f1da69bf4 100644
---- a/kernel/module.c
-+++ b/kernel/module.c
-@@ -4285,6 +4285,13 @@ void module_layout(struct module *mod,
- EXPORT_SYMBOL(module_layout);
- #endif
- 
-+#ifdef CONFIG_MODULE_SIG
-+void enforce_signed_modules(void)
-+{
-+	sig_enforce = true;
-+}
-+#endif
-+
- bool secure_modules(void)
- {
- #ifdef CONFIG_MODULE_SIG
--- 
-2.9.3
-

Allwinner-A64-timer-workaround.patch

@@ -1,527 +0,0 @@
-From patchwork Sun Jan 13 02:17:18 2019
-Content-Type: text/plain; charset="utf-8"
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-From: Samuel Holland <samuel@sholland.org>
-To: Catalin Marinas <catalin.marinas@arm.com>,
- Will Deacon <will.deacon@arm.com>,
- Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
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- Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
-Subject: [PATCH v3 1/2] arm64: arch_timer: Workaround for Allwinner A64 timer
- instability
-Date: Sat, 12 Jan 2019 20:17:18 -0600
-Message-Id: <20190113021719.46457-2-samuel@sholland.org>
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-
-The Allwinner A64 SoC is known[1] to have an unstable architectural
-timer, which manifests itself most obviously in the time jumping forward
-a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a
-timer frequency of 24 MHz, implying that the time went slightly backward
-(and this was interpreted by the kernel as it jumping forward and
-wrapping around past the epoch).
-
-Investigation revealed instability in the low bits of CNTVCT at the
-point a high bit rolls over. This leads to power-of-two cycle forward
-and backward jumps. (Testing shows that forward jumps are about twice as
-likely as backward jumps.) Since the counter value returns to normal
-after an indeterminate read, each "jump" really consists of both a
-forward and backward jump from the software perspective.
-
-Unless the kernel is trapping CNTVCT reads, a userspace program is able
-to read the register in a loop faster than it changes. A test program
-running on all 4 CPU cores that reported jumps larger than 100 ms was
-run for 13.6 hours and reported the following:
-
- Count | Event
--------+---------------------------
-  9940 | jumped backward      699ms
-   268 | jumped backward     1398ms
-     1 | jumped backward     2097ms
- 16020 | jumped forward       175ms
-  6443 | jumped forward       699ms
-  2976 | jumped forward      1398ms
-     9 | jumped forward    356516ms
-     9 | jumped forward    357215ms
-     4 | jumped forward    714430ms
-     1 | jumped forward   3578440ms
-
-This works out to a jump larger than 100 ms about every 5.5 seconds on
-each CPU core.
-
-The largest jump (almost an hour!) was the following sequence of reads:
-    0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
-
-Note that the middle bits don't necessarily all read as all zeroes or
-all ones during the anomalous behavior; however the low 10 bits checked
-by the function in this patch have never been observed with any other
-value.
-
-Also note that smaller jumps are much more common, with backward jumps
-of 2048 (2^11) cycles observed over 400 times per second on each core.
-(Of course, this is partially explained by lower bits rolling over more
-frequently.) Any one of these could have caused the 95 year time skip.
-
-Similar anomalies were observed while reading CNTPCT (after patching the
-kernel to allow reads from userspace). However, the CNTPCT jumps are
-much less frequent, and only small jumps were observed. The same program
-as before (except now reading CNTPCT) observed after 72 hours:
-
- Count | Event
--------+---------------------------
-    17 | jumped backward      699ms
-    52 | jumped forward       175ms
-  2831 | jumped forward       699ms
-     5 | jumped forward      1398ms
-
-Further investigation showed that the instability in CNTPCT/CNTVCT also
-affected the respective timer's TVAL register. The following values were
-observed immediately after writing CNVT_TVAL to 0x10000000:
-
- CNTVCT             | CNTV_TVAL  | CNTV_CVAL          | CNTV_TVAL Error
---------------------+------------+--------------------+-----------------
- 0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000
- 0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000
- 0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000
- 0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000
-
-The pattern of errors in CNTV_TVAL seemed to depend on exactly which
-value was written to it. For example, after writing 0x10101010:
-
- CNTVCT             | CNTV_TVAL  | CNTV_CVAL          | CNTV_TVAL Error
---------------------+------------+--------------------+-----------------
- 0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000
- 0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000
- 0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000
- 0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000
- 0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000
- 0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000
-
-I was also twice able to reproduce the issue covered by Allwinner's
-workaround[4], that writing to TVAL sometimes fails, and both CVAL and
-TVAL are left with entirely bogus values. One was the following values:
-
- CNTVCT             | CNTV_TVAL  | CNTV_CVAL
---------------------+------------+--------------------------------------
- 0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past)
-
-========================================================================
-
-Because the CPU can read the CNTPCT/CNTVCT registers faster than they
-change, performing two reads of the register and comparing the high bits
-(like other workarounds) is not a workable solution. And because the
-timer can jump both forward and backward, no pair of reads can
-distinguish a good value from a bad one. The only way to guarantee a
-good value from consecutive reads would be to read _three_ times, and
-take the middle value only if the three values are 1) each unique and
-2) increasing. This takes at minimum 3 counter cycles (125 ns), or more
-if an anomaly is detected.
-
-However, since there is a distinct pattern to the bad values, we can
-optimize the common case (1022/1024 of the time) to a single read by
-simply ignoring values that match the error pattern. This still takes no
-more than 3 cycles in the worst case, and requires much less code. As an
-additional safety check, we still limit the loop iteration to the number
-of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods.
-
-For the TVAL registers, the simple solution is to not use them. Instead,
-read or write the CVAL and calculate the TVAL value in software.
-
-Although the manufacturer is aware of at least part of the erratum[4],
-there is no official name for it. For now, use the kernel-internal name
-"UNKNOWN1".
-
-[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
-[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
-[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
-[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272
-
-Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
-Tested-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/arm64/silicon-errata.txt |  2 +
- drivers/clocksource/Kconfig            | 10 +++++
- drivers/clocksource/arm_arch_timer.c   | 55 ++++++++++++++++++++++++++
- 3 files changed, 67 insertions(+)
-
-diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
-index 8f9577621144..4a269732d2a0 100644
---- a/Documentation/arm64/silicon-errata.txt
-+++ b/Documentation/arm64/silicon-errata.txt
-@@ -44,6 +44,8 @@ stable kernels.
- 
- | Implementor    | Component       | Erratum ID      | Kconfig                     |
- +----------------+-----------------+-----------------+-----------------------------+
-+| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |
-+|                |                 |                 |                             |
- | ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |
- | ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |
- | ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069        |
-diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
-index 55c77e44bb2d..d20ff4da07c3 100644
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -364,6 +364,16 @@ config ARM64_ERRATUM_858921
- 	  The workaround will be dynamically enabled when an affected
- 	  core is detected.
- 
-+config SUN50I_ERRATUM_UNKNOWN1
-+	bool "Workaround for Allwinner A64 erratum UNKNOWN1"
-+	default y
-+	depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
-+	select ARM_ARCH_TIMER_OOL_WORKAROUND
-+	help
-+	  This option enables a workaround for instability in the timer on
-+	  the Allwinner A64 SoC. The workaround will only be active if the
-+	  allwinner,erratum-unknown1 property is found in the timer node.
-+
- config ARM_GLOBAL_TIMER
- 	bool "Support for the ARM global timer" if COMPILE_TEST
- 	select TIMER_OF if OF
-diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
-index 9a7d4dc00b6e..a8b20b65bd4b 100644
---- a/drivers/clocksource/arm_arch_timer.c
-+++ b/drivers/clocksource/arm_arch_timer.c
-@@ -326,6 +326,48 @@ static u64 notrace arm64_1188873_read_cntvct_el0(void)
- }
- #endif
- 
-+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
-+/*
-+ * The low bits of the counter registers are indeterminate while bit 10 or
-+ * greater is rolling over. Since the counter value can jump both backward
-+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
-+ * with all ones or all zeros in the low bits. Bound the loop by the maximum
-+ * number of CPU cycles in 3 consecutive 24 MHz counter periods.
-+ */
-+#define __sun50i_a64_read_reg(reg) ({					\
-+	u64 _val;							\
-+	int _retries = 150;						\
-+									\
-+	do {								\
-+		_val = read_sysreg(reg);				\
-+		_retries--;						\
-+	} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries);	\
-+									\
-+	WARN_ON_ONCE(!_retries);					\
-+	_val;								\
-+})
-+
-+static u64 notrace sun50i_a64_read_cntpct_el0(void)
-+{
-+	return __sun50i_a64_read_reg(cntpct_el0);
-+}
-+
-+static u64 notrace sun50i_a64_read_cntvct_el0(void)
-+{
-+	return __sun50i_a64_read_reg(cntvct_el0);
-+}
-+
-+static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
-+{
-+	return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
-+}
-+
-+static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
-+{
-+	return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
-+}
-+#endif
-+
- #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
- DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
- EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
-@@ -423,6 +465,19 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
- 		.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
- 	},
- #endif
-+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
-+	{
-+		.match_type = ate_match_dt,
-+		.id = "allwinner,erratum-unknown1",
-+		.desc = "Allwinner erratum UNKNOWN1",
-+		.read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
-+		.read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
-+		.read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
-+		.read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
-+		.set_next_event_phys = erratum_set_next_event_tval_phys,
-+		.set_next_event_virt = erratum_set_next_event_tval_virt,
-+	},
-+#endif
- };
- 
- typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
-
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- Sat, 12 Jan 2019 21:17:22 -0500 (EST)
-From: Samuel Holland <samuel@sholland.org>
-To: Catalin Marinas <catalin.marinas@arm.com>,
- Will Deacon <will.deacon@arm.com>,
- Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
- Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
- Daniel Lezcano <daniel.lezcano@linaro.org>,
- Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
-Subject: [PATCH v3 2/2] arm64: dts: allwinner: a64: Enable A64 timer
- workaround
-Date: Sat, 12 Jan 2019 20:17:19 -0600
-Message-Id: <20190113021719.46457-3-samuel@sholland.org>
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-
-As instability in the architectural timer has been observed on multiple
-devices using this SoC, inluding the Pine64 and the Orange Pi Win,
-enable the workaround in the SoC's device tree.
-
-Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-index f3a66f888205..13eac92a8c55 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -175,6 +175,7 @@
- 
- 	timer {
- 		compatible = "arm,armv8-timer";
-+		allwinner,erratum-unknown1;
- 		interrupts = <GIC_PPI 13
- 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- 			     <GIC_PPI 14

Input-synaptics-pin-3-touches-when-the-firmware-repo.patch

@@ -1,47 +0,0 @@
-From: Benjamin Tissoires <benjamin.tissoires@redhat.com>
-Date: Thu, 16 Apr 2015 13:01:46 -0400
-Subject: [PATCH] Input - synaptics: pin 3 touches when the firmware reports 3
- fingers
-
-Synaptics PS/2 touchpad can send only 2 touches in a report. They can
-detect 4 or 5 and this information is valuable.
-
-In commit 63c4fda (Input: synaptics - allocate 3 slots to keep stability
-in image sensors), we allocate 3 slots, but we still continue to report
-the 2 available fingers. That means that the client sees 2 used slots while
-there is a total of 3 fingers advertised by BTN_TOOL_TRIPLETAP.
-
-For old kernels this is not a problem because max_slots was 2 and libinput/
-xorg-synaptics knew how to deal with that. Now that max_slot is 3, the
-clients ignore BTN_TOOL_TRIPLETAP and count the actual used slots (so 2).
-It then gets confused when receiving the BTN_TOOL_TRIPLETAP and DOUBLETAP
-information, and goes wild.
-
-We can pin the 3 slots until we get a total number of fingers below 2.
-
-Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1212230
-
-Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
----
- drivers/input/mouse/synaptics.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
-index 3a32caf06bf1..58102970f94f 100644
---- a/drivers/input/mouse/synaptics.c
-+++ b/drivers/input/mouse/synaptics.c
-@@ -940,6 +940,14 @@ static void synaptics_report_mt_data(struct psmouse *psmouse,
- 		input_report_abs(dev, ABS_MT_PRESSURE, hw[i]->z);
- 	}
- 
-+	/* keep (slot count <= num_fingers) by pinning all slots */
-+	if (num_fingers >= 3) {
-+		for (i = 0; i < 3; i++) {
-+			input_mt_slot(dev, i);
-+			input_mt_report_slot_state(dev, MT_TOOL_FINGER, true);
-+		}
-+	}
-+
- 	input_mt_drop_unused(dev);
- 
- 	/* Don't use active slot count to generate BTN_TOOL events. */

KEYS-Allow-unrestricted-boot-time-addition-of-keys-t.patch

@@ -1,95 +0,0 @@
-From fb2ac204a70da565de9ef9a9d6d69a40c2d59727 Mon Sep 17 00:00:00 2001
-From: David Howells <dhowells@redhat.com>
-Date: Fri, 5 May 2017 08:21:56 +0100
-Subject: [PATCH] KEYS: Allow unrestricted boot-time addition of keys to
- secondary keyring
-
-Allow keys to be added to the system secondary certificates keyring during
-kernel initialisation in an unrestricted fashion.  Such keys are implicitly
-trusted and don't have their trust chains checked on link.
-
-This allows keys in the UEFI database to be added in secure boot mode for
-the purposes of module signing.
-
-Signed-off-by: David Howells <dhowells@redhat.com>
----
- certs/internal.h       | 18 ++++++++++++++++++
- certs/system_keyring.c | 33 +++++++++++++++++++++++++++++++++
- 2 files changed, 51 insertions(+)
- create mode 100644 certs/internal.h
-
-diff --git a/certs/internal.h b/certs/internal.h
-new file mode 100644
-index 0000000..5dcbefb
---- /dev/null
-+++ b/certs/internal.h
-@@ -0,0 +1,18 @@
-+/* Internal definitions
-+ *
-+ * Copyright (C) 2016 Red Hat, Inc. All Rights Reserved.
-+ * Written by David Howells (dhowells@redhat.com)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public Licence
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the Licence, or (at your option) any later version.
-+ */
-+
-+/*
-+ * system_keyring.c
-+ */
-+#ifdef CONFIG_SECONDARY_TRUSTED_KEYRING
-+extern void __init add_trusted_secondary_key(const char *source,
-+					     const void *data, size_t len);
-+#endif
-diff --git a/certs/system_keyring.c b/certs/system_keyring.c
-index 6251d1b..5ac8ba6 100644
---- a/certs/system_keyring.c
-+++ b/certs/system_keyring.c
-@@ -18,6 +18,7 @@
- #include <keys/asymmetric-type.h>
- #include <keys/system_keyring.h>
- #include <crypto/pkcs7.h>
-+#include "internal.h"
-
- static struct key *builtin_trusted_keys;
- #ifdef CONFIG_SECONDARY_TRUSTED_KEYRING
-@@ -265,3 +266,35 @@ int verify_pkcs7_signature(const void *data, size_t len,
- EXPORT_SYMBOL_GPL(verify_pkcs7_signature);
-
- #endif /* CONFIG_SYSTEM_DATA_VERIFICATION */
-+
-+#ifdef CONFIG_SECONDARY_TRUSTED_KEYRING
-+/**
-+ * add_trusted_secondary_key - Add to secondary keyring with no validation
-+ * @source: Source of key
-+ * @data: The blob holding the key
-+ * @len: The length of the data blob
-+ *
-+ * Add a key to the secondary keyring without checking its trust chain.  This
-+ * is available only during kernel initialisation.
-+ */
-+void __init add_trusted_secondary_key(const char *source,
-+				      const void *data, size_t len)
-+{
-+	key_ref_t key;
-+
-+	key = key_create_or_update(make_key_ref(secondary_trusted_keys, 1),
-+				   "asymmetric",
-+				   NULL, data, len,
-+				   (KEY_POS_ALL & ~KEY_POS_SETATTR) |
-+				   KEY_USR_VIEW,
-+				   KEY_ALLOC_NOT_IN_QUOTA |
-+				   KEY_ALLOC_BYPASS_RESTRICTION);
-+
-+	if (IS_ERR(key))
-+		pr_err("Problem loading %s X.509 certificate (%ld)\n",
-+		       source, PTR_ERR(key));
-+	else
-+		pr_notice("Loaded %s cert '%s' linked to secondary sys keyring\n",
-+			  source, key_ref_to_ptr(key)->description);
-+}
-+#endif /* CONFIG_SECONDARY_TRUSTED_KEYRING */
--- 
-2.9.3
-

KEYS-Make-use-of-platform-keyring-for-module-signature.patch

@@ -0,0 +1,43 @@
+From 70cecc97a4fc1667472224558a50dd7b6c42c789 Mon Sep 17 00:00:00 2001
+From: Robert Holmes <robeholmes@gmail.com>
+Date: Tue, 23 Apr 2019 07:39:29 +0000
+Subject: [PATCH] KEYS: Make use of platform keyring for module signature
+ verify
+
+This patch completes commit 278311e417be ("kexec, KEYS: Make use of
+platform keyring for signature verify") which, while adding the
+platform keyring for bzImage verification, neglected to also add
+this keyring for module verification.
+
+As such, kernel modules signed with keys from the MokList variable
+were not successfully verified.
+
+Signed-off-by: Robert Holmes <robeholmes@gmail.com>
+Signed-off-by: Jeremy Cline <jcline@redhat.com>
+---
+ kernel/module_signing.c | 16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/kernel/module_signing.c b/kernel/module_signing.c
+index 9d9fc678c91d..84ad75a53c83 100644
+--- a/kernel/module_signing.c
++++ b/kernel/module_signing.c
+@@ -38,8 +38,15 @@ int mod_verify_sig(const void *mod, struct load_info *info)
+ 	modlen -= sig_len + sizeof(ms);
+ 	info->len = modlen;
+ 
+-	return verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len,
++	ret = verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len,
+ 				      VERIFY_USE_SECONDARY_KEYRING,
+ 				      VERIFYING_MODULE_SIGNATURE,
+ 				      NULL, NULL);
++	if (ret == -ENOKEY && IS_ENABLED(CONFIG_INTEGRITY_PLATFORM_KEYRING)) {
++		ret = verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len,
++				VERIFY_USE_PLATFORM_KEYRING,
++				VERIFYING_MODULE_SIGNATURE,
++				NULL, NULL);
++	}
++	return ret;
+ }
+-- 
+2.21.0

Kbuild-Add-an-option-to-enable-GCC-VTA.patch

@@ -1,89 +0,0 @@
-From: Josh Stone <jistone@redhat.com>
-Date: Fri, 21 Nov 2014 10:40:00 -0800
-Subject: [PATCH] Kbuild: Add an option to enable GCC VTA
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Due to recent codegen issues, gcc -fvar-tracking-assignments was
-unconditionally disabled in commit 2062afb4f804a ("Fix gcc-4.9.0
-miscompilation of load_balance() in scheduler").  However, this reduces
-the debuginfo coverage for variable locations, especially in inline
-functions.  VTA is certainly not perfect either in those cases, but it
-is much better than without.  With compiler versions that have fixed the
-codegen bugs, we would prefer to have the better details for SystemTap,
-and surely other debuginfo consumers like perf will benefit as well.
-
-This patch simply makes CONFIG_DEBUG_INFO_VTA an option.  I considered
-Frank and Linus's discussion of a cc-option-like -fcompare-debug test,
-but I'm convinced that a narrow test of an arch-specific codegen issue
-is not really useful.  GCC has their own regression tests for this, so
-I'd suggest GCC_COMPARE_DEBUG=-fvar-tracking-assignments-toggle is more
-useful for kernel developers to test confidence.
-
-In fact, I ran into a couple more issues when testing for this patch[1],
-although neither of those had any codegen impact.
- [1] https://bugzilla.redhat.com/show_bug.cgi?id=1140872
-
-With gcc-4.9.2-1.fc22, I can now build v3.18-rc5 with Fedora's i686 and
-x86_64 configs, and this is completely clean with GCC_COMPARE_DEBUG.
-
-Cc: Frank Ch. Eigler <fche@redhat.com>
-Cc: Jakub Jelinek <jakub@redhat.com>
-Cc: Josh Boyer <jwboyer@fedoraproject.org>
-Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Cc: Linus Torvalds <torvalds@linux-foundation.org>
-Cc: Andrew Morton <akpm@linux-foundation.org>
-Cc: Markus Trippelsdorf <markus@trippelsdorf.de>
-Cc: Michel Dänzer <michel@daenzer.net>
-Signed-off-by: Josh Stone <jistone@redhat.com>
----
- Makefile          |  4 ++++
- lib/Kconfig.debug | 18 +++++++++++++++++-
- 2 files changed, 21 insertions(+), 1 deletion(-)
-
-diff --git a/Makefile b/Makefile
-index 257ef5892ab7..3cc6f4477e78 100644
---- a/Makefile
-+++ b/Makefile
-@@ -701,7 +701,11 @@ KBUILD_CFLAGS	+= -fomit-frame-pointer
- endif
- endif
- 
-+ifdef CONFIG_DEBUG_INFO_VTA
-+KBUILD_CFLAGS   += $(call cc-option, -fvar-tracking-assignments)
-+else
- KBUILD_CFLAGS   += $(call cc-option, -fno-var-tracking-assignments)
-+endif
- 
- ifdef CONFIG_DEBUG_INFO
- ifdef CONFIG_DEBUG_INFO_SPLIT
-diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
-index e2894b23efb6..d98afe18f704 100644
---- a/lib/Kconfig.debug
-+++ b/lib/Kconfig.debug
-@@ -165,7 +165,23 @@ config DEBUG_INFO_DWARF4
- 	  Generate dwarf4 debug info. This requires recent versions
- 	  of gcc and gdb. It makes the debug information larger.
- 	  But it significantly improves the success of resolving
--	  variables in gdb on optimized code.
-+	  variables in gdb on optimized code.  The gcc docs also
-+	  recommend enabling -fvar-tracking-assignments for maximum
-+	  benefit. (see DEBUG_INFO_VTA)
-+
-+config DEBUG_INFO_VTA
-+	bool "Enable var-tracking-assignments for debuginfo"
-+	depends on DEBUG_INFO
-+	help
-+	  Enable gcc -fvar-tracking-assignments for improved debug
-+	  information on variable locations in optimized code.  Per
-+	  gcc, DEBUG_INFO_DWARF4 is recommended for best use of VTA.
-+
-+	  VTA has been implicated in codegen bugs (gcc PR61801,
-+	  PR61904), so this may deserve some caution.  One can set
-+	  GCC_COMPARE_DEBUG=-fvar-tracking-assignments-toggle in the
-+	  environment to automatically compile everything both ways,
-+	  generating an error if anything differs.
- 
- config GDB_SCRIPTS
- 	bool "Provide GDB scripts for kernel debugging"

PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch

@@ -0,0 +1,481 @@
+From patchwork Fri Jan 10 19:14:59 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Vidya Sagar <vidyas@nvidia.com>
+X-Patchwork-Id: 1221384
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+From: Vidya Sagar <vidyas@nvidia.com>
+To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
+ <rjw@rjwysocki.net>, <lenb@kernel.org>, <andrew.murray@arm.com>,
+ <treding@nvidia.com>, <jonathanh@nvidia.com>
+CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
+ <linux-acpi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
+ <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
+ <sagar.tv@gmail.com>
+Subject: [PATCH V3 1/2] arm64: tegra: Re-order PCIe aperture mappings to
+ support ACPI boot
+Date: Sat, 11 Jan 2020 00:44:59 +0530
+Message-ID: <20200110191500.9538-2-vidyas@nvidia.com>
+X-Mailer: git-send-email 2.17.1
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+ <20200110191500.9538-1-vidyas@nvidia.com>
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+
+Re-order Tegra194's PCIe aperture mappings to have IO window moved to
+64-bit aperture and have the entire 32-bit aperture used for accessing
+the configuration space. This makes it to use the entire 32MB of the 32-bit
+aperture for ECAM purpose while booting through ACPI.
+
+Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
+---
+V3:
+* New change in this series
+
+ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 36 ++++++++++++------------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+index ccac43be12ac..5d790ec5bdef 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+@@ -1247,9 +1247,9 @@
+ 		nvidia,aspm-l0s-entrance-latency-us = <3>;
+ 
+ 		bus-range = <0x0 0xff>;
+-		ranges = <0x81000000 0x0  0x30100000 0x0  0x30100000 0x0 0x00100000   /* downstream I/O (1MB) */
+-			  0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000   /* prefetchable memory (768MB) */
+-			  0x82000000 0x0  0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
++		ranges = <0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000   /* prefetchable memory (768MB) */
++			  0x82000000 0x00 0x40000000 0x12 0x30000000 0x0 0x0fff0000   /* non-prefetchable memory (256MB - 64KB) */
++			  0x81000000 0x00 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
+ 	};
+ 
+ 	pcie@14120000 {
+@@ -1292,9 +1292,9 @@
+ 		nvidia,aspm-l0s-entrance-latency-us = <3>;
+ 
+ 		bus-range = <0x0 0xff>;
+-		ranges = <0x81000000 0x0  0x32100000 0x0  0x32100000 0x0 0x00100000   /* downstream I/O (1MB) */
+-			  0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000   /* prefetchable memory (768MB) */
+-			  0x82000000 0x0  0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
++		ranges = <0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000   /* prefetchable memory (768MB) */
++			  0x82000000 0x00 0x40000000 0x12 0x70000000 0x0 0x0fff0000   /* non-prefetchable memory (256MB - 64KB) */
++			  0x81000000 0x00 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
+ 	};
+ 
+ 	pcie@14140000 {
+@@ -1337,9 +1337,9 @@
+ 		nvidia,aspm-l0s-entrance-latency-us = <3>;
+ 
+ 		bus-range = <0x0 0xff>;
+-		ranges = <0x81000000 0x0  0x34100000 0x0  0x34100000 0x0 0x00100000   /* downstream I/O (1MB) */
+-			  0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000   /* prefetchable memory (768MB) */
+-			  0x82000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
++		ranges = <0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000   /* prefetchable memory (768MB) */
++			  0x82000000 0x00 0x40000000 0x12 0xb0000000 0x0 0x0fff0000   /* non-prefetchable memory (256MB - 64KB) */
++			  0x81000000 0x00 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
+ 	};
+ 
+ 	pcie@14160000 {
+@@ -1382,9 +1382,9 @@
+ 		nvidia,aspm-l0s-entrance-latency-us = <3>;
+ 
+ 		bus-range = <0x0 0xff>;
+-		ranges = <0x81000000 0x0  0x36100000 0x0  0x36100000 0x0 0x00100000   /* downstream I/O (1MB) */
+-			  0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
+-			  0x82000000 0x0  0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
++		ranges = <0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
++			  0x82000000 0x00 0x40000000 0x17 0x40000000 0x0 0xbfff0000   /* non-prefetchable memory (3GB - 64KB) */
++			  0x81000000 0x00 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
+ 	};
+ 
+ 	pcie@14180000 {
+@@ -1427,9 +1427,9 @@
+ 		nvidia,aspm-l0s-entrance-latency-us = <3>;
+ 
+ 		bus-range = <0x0 0xff>;
+-		ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000   /* downstream I/O (1MB) */
+-			  0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
+-			  0x82000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
++		ranges = <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
++			  0x82000000 0x00 0x40000000 0x1b 0x40000000 0x0 0xbfff0000   /* non-prefetchable memory (3GB - 64KB) */
++			  0x81000000 0x00 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
+ 	};
+ 
+ 	pcie@141a0000 {
+@@ -1476,9 +1476,9 @@
+ 		nvidia,aspm-l0s-entrance-latency-us = <3>;
+ 
+ 		bus-range = <0x0 0xff>;
+-		ranges = <0x81000000 0x0  0x3a100000 0x0  0x3a100000 0x0 0x00100000   /* downstream I/O (1MB) */
+-			  0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
+-			  0x82000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
++		ranges = <0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
++			  0x82000000 0x00 0x40000000 0x1f 0x40000000 0x0 0xbfff0000   /* non-prefetchable memory (3GB - 64KB) */
++			  0x81000000 0x00 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
+ 	};
+ 
+ 	pcie_ep@14160000 {
+
+From patchwork Fri Jan 10 19:15:00 2020
+Content-Type: text/plain; charset="utf-8"
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+X-Patchwork-Submitter: Vidya Sagar <vidyas@nvidia.com>
+X-Patchwork-Id: 1221385
+Return-Path: <linux-pci-owner@vger.kernel.org>
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+ id <B5e18cd440002>; Fri, 10 Jan 2020 11:15:20 -0800
+From: Vidya Sagar <vidyas@nvidia.com>
+To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
+ <rjw@rjwysocki.net>, <lenb@kernel.org>, <andrew.murray@arm.com>,
+ <treding@nvidia.com>, <jonathanh@nvidia.com>
+CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
+ <linux-acpi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
+ <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
+ <sagar.tv@gmail.com>
+Subject: [PATCH V3 2/2] PCI: Add MCFG quirks for Tegra194 host controllers
+Date: Sat, 11 Jan 2020 00:45:00 +0530
+Message-ID: <20200110191500.9538-3-vidyas@nvidia.com>
+X-Mailer: git-send-email 2.17.1
+In-Reply-To: <20200110191500.9538-1-vidyas@nvidia.com>
+References: <20200106082709.14370-1-vidyas@nvidia.com>
+ <20200110191500.9538-1-vidyas@nvidia.com>
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+Sender: linux-pci-owner@vger.kernel.org
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+
+The PCIe controller in Tegra194 SoC is not completely ECAM-compliant.
+With the current hardware design limitations in place, ECAM can be enabled
+only for one controller (C5 controller to be precise) with bus numbers
+starting from 160 instead of 0. A different approach is taken to avoid this
+abnormal way of enabling ECAM for just one controller but to enable
+configuration space access for all the other controllers. In this approach,
+ops are added through MCFG quirk mechanism which access the configuration
+spaces by dynamically programming iATU (internal AddressTranslation Unit)
+to generate respective configuration accesses just like the way it is
+done in DesignWare core sub-system.
+
+Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
+Reported-by: kbuild test robot <lkp@intel.com>
+Acked-by: Thierry Reding <treding@nvidia.com>
+---
+V3:
+* Removed MCFG address hardcoding in pci_mcfg.c file
+* Started using 'dbi_base' for accessing root port's own config space
+* and using 'config_base' for accessing config space of downstream hierarchy
+
+V2:
+* Fixed build issues reported by kbuild test bot
+
+ drivers/acpi/pci_mcfg.c                    |   7 ++
+ drivers/pci/controller/dwc/Kconfig         |   3 +-
+ drivers/pci/controller/dwc/Makefile        |   2 +-
+ drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++
+ include/linux/pci-ecam.h                   |   1 +
+ 5 files changed, 113 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
+index 6b347d9920cc..707181408173 100644
+--- a/drivers/acpi/pci_mcfg.c
++++ b/drivers/acpi/pci_mcfg.c
+@@ -116,6 +116,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
+ 	THUNDER_ECAM_QUIRK(2, 12),
+ 	THUNDER_ECAM_QUIRK(2, 13),
+ 
++	{ "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
++	{ "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
++	{ "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
++	{ "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
++	{ "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
++	{ "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
++
+ #define XGENE_V1_ECAM_MCFG(rev, seg) \
+ 	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
+ 		&xgene_v1_pcie_ecam_ops }
+diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
+index 0830dfcfa43a..f5b9e75aceed 100644
+--- a/drivers/pci/controller/dwc/Kconfig
++++ b/drivers/pci/controller/dwc/Kconfig
+@@ -255,7 +255,8 @@ config PCIE_TEGRA194
+ 	select PHY_TEGRA194_P2U
+ 	help
+ 	  Say Y here if you want support for DesignWare core based PCIe host
+-	  controller found in NVIDIA Tegra194 SoC.
++	  controller found in NVIDIA Tegra194 SoC. ACPI platforms with Tegra194
++	  don't need to enable this.
+ 
+ config PCIE_UNIPHIER
+ 	bool "Socionext UniPhier PCIe controllers"
+diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
+index 8a637cfcf6e9..76a6c52b8500 100644
+--- a/drivers/pci/controller/dwc/Makefile
++++ b/drivers/pci/controller/dwc/Makefile
+@@ -17,7 +17,6 @@ obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
+ obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
+ obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+ obj-$(CONFIG_PCI_MESON) += pci-meson.o
+-obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
+ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
+ 
+ # The following drivers are for devices that use the generic ACPI
+@@ -33,4 +32,5 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
+ ifdef CONFIG_PCI
+ obj-$(CONFIG_ARM64) += pcie-al.o
+ obj-$(CONFIG_ARM64) += pcie-hisi.o
++obj-$(CONFIG_ARM64) += pcie-tegra194.o
+ endif
+diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
+index cbe95f0ea0ca..660f55caa8be 100644
+--- a/drivers/pci/controller/dwc/pcie-tegra194.c
++++ b/drivers/pci/controller/dwc/pcie-tegra194.c
+@@ -21,6 +21,8 @@
+ #include <linux/of_irq.h>
+ #include <linux/of_pci.h>
+ #include <linux/pci.h>
++#include <linux/pci-acpi.h>
++#include <linux/pci-ecam.h>
+ #include <linux/phy/phy.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/platform_device.h>
+@@ -285,6 +287,103 @@ struct tegra_pcie_dw {
+ 	struct dentry *debugfs;
+ };
+ 
++#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
++struct tegra194_pcie_acpi  {
++	void __iomem *config_base;
++	void __iomem *iatu_base;
++	void __iomem *dbi_base;
++};
++
++static int tegra194_acpi_init(struct pci_config_window *cfg)
++{
++	struct device *dev = cfg->parent;
++	struct tegra194_pcie_acpi *pcie;
++
++	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
++	if (!pcie)
++		return -ENOMEM;
++
++	pcie->config_base = cfg->win;
++	pcie->iatu_base = cfg->win + SZ_256K;
++	pcie->dbi_base = cfg->win + SZ_512K;
++	cfg->priv = pcie;
++
++	return 0;
++}
++
++static inline void atu_reg_write(struct tegra194_pcie_acpi *pcie, int index,
++				 u32 val, u32 reg)
++{
++	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
++
++	writel(val, pcie->iatu_base + offset + reg);
++}
++
++static void program_outbound_atu(struct tegra194_pcie_acpi *pcie, int index,
++				 int type, u64 cpu_addr, u64 pci_addr, u64 size)
++{
++	atu_reg_write(pcie, index, lower_32_bits(cpu_addr),
++		      PCIE_ATU_LOWER_BASE);
++	atu_reg_write(pcie, index, upper_32_bits(cpu_addr),
++		      PCIE_ATU_UPPER_BASE);
++	atu_reg_write(pcie, index, lower_32_bits(pci_addr),
++		      PCIE_ATU_LOWER_TARGET);
++	atu_reg_write(pcie, index, lower_32_bits(cpu_addr + size - 1),
++		      PCIE_ATU_LIMIT);
++	atu_reg_write(pcie, index, upper_32_bits(pci_addr),
++		      PCIE_ATU_UPPER_TARGET);
++	atu_reg_write(pcie, index, type, PCIE_ATU_CR1);
++	atu_reg_write(pcie, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
++}
++
++static void __iomem *tegra194_map_bus(struct pci_bus *bus,
++				      unsigned int devfn, int where)
++{
++	struct pci_config_window *cfg = bus->sysdata;
++	struct tegra194_pcie_acpi *pcie = cfg->priv;
++	u32 busdev;
++	int type;
++
++	if (bus->number < cfg->busr.start || bus->number > cfg->busr.end)
++		return NULL;
++
++	if (bus->number == cfg->busr.start) {
++		if (PCI_SLOT(devfn) == 0)
++			return pcie->dbi_base + where;
++		else
++			return NULL;
++	}
++
++	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
++		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
++
++	if (bus->parent->number == cfg->busr.start) {
++		if (PCI_SLOT(devfn) == 0)
++			type = PCIE_ATU_TYPE_CFG0;
++		else
++			return NULL;
++	} else {
++		type = PCIE_ATU_TYPE_CFG1;
++	}
++
++	program_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, type,
++			     cfg->res.start, busdev, SZ_256K);
++	return (void __iomem *)(pcie->config_base + where);
++}
++
++struct pci_ecam_ops tegra194_pcie_ops = {
++	.bus_shift	= 20,
++	.init		= tegra194_acpi_init,
++	.pci_ops	= {
++		.map_bus	= tegra194_map_bus,
++		.read		= pci_generic_config_read,
++		.write		= pci_generic_config_write,
++	}
++};
++#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
++
++#ifdef CONFIG_PCIE_TEGRA194
++
+ static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
+ {
+ 	return container_of(pci, struct tegra_pcie_dw, pci);
+@@ -1728,3 +1827,6 @@ MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
+ MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
+ MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
+ MODULE_LICENSE("GPL v2");
++
++#endif /* CONFIG_PCIE_TEGRA194 */
++
+diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
+index a73164c85e78..6156140dcbb6 100644
+--- a/include/linux/pci-ecam.h
++++ b/include/linux/pci-ecam.h
+@@ -57,6 +57,7 @@ extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
+ extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
+ extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
+ extern struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
++extern struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
+ #endif
+ 
+ #ifdef CONFIG_PCI_HOST_COMMON

RFC-PCI-tegra-Revert-raw_violation_fixup-for-tegra124.patch

@@ -0,0 +1,144 @@
+From patchwork Mon Apr 20 16:43:04 2020
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+ [2.15.34.211])
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+ Mon, 20 Apr 2020 09:43:06 -0700 (PDT)
+From: Nicolas Chauvet <kwizart@gmail.com>
+To: Manikanta Maddireddy <mmaddireddy@nvidia.com>,
+ Thierry Reding <thierry.reding@gmail.com>,
+ Jonathan Hunter <jonathanh@nvidia.com>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
+ linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
+ Nicolas Chauvet <kwizart@gmail.com>
+Subject: [RFC] PCI: tegra: Revert raw_violation_fixup for tegra124
+Date: Mon, 20 Apr 2020 18:43:04 +0200
+Message-Id: <20200420164304.28810-1-kwizart@gmail.com>
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+
+As reported in https://bugzilla.kernel.org/206217 , raw_violation_fixup
+is causing more harm than good in some common use-cases.
+
+This patch as RFC is a partial revert of the 191cd6fb5 commit:
+ "PCI: tegra: Add SW fixup for RAW violations" 
+that was first introduced in 5.3 kernel.
+This fix the following regression since then.
+
+
+When using both the network NIC and I/O on MMC this can lead to the
+following message on jetson-tk1:
+
+ NETDEV WATCHDOG: enp1s0 (r8169): transmit queue 0 timed out
+
+and
+
+ pcieport 0000:00:02.0: AER: Uncorrected (Non-Fatal) error received: 0000:01:00.0
+ r8169 0000:01:00.0: AER: PCIe Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, (Requester ID)
+ r8169 0000:01:00.0: AER:   device [10ec:8168] error status/mask=00004000/00400000
+ r8169 0000:01:00.0: AER:    [14] CmpltTO                (First)
+ r8169 0000:01:00.0: AER: can't recover (no error_detected callback)
+ pcieport 0000:00:02.0: AER: device recovery failed
+
+
+After that, the ethernet NIC isn't functional anymore even after reloading
+the module.
+After a reboot, this is reproducible by copying a large file over the
+ethernet NIC to the MMC.
+For some reasons this cannot be reproduced when the same file is copied
+to a tmpfs.
+
+
+This patch is RFC because it requires more understanding from Nvidia.
+ - Is the fixup (available in l4t downstrem) still needed for upstream ?
+ - Is there a need to update the fixup values for upstream ?
+ - If the fixup is reverted, does the hw bug can still be seen with
+   upstream ?
+
+Others can also provides more understanding:
+ - Conditions to reproduce the bug (or not)...
+
+
+Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
+Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
+---
+ drivers/pci/controller/pci-tegra.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
+index 3e64ba6a36a8..4027e074094a 100644
+--- a/drivers/pci/controller/pci-tegra.c
++++ b/drivers/pci/controller/pci-tegra.c
+@@ -2470,7 +2470,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
+ 	.program_uphy = true,
+ 	.update_clamp_threshold = true,
+ 	.program_deskew_time = false,
+-	.raw_violation_fixup = true,
++	.raw_violation_fixup = false,
+ 	.update_fc_timer = false,
+ 	.has_cache_bars = false,
+ 	.ectl.enable = false,

USB-pci-quirks-Add-Raspberry-Pi-4-quirk.patch

@@ -0,0 +1,671 @@
+From patchwork Tue Mar 24 18:28:09 2020
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+X-Patchwork-Id: 11456187
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+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+To: linux-kernel@vger.kernel.org, Florian Fainelli <f.fainelli@gmail.com>,
+ Ray Jui <rjui@broadcom.com>, Scott Branden <sbranden@broadcom.com>,
+ bcm-kernel-feedback-list@broadcom.com,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Subject: [PATCH v6 1/4] soc: bcm2835: Sync xHCI reset firmware property with
+ downstream
+Date: Tue, 24 Mar 2020 19:28:09 +0100
+Message-Id: <20200324182812.20420-2-nsaenzjulienne@suse.de>
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+ <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,
+ <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>
+Cc: tim.gover@raspberrypi.org, sergei.shtylyov@cogentembedded.com,
+ gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
+ linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, wahrenst@gmx.net
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+ linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
+
+The property is needed in order to trigger VL805's firmware load. Note
+that there is a gap between the property introduced and the previous
+one. This is also the case downstream.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ include/soc/bcm2835/raspberrypi-firmware.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h
+index 7800e12ee042..cc9cdbc66403 100644
+--- a/include/soc/bcm2835/raspberrypi-firmware.h
++++ b/include/soc/bcm2835/raspberrypi-firmware.h
+@@ -90,7 +90,7 @@ enum rpi_firmware_property_tag {
+ 	RPI_FIRMWARE_SET_PERIPH_REG =                         0x00038045,
+ 	RPI_FIRMWARE_GET_POE_HAT_VAL =                        0x00030049,
+ 	RPI_FIRMWARE_SET_POE_HAT_VAL =                        0x00030050,
+-
++	RPI_FIRMWARE_NOTIFY_XHCI_RESET =                      0x00030058,
+ 
+ 	/* Dispmanx TAGS */
+ 	RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE =                   0x00040001,
+
+From patchwork Tue Mar 24 18:28:10 2020
+Content-Type: text/plain; charset="utf-8"
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+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+To: linux-kernel@vger.kernel.org,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+ Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>,
+ bcm-kernel-feedback-list@broadcom.com
+Subject: [PATCH v6 2/4] firmware: raspberrypi: Introduce vl805 init routine
+Date: Tue, 24 Mar 2020 19:28:10 +0100
+Message-Id: <20200324182812.20420-3-nsaenzjulienne@suse.de>
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+Cc: tim.gover@raspberrypi.org, sergei.shtylyov@cogentembedded.com,
+ gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
+ linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, wahrenst@gmx.net
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+ linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
+
+On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
+loaded directly from an EEPROM or, if not present, by the SoC's
+VideCore. The function informs VideCore that VL805 was just reset, or
+requests for a probe defer.
+
+Based on Tim Gover's downstream implementation.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+Changes since v4:
+ - Inline function definition when RASPBERRYPI_FIRMWARE is not defined
+
+Changes since v1:
+ - Move include into .c file and add forward declaration to .h
+
+ drivers/firmware/raspberrypi.c             | 38 ++++++++++++++++++++++
+ include/soc/bcm2835/raspberrypi-firmware.h |  7 ++++
+ 2 files changed, 45 insertions(+)
+
+diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c
+index da26a584dca0..cbb495aff6a0 100644
+--- a/drivers/firmware/raspberrypi.c
++++ b/drivers/firmware/raspberrypi.c
+@@ -12,6 +12,7 @@
+ #include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
++#include <linux/pci.h>
+ #include <soc/bcm2835/raspberrypi-firmware.h>
+ 
+ #define MBOX_MSG(chan, data28)		(((data28) & ~0xf) | ((chan) & 0xf))
+@@ -286,6 +287,43 @@ struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node)
+ }
+ EXPORT_SYMBOL_GPL(rpi_firmware_get);
+ 
++/*
++ * On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
++ * loaded directly from an EEPROM or, if not present, by the SoC's VideCore.
++ * Inform VideCore that VL805 was just reset, or defer xhci's probe if not yet
++ * joinable trough the mailbox interface.
++ */
++int rpi_firmware_init_vl805(struct pci_dev *pdev)
++{
++	struct device_node *fw_np;
++	struct rpi_firmware *fw;
++	u32 dev_addr;
++	int ret;
++
++	fw_np = of_find_compatible_node(NULL, NULL,
++					"raspberrypi,bcm2835-firmware");
++	if (!fw_np)
++		return 0;
++
++	fw = rpi_firmware_get(fw_np);
++	of_node_put(fw_np);
++	if (!fw)
++		return -EPROBE_DEFER;
++
++	dev_addr = pdev->bus->number << 20 | PCI_SLOT(pdev->devfn) << 15 |
++		   PCI_FUNC(pdev->devfn) << 12;
++
++	ret = rpi_firmware_property(fw, RPI_FIRMWARE_NOTIFY_XHCI_RESET,
++				    &dev_addr, sizeof(dev_addr));
++	if (ret)
++		return ret;
++
++	dev_dbg(&pdev->dev, "loaded Raspberry Pi's VL805 firmware\n");
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(rpi_firmware_init_vl805);
++
+ static const struct of_device_id rpi_firmware_of_match[] = {
+ 	{ .compatible = "raspberrypi,bcm2835-firmware", },
+ 	{},
+diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h
+index cc9cdbc66403..3025aca3c358 100644
+--- a/include/soc/bcm2835/raspberrypi-firmware.h
++++ b/include/soc/bcm2835/raspberrypi-firmware.h
+@@ -10,6 +10,7 @@
+ #include <linux/of_device.h>
+ 
+ struct rpi_firmware;
++struct pci_dev;
+ 
+ enum rpi_firmware_property_status {
+ 	RPI_FIRMWARE_STATUS_REQUEST = 0,
+@@ -141,6 +142,7 @@ int rpi_firmware_property(struct rpi_firmware *fw,
+ int rpi_firmware_property_list(struct rpi_firmware *fw,
+ 			       void *data, size_t tag_size);
+ struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node);
++int rpi_firmware_init_vl805(struct pci_dev *pdev);
+ #else
+ static inline int rpi_firmware_property(struct rpi_firmware *fw, u32 tag,
+ 					void *data, size_t len)
+@@ -158,6 +160,11 @@ static inline struct rpi_firmware *rpi_firmware_get(struct device_node *firmware
+ {
+ 	return NULL;
+ }
++
++static inline int rpi_firmware_init_vl805(struct pci_dev *pdev)
++{
++	return 0;
++}
+ #endif
+ 
+ #endif /* __SOC_RASPBERRY_FIRMWARE_H__ */
+
+From patchwork Tue Mar 24 18:28:11 2020
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+ by mx2.suse.de (Postfix) with ESMTP id 1A1A0ABF4;
+ Tue, 24 Mar 2020 18:28:24 +0000 (UTC)
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+To: linux-kernel@vger.kernel.org,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ bcm-kernel-feedback-list@broadcom.com,
+ Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
+ Andrew Murray <amurray@thegoodpenguin.co.uk>
+Subject: [PATCH v6 3/4] PCI: brcmstb: Wait for Raspberry Pi's firmware when
+ present
+Date: Tue, 24 Mar 2020 19:28:11 +0100
+Message-Id: <20200324182812.20420-4-nsaenzjulienne@suse.de>
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+Cc: tim.gover@raspberrypi.org, sergei.shtylyov@cogentembedded.com,
+ gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
+ linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
+ Bjorn Helgaas <bhelgaas@google.com>, linux-arm-kernel@lists.infradead.org,
+ wahrenst@gmx.net
+Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
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+
+xHCI's PCI fixup, run at the end of pcie-brcmstb's probe, depends on
+RPi4's VideoCore firmware interface to be up and running. It's possible
+for both initializations to race, so make sure it's available prior to
+starting.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ drivers/pci/controller/pcie-brcmstb.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
+index 3a10e678c7f4..a3d3070a5832 100644
+--- a/drivers/pci/controller/pcie-brcmstb.c
++++ b/drivers/pci/controller/pcie-brcmstb.c
+@@ -28,6 +28,8 @@
+ #include <linux/string.h>
+ #include <linux/types.h>
+ 
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
+ #include "../pci.h"
+ 
+ /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
+@@ -917,11 +919,24 @@ static int brcm_pcie_probe(struct platform_device *pdev)
+ {
+ 	struct device_node *np = pdev->dev.of_node, *msi_np;
+ 	struct pci_host_bridge *bridge;
++	struct device_node *fw_np;
+ 	struct brcm_pcie *pcie;
+ 	struct pci_bus *child;
+ 	struct resource *res;
+ 	int ret;
+ 
++	/*
++	 * We have to wait for the Raspberry Pi's firmware interface to be up
++	 * as some PCI fixups depend on it.
++	 */
++	fw_np = of_find_compatible_node(NULL, NULL,
++					"raspberrypi,bcm2835-firmware");
++	if (fw_np && !rpi_firmware_get(fw_np)) {
++		of_node_put(fw_np);
++		return -EPROBE_DEFER;
++	}
++	of_node_put(fw_np);
++
+ 	bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
+ 	if (!bridge)
+ 		return -ENOMEM;
+
+From patchwork Tue Mar 24 18:28:12 2020
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+X-Patchwork-Id: 11456185
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+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+To: linux-kernel@vger.kernel.org,
+	Mathias Nyman <mathias.nyman@intel.com>
+Subject: [PATCH v6 4/4] USB: pci-quirks: Add Raspberry Pi 4 quirk
+Date: Tue, 24 Mar 2020 19:28:12 +0100
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+Cc: f.fainelli@gmail.com, sergei.shtylyov@cogentembedded.com,
+ gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>, tim.gover@raspberrypi.org,
+ bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org,
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+ linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
+
+On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
+loaded directly from an EEPROM or, if not present, by the SoC's
+VideCore. Inform VideCore that VL805 was just reset.
+
+Also, as this creates a dependency between USB_PCI and VideoCore's
+firmware interface. Since USB_PCI can't be set as a module neither this
+should.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+
+Changes since v5:
+ - Fix Kconfig issue with allmodconfig
+
+Changes since v4:
+ - Do not split up error message
+
+Changes since v3:
+ - Add more complete error message
+
+Changes since v1:
+ - Make RASPBERRYPI_FIRMWARE dependent on this quirk to make sure it
+   gets compiled when needed.
+
+ drivers/firmware/Kconfig      |  3 ++-
+ drivers/usb/host/pci-quirks.c | 16 ++++++++++++++++
+ 2 files changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
+index ea869addc89b..78ab2ad6d3f0 100644
+--- a/drivers/firmware/Kconfig
++++ b/drivers/firmware/Kconfig
+@@ -178,8 +178,9 @@ config ISCSI_IBFT
+ 	  Otherwise, say N.
+ 
+ config RASPBERRYPI_FIRMWARE
+-	tristate "Raspberry Pi Firmware Driver"
++	bool "Raspberry Pi Firmware Driver"
+ 	depends on BCM2835_MBOX
++	default USB_PCI
+ 	help
+ 	  This option enables support for communicating with the firmware on the
+ 	  Raspberry Pi.
+diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
+index beb2efa71341..0dc34668bb2a 100644
+--- a/drivers/usb/host/pci-quirks.c
++++ b/drivers/usb/host/pci-quirks.c
+@@ -16,6 +16,9 @@
+ #include <linux/export.h>
+ #include <linux/acpi.h>
+ #include <linux/dmi.h>
++
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
+ #include "pci-quirks.h"
+ #include "xhci-ext-caps.h"
+ 
+@@ -1243,11 +1246,24 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
+ 
+ static void quirk_usb_early_handoff(struct pci_dev *pdev)
+ {
++	int ret;
++
+ 	/* Skip Netlogic mips SoC's internal PCI USB controller.
+ 	 * This device does not need/support EHCI/OHCI handoff
+ 	 */
+ 	if (pdev->vendor == 0x184e)	/* vendor Netlogic */
+ 		return;
++
++	if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
++		ret = rpi_firmware_init_vl805(pdev);
++		if (ret) {
++			/* Firmware might be outdated, or something failed */
++			dev_warn(&pdev->dev,
++				 "Failed to load VL805's firmware: %d. Will continue to attempt to work, but bad things might happen. You should fix this...\n",
++				 ret);
++		}
++	}
++
+ 	if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
+ 			pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
+ 			pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&

arm-bcm2711-mmc-sdhci-iproc-Add-custom-set_power-callback.patch

@@ -0,0 +1,374 @@
+From 6c92ae1e452ff3f4648b1450c9a3233a2ca53feb Mon Sep 17 00:00:00 2001
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Fri, 6 Mar 2020 18:44:03 +0100
+Subject: mmc: sdhci: Introduce sdhci_set_power_and_bus_voltage()
+
+Some controllers diverge from the standard way of setting power and need
+their bus voltage register to be configured regardless of the whether
+they use regulators. As this is a common pattern across sdhci hosts,
+create a helper function.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/20200306174413.20634-2-nsaenzjulienne@suse.de
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci.c | 19 +++++++++++++++++++
+ drivers/mmc/host/sdhci.h |  3 +++
+ 2 files changed, 22 insertions(+)
+
+diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
+index c59566363a42..525e0c971c6a 100644
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -2010,6 +2010,25 @@ void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
+ }
+ EXPORT_SYMBOL_GPL(sdhci_set_power);
+ 
++/*
++ * Some controllers need to configure a valid bus voltage on their power
++ * register regardless of whether an external regulator is taking care of power
++ * supply. This helper function takes care of it if set as the controller's
++ * sdhci_ops.set_power callback.
++ */
++void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
++				     unsigned char mode,
++				     unsigned short vdd)
++{
++	if (!IS_ERR(host->mmc->supply.vmmc)) {
++		struct mmc_host *mmc = host->mmc;
++
++		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
++	}
++	sdhci_set_power_noreg(host, mode, vdd);
++}
++EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
++
+ /*****************************************************************************\
+  *                                                                           *
+  * MMC callbacks                                                             *
+diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
+index 249635692112..851b81565f46 100644
+--- a/drivers/mmc/host/sdhci.h
++++ b/drivers/mmc/host/sdhci.h
+@@ -772,6 +772,9 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
+ void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
+ void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
+ 		     unsigned short vdd);
++void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
++				     unsigned char mode,
++				     unsigned short vdd);
+ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
+ 			   unsigned short vdd);
+ void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
+-- 
+cgit 1.2-0.3.lf.el7
+From f87391eec2c5f54269e64d655da19f2c32515e4c Mon Sep 17 00:00:00 2001
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Fri, 6 Mar 2020 18:44:11 +0100
+Subject: mmc: sdhci: iproc: Add custom set_power() callback for bcm2711
+
+The controller needs a valid bus voltage in its power register
+regardless of whether an external regulator is taking care of the power
+supply.
+
+The sdhci core already provides a helper function for this,
+sdhci_set_power_and_bus_voltage(), so create a bcm2711 specific 'struct
+sdhci_ops' which makes use of it.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/20200306174413.20634-10-nsaenzjulienne@suse.de
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-iproc.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
+index f4f5f0a70cda..225603148d7d 100644
+--- a/drivers/mmc/host/sdhci-iproc.c
++++ b/drivers/mmc/host/sdhci-iproc.c
+@@ -261,9 +261,24 @@ static const struct sdhci_iproc_data bcm2835_data = {
+ 	.mmc_caps = 0x00000000,
+ };
+ 
++static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
++	.read_l = sdhci_iproc_readl,
++	.read_w = sdhci_iproc_readw,
++	.read_b = sdhci_iproc_readb,
++	.write_l = sdhci_iproc_writel,
++	.write_w = sdhci_iproc_writew,
++	.write_b = sdhci_iproc_writeb,
++	.set_clock = sdhci_set_clock,
++	.set_power = sdhci_set_power_and_bus_voltage,
++	.get_max_clock = sdhci_iproc_get_max_clock,
++	.set_bus_width = sdhci_set_bus_width,
++	.reset = sdhci_reset,
++	.set_uhs_signaling = sdhci_set_uhs_signaling,
++};
++
+ static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
+ 	.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
+-	.ops = &sdhci_iproc_32only_ops,
++	.ops = &sdhci_iproc_bcm2711_ops,
+ };
+ 
+ static const struct sdhci_iproc_data bcm2711_data = {
+-- 
+cgit 1.2-0.3.lf.el7
+From patchwork Fri Mar  6 17:44:12 2020
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+X-Patchwork-Id: 11424593
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+ Fri,  6 Mar 2020 17:44:32 +0000 (UTC)
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+To: adrian.hunter@intel.com, linux-kernel@vger.kernel.org,
+ Rob Herring <robh+dt@kernel.org>,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Subject: [PATCH v2 10/11] ARM: dts: bcm2711: Update expgpio's GPIO labels
+Date: Fri,  6 Mar 2020 18:44:12 +0100
+Message-Id: <20200306174413.20634-11-nsaenzjulienne@suse.de>
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+Cc: stefan.wahren@i2se.com, devicetree@vger.kernel.org, f.fainelli@gmail.com,
+ linux-mmc@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com,
+ linux-rpi-kernel@lists.infradead.org, phil@raspberrypi.com,
+ linux-arm-kernel@lists.infradead.org
+Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
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+
+The 6th line of the GPIO expander is used to power the board's SD card.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+index 1d4b589fe233..b0ea8233b636 100644
+--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
++++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+@@ -68,7 +68,7 @@ expgpio: gpio {
+ 				  "GLOBAL_RESET",
+ 				  "VDD_SD_IO_SEL",
+ 				  "CAM_GPIO",
+-				  "",
++				  "SD_PWR_ON",
+ 				  "";
+ 		status = "okay";
+ 	};
+From patchwork Fri Mar  6 17:44:13 2020
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+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+To: adrian.hunter@intel.com, linux-kernel@vger.kernel.org,
+ Rob Herring <robh+dt@kernel.org>,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Subject: [PATCH v2 11/11] ARM: dts: bcm2711: Add vmmc regulator in emmc2
+Date: Fri,  6 Mar 2020 18:44:13 +0100
+Message-Id: <20200306174413.20634-12-nsaenzjulienne@suse.de>
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+
+The SD card power can be controlled trough a pin routed into the board's
+external GPIO expander. Turn that into a regulator and provide it to
+emmc2.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+index b0ea8233b636..a2da058396fe 100644
+--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
++++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+@@ -55,6 +55,16 @@ sd_io_1v8_reg: sd_io_1v8_reg {
+ 			  3300000 0x0>;
+ 		status = "okay";
+ 	};
++
++	sd_vcc_reg: sd_vcc_reg {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-sd";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		enable-active-high;
++		gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
++	};
+ };
+ 
+ &firmware {
+@@ -173,6 +183,7 @@ brcmf: wifi@1 {
+ /* EMMC2 is used to drive the SD card */
+ &emmc2 {
+ 	vqmmc-supply = <&sd_io_1v8_reg>;
++	vmmc-supply = <&sd_vcc_reg>;
+ 	broken-cd;
+ 	status = "okay";
+ };

arm-bcm2835-serial-8250_early-support-aux-uart.patch

@@ -0,0 +1,47 @@
+From 57b76faf1d7860f070a1ee2d0b7eccd9f37ecc55 Mon Sep 17 00:00:00 2001
+From: Matthias Brugger <mbrugger@suse.com>
+Date: Sun, 26 Jan 2020 13:33:14 +0100
+Subject: serial: 8250_early: Add earlycon for BCM2835 aux uart
+
+Define the OF early console for BCM2835 aux UART, which can be enabled
+by passing "earlycon" on the boot command line. This UART is found on
+BCM283x and BCM27xx SoCs, a.k.a. Raspberry Pi in its variants.
+
+Signed-off-by: Matthias Brugger <mbrugger@suse.com>
+Link: https://lore.kernel.org/r/20200126123314.3558-1-matthias.bgg@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/8250/8250_bcm2835aux.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/tty/serial/8250/8250_bcm2835aux.c b/drivers/tty/serial/8250/8250_bcm2835aux.c
+index e70e3cc30050..5cc03bf24f85 100644
+--- a/drivers/tty/serial/8250/8250_bcm2835aux.c
++++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
+@@ -137,6 +137,24 @@ static struct platform_driver bcm2835aux_serial_driver = {
+ };
+ module_platform_driver(bcm2835aux_serial_driver);
+ 
++#ifdef CONFIG_SERIAL_8250_CONSOLE
++
++static int __init early_bcm2835aux_setup(struct earlycon_device *device,
++					const char *options)
++{
++	if (!device->port.membase)
++		return -ENODEV;
++
++	device->port.iotype = UPIO_MEM32;
++	device->port.regshift = 2;
++
++	return early_serial8250_setup(device, NULL);
++}
++
++OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart",
++		    early_bcm2835aux_setup);
++#endif
++
+ MODULE_DESCRIPTION("BCM2835 auxiliar UART driver");
+ MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
+ MODULE_LICENSE("GPL v2");
+-- 
+cgit 1.2-0.3.lf.el7

arm-make-highpte-not-expert.patch

@@ -0,0 +1,31 @@
+From 19908e5fe3e63ed2d39f0a8a9135f35fd428d766 Mon Sep 17 00:00:00 2001
+From: Jon Masters <jcm@redhat.com>
+Date: Thu, 18 Jul 2019 15:47:26 -0400
+Subject: [PATCH] arm: make CONFIG_HIGHPTE optional without CONFIG_EXPERT
+
+We will use this to force CONFIG_HIGHPTE off on LPAE for now
+
+Signed-off-by: Jon Masters <jcm@redhat.com>
+---
+ arch/arm/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 2bf1ce39a96d..e792b3e60095 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1644,9 +1644,9 @@ config HIGHMEM
+ 	  If unsure, say n.
+ 
+ config HIGHPTE
+-	bool "Allocate 2nd-level pagetables from highmem" if EXPERT
++	bool "Allocate 2nd-level pagetables from highmem"
+ 	depends on HIGHMEM
+-	default y
++	default n
+ 	help
+ 	  The VM uses one page of physical memory for each page table.
+ 	  For systems with a lot of processes, this can use a lot of
+-- 
+2.17.2
+

arm-sdhci-esdhc-imx-fixes.patch

@@ -1,57 +0,0 @@
-From patchwork Thu Jun 28 08:13:30 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [2/3] mmc: sdhci: add quirk to prevent higher speed modes
-From: Stefan Agner <stefan@agner.ch>
-X-Patchwork-Id: 10493273
-Message-Id: <20180628081331.13051-3-stefan@agner.ch>
-To: adrian.hunter@intel.com, ulf.hansson@linaro.org
-Cc: fabio.estevam@nxp.com, haibo.chen@nxp.com, aisheng.dong@nxp.com,
- michael@amarulasolutions.com, rmk+kernel@armlinux.org.uk,
- linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
- Stefan Agner <stefan@agner.ch>
-Date: Thu, 28 Jun 2018 10:13:30 +0200
-
-Some hosts are capable of running higher speed modes but do not
-have the board support for it. Introduce a quirk which prevents
-the stack from using modes running at 100MHz or faster.
-
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- drivers/mmc/host/sdhci.c | 8 ++++++++
- drivers/mmc/host/sdhci.h | 2 ++
- 2 files changed, 10 insertions(+)
-
-diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
-index 1c828e0e9905..8ac257dfaab3 100644
---- a/drivers/mmc/host/sdhci.c
-+++ b/drivers/mmc/host/sdhci.c
-@@ -3749,6 +3749,14 @@ int sdhci_setup_host(struct sdhci_host *host)
- 		}
- 	}
- 
-+	if (host->quirks2 & SDHCI_QUIRK2_NO_UHS_HS200_HS400) {
-+		host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
-+				 SDHCI_SUPPORT_DDR50);
-+
-+		mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HSX00_1_2V |
-+				MMC_CAP2_HS400_ES);
-+	}
-+
- 	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
- 		host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
- 				 SDHCI_SUPPORT_DDR50);
-diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
-index 23966f887da6..cb2433d6d61f 100644
---- a/drivers/mmc/host/sdhci.h
-+++ b/drivers/mmc/host/sdhci.h
-@@ -450,6 +450,8 @@ struct sdhci_host {
-  * block count.
-  */
- #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT			(1<<18)
-+/* Do not support any higher speeds (>50MHz) */
-+#define SDHCI_QUIRK2_NO_UHS_HS200_HS400			(1<<19)
- 
- 	int irq;		/* Device IRQ */
- 	void __iomem *ioaddr;	/* Mapped address */

arm64-Fix-some-GPIO-setup-on-Pinebook-Pro.patch

@@ -0,0 +1,50 @@
+From c45fbddb2cd7ce6198e33ebe6dc4c1301d7875d4 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Sun, 19 Apr 2020 20:50:08 +0100
+Subject: [PATCH] Fix some GPIO setup on Pinebook Pro
+
+This patchset contains two small fixes for the dts of the Pinebook Pro.
+The first fixes inverted logic on the headphone detect GPIO.
+The second patch fixes unreliable DC charger detection.
+
+Tobias Schramm (2):
+  arm64: dts: rockchip: fix inverted headphone detection
+  arm64: dts: rockchip: enable DC charger detection pullup
+
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+index 5ea281b55fe2..294d21bf45f5 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -147,7 +147,7 @@ es8316-sound {
+ 			"Speaker", "Speaker Amplifier OUTL",
+ 			"Speaker", "Speaker Amplifier OUTR";
+ 
+-		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
++		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ 		simple-audio-card,aux-devs = <&speaker_amp>;
+ 		simple-audio-card,pin-switches = "Speaker";
+ 
+@@ -788,13 +788,13 @@ lidbtn_gpio: lidbtn-gpio {
+ 
+ 	dc-charger {
+ 		dc_det_gpio: dc-det-gpio {
+-			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
++			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ 
+ 	es8316 {
+ 		hp_det_gpio: hp-det-gpio {
+-			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
++			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ 
+-- 
+2.26.1
+

arm64-a64-mbus.patch

@@ -0,0 +1,69 @@
+From daae9f66b29a04a94708b1b5a9b61e3ee14df031 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Mon, 10 Feb 2020 18:06:52 +0100
+Subject: [PATCH 1/2] dt-bindings: interconnect: sunxi: Add A64 MBUS compatible
+
+A64 contains MBUS controller. Add a compatible for it.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ .../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml  | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
+index 9370e64992dd..aa0738b4d534 100644
+--- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
++++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
+@@ -30,6 +30,7 @@ properties:
+     enum:
+       - allwinner,sun5i-a13-mbus
+       - allwinner,sun8i-h3-mbus
++      - allwinner,sun50i-a64-mbus
+ 
+   reg:
+     maxItems: 1
+-- 
+2.24.1
+
+From 410bb2be7e1f1d329c238e2d6d06b6c25dcee404 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Mon, 10 Feb 2020 18:06:54 +0100
+Subject: [PATCH 2/2] arm64: dts: allwinner: a64: Add MBUS controller node
+
+A64 contains MBUS, which is the bus used by DMA devices to access
+system memory.
+
+MBUS controller is responsible for arbitration between channels based
+on set priority and can do some other things as well, like report
+bandwidth used. It also maps RAM region to different address than CPU.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 862b47dc9dc9..251c91724de1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 {
+ 			status = "disabled";
+ 		};
+ 
++		mbus: dram-controller@1c62000 {
++			compatible = "allwinner,sun50i-a64-mbus";
++			reg = <0x01c62000 0x1000>;
++			clocks = <&ccu 112>;
++			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
++			#interconnect-cells = <1>;
++		};
++
+ 		csi: csi@1cb0000 {
+ 			compatible = "allwinner,sun50i-a64-csi";
+ 			reg = <0x01cb0000 0x1000>;
+-- 
+2.24.1
+

arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch

@@ -0,0 +1,200 @@
+From patchwork Tue Feb 11 13:48:28 2020
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+X-Patchwork-Id: 11375533
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+From: Alifer Moraes <alifer.wsdm@gmail.com>
+To: robh+dt@kernel.org
+Subject: [PATCH] arm64: dts: imx8mq-phanbell: Add support for ethernet
+Date: Tue, 11 Feb 2020 10:48:28 -0300
+Message-Id: <20200211134828.138-1-alifer.wsdm@gmail.com>
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+Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, festevam@gmail.com,
+ s.hauer@pengutronix.de, linux-kernel@vger.kernel.org,
+ Alifer Moraes <alifer.wsdm@gmail.com>, marco.franchi@nxp.com,
+ shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org
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+
+Add support for ethernet on Google's i.MX 8MQ Phanbell
+
+Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
+---
+ .../boot/dts/freescale/imx8mq-phanbell.dts    | 41 +++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+index 3f2a489a4ad8..16ed13c44a47 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+@@ -201,6 +201,27 @@
+ 	};
+ };
+ 
++&fec1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_fec1>;
++	phy-mode = "rgmii-id";
++	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
++	phy-reset-duration = <10>;
++	phy-reset-post-delay = <30>;
++	phy-handle = <&ethphy0>;
++	fsl,magic-packet;
++	status = "okay";
++
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		ethphy0: ethernet-phy@0 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <0>;
++		};
++	};
++};
++
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_uart1>;
+@@ -254,6 +275,26 @@
+ };
+ 
+ &iomuxc {
++	pinctrl_fec1: fec1grp {
++		fsl,pins = <
++			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
++			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
++			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
++			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
++			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
++			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
++			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
++			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
++			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
++			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
++			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
++			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
++			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
++			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
++			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
++		>;
++	};
++
+ 	pinctrl_i2c1: i2c1grp {
+ 		fsl,pins = <
+ 			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f

arm64-pinctrl-bcm2835-Add-support-for-all-BCM2711-GPIOs.patch

@@ -0,0 +1,868 @@
+From patchwork Mon Jan 27 18:15:05 2020
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Linus Walleij <linus.walleij@linaro.org>, Ray Jui <rjui@broadcom.com>,
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+Subject: [RFC PATCH 1/4] pinctrl: bcm2835: Drop unused define
+Date: Mon, 27 Jan 2020 19:15:05 +0100
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+Cc: Stefan Wahren <stefan.wahren@i2se.com>, linux-gpio@vger.kernel.org,
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+
+There is no usage for this define, so drop it.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ drivers/pinctrl/bcm/pinctrl-bcm2835.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+index 0de1a3a..3fc2638 100644
+--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+@@ -40,9 +40,6 @@
+ #define BCM2835_NUM_BANKS 2
+ #define BCM2835_NUM_IRQS  3
+ 
+-#define BCM2835_PIN_BITMAP_SZ \
+-	DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
+-
+ /* GPIO register offsets */
+ #define GPFSEL0		0x0	/* Function Select */
+ #define GPSET0		0x1c	/* Pin Output Set */
+
+From patchwork Mon Jan 27 18:15:06 2020
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Linus Walleij <linus.walleij@linaro.org>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>
+Subject: [RFC PATCH 2/4] pinctrl: bcm2835: Refactor platform data
+Date: Mon, 27 Jan 2020 19:15:06 +0100
+Message-Id: <1580148908-4863-3-git-send-email-stefan.wahren@i2se.com>
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+Cc: Stefan Wahren <stefan.wahren@i2se.com>, linux-gpio@vger.kernel.org,
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+
+This prepares the platform data to be easier to extend for more GPIOs.
+Except of this there is no functional change.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ drivers/pinctrl/bcm/pinctrl-bcm2835.c | 57 +++++++++++++++++++++++++++--------
+ 1 file changed, 44 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+index 3fc2638..ffd069a 100644
+--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+@@ -82,6 +82,7 @@ struct bcm2835_pinctrl {
+ 
+ 	struct pinctrl_dev *pctl_dev;
+ 	struct gpio_chip gpio_chip;
++	struct pinctrl_desc pctl_desc;
+ 	struct pinctrl_gpio_range gpio_range;
+ 
+ 	raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
+@@ -1051,7 +1052,7 @@ static const struct pinconf_ops bcm2711_pinconf_ops = {
+ 	.pin_config_set = bcm2711_pinconf_set,
+ };
+ 
+-static struct pinctrl_desc bcm2835_pinctrl_desc = {
++static const struct pinctrl_desc bcm2835_pinctrl_desc = {
+ 	.name = MODULE_NAME,
+ 	.pins = bcm2835_gpio_pins,
+ 	.npins = ARRAY_SIZE(bcm2835_gpio_pins),
+@@ -1061,19 +1062,47 @@ static struct pinctrl_desc bcm2835_pinctrl_desc = {
+ 	.owner = THIS_MODULE,
+ };
+ 
+-static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
++static const struct pinctrl_desc bcm2711_pinctrl_desc = {
++	.name = MODULE_NAME,
++	.pins = bcm2835_gpio_pins,
++	.npins = ARRAY_SIZE(bcm2835_gpio_pins),
++	.pctlops = &bcm2835_pctl_ops,
++	.pmxops = &bcm2835_pmx_ops,
++	.confops = &bcm2711_pinconf_ops,
++	.owner = THIS_MODULE,
++};
++
++static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
+ 	.name = MODULE_NAME,
+ 	.npins = BCM2835_NUM_GPIOS,
+ };
+ 
++struct bcm_plat_data {
++	const struct gpio_chip *gpio_chip;
++	const struct pinctrl_desc *pctl_desc;
++	const struct pinctrl_gpio_range *gpio_range;
++};
++
++static const struct bcm_plat_data bcm2835_plat_data = {
++	.gpio_chip = &bcm2835_gpio_chip,
++	.pctl_desc = &bcm2835_pinctrl_desc,
++	.gpio_range = &bcm2835_pinctrl_gpio_range,
++};
++
++static const struct bcm_plat_data bcm2711_plat_data = {
++	.gpio_chip = &bcm2835_gpio_chip,
++	.pctl_desc = &bcm2711_pinctrl_desc,
++	.gpio_range = &bcm2835_pinctrl_gpio_range,
++};
++
+ static const struct of_device_id bcm2835_pinctrl_match[] = {
+ 	{
+ 		.compatible = "brcm,bcm2835-gpio",
+-		.data = &bcm2835_pinconf_ops,
++		.data = &bcm2835_plat_data,
+ 	},
+ 	{
+ 		.compatible = "brcm,bcm2711-gpio",
+-		.data = &bcm2711_pinconf_ops,
++		.data = &bcm2711_plat_data,
+ 	},
+ 	{}
+ };
+@@ -1083,6 +1112,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct bcm2835_pinctrl *pc;
++	struct bcm_plat_data *pdata;
+ 	struct gpio_irq_chip *girq;
+ 	struct resource iomem;
+ 	int err, i;
+@@ -1108,7 +1138,13 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
+ 	if (IS_ERR(pc->base))
+ 		return PTR_ERR(pc->base);
+ 
+-	pc->gpio_chip = bcm2835_gpio_chip;
++	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
++	if (!match)
++		return -EINVAL;
++
++	pdata = (struct bcm_plat_data *)match->data;
++
++	memcpy(&pc->gpio_chip, pdata->gpio_chip, sizeof(pc->gpio_chip));
+ 	pc->gpio_chip.parent = dev;
+ 	pc->gpio_chip.of_node = np;
+ 
+@@ -1159,19 +1195,14 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
+ 		return err;
+ 	}
+ 
+-	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
+-	if (match) {
+-		bcm2835_pinctrl_desc.confops =
+-			(const struct pinconf_ops *)match->data;
+-	}
+-
+-	pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
++	memcpy(&pc->pctl_desc, pdata->pctl_desc, sizeof(pc->pctl_desc));
++	pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
+ 	if (IS_ERR(pc->pctl_dev)) {
+ 		gpiochip_remove(&pc->gpio_chip);
+ 		return PTR_ERR(pc->pctl_dev);
+ 	}
+ 
+-	pc->gpio_range = bcm2835_pinctrl_gpio_range;
++	memcpy(&pc->gpio_range, pdata->gpio_range, sizeof(pc->gpio_range));
+ 	pc->gpio_range.base = pc->gpio_chip.base;
+ 	pc->gpio_range.gc = &pc->gpio_chip;
+ 	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
+
+From patchwork Mon Jan 27 18:15:07 2020
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+X-Patchwork-Id: 11353089
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Linus Walleij <linus.walleij@linaro.org>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>
+Subject: [RFC PATCH 3/4] pinctrl: bcm2835: Add support for all GPIOs on
+ BCM2711
+Date: Mon, 27 Jan 2020 19:15:07 +0100
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+
+The BCM2711 supports 58 GPIOs. So extend pinctrl and GPIOs accordingly.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ drivers/pinctrl/bcm/pinctrl-bcm2835.c | 54 +++++++++++++++++++++++++++--------
+ 1 file changed, 42 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+index ffd069a..41e7bf9 100644
+--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+@@ -37,6 +37,7 @@
+ 
+ #define MODULE_NAME "pinctrl-bcm2835"
+ #define BCM2835_NUM_GPIOS 54
++#define BCM2711_NUM_GPIOS 58
+ #define BCM2835_NUM_BANKS 2
+ #define BCM2835_NUM_IRQS  3
+ 
+@@ -78,7 +79,7 @@ struct bcm2835_pinctrl {
+ 
+ 	/* note: locking assumes each bank will have its own unsigned long */
+ 	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
+-	unsigned int irq_type[BCM2835_NUM_GPIOS];
++	unsigned int irq_type[BCM2711_NUM_GPIOS];
+ 
+ 	struct pinctrl_dev *pctl_dev;
+ 	struct gpio_chip gpio_chip;
+@@ -145,6 +146,10 @@ static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
+ 	BCM2835_GPIO_PIN(51),
+ 	BCM2835_GPIO_PIN(52),
+ 	BCM2835_GPIO_PIN(53),
++	BCM2835_GPIO_PIN(54),
++	BCM2835_GPIO_PIN(55),
++	BCM2835_GPIO_PIN(56),
++	BCM2835_GPIO_PIN(57),
+ };
+ 
+ /* one pin per group */
+@@ -203,6 +208,10 @@ static const char * const bcm2835_gpio_groups[] = {
+ 	"gpio51",
+ 	"gpio52",
+ 	"gpio53",
++	"gpio54",
++	"gpio55",
++	"gpio56",
++	"gpio57",
+ };
+ 
+ enum bcm2835_fsel {
+@@ -353,6 +362,22 @@ static const struct gpio_chip bcm2835_gpio_chip = {
+ 	.can_sleep = false,
+ };
+ 
++static const struct gpio_chip bcm2711_gpio_chip = {
++	.label = "pinctrl-bcm2711",
++	.owner = THIS_MODULE,
++	.request = gpiochip_generic_request,
++	.free = gpiochip_generic_free,
++	.direction_input = bcm2835_gpio_direction_input,
++	.direction_output = bcm2835_gpio_direction_output,
++	.get_direction = bcm2835_gpio_get_direction,
++	.get = bcm2835_gpio_get,
++	.set = bcm2835_gpio_set,
++	.set_config = gpiochip_generic_config,
++	.base = -1,
++	.ngpio = BCM2711_NUM_GPIOS,
++	.can_sleep = false,
++};
++
+ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
+ 					 unsigned int bank, u32 mask)
+ {
+@@ -399,7 +424,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
+ 		bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
+ 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
+ 		break;
+-	case 2: /* IRQ2 covers GPIOs 46-53 */
++	case 2: /* IRQ2 covers GPIOs 46-57 */
+ 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
+ 		break;
+ 	}
+@@ -618,7 +643,7 @@ static struct irq_chip bcm2835_gpio_irq_chip = {
+ 
+ static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
+ {
+-	return ARRAY_SIZE(bcm2835_gpio_groups);
++	return BCM2835_NUM_GPIOS;
+ }
+ 
+ static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
+@@ -776,7 +801,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ 		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
+ 		if (err)
+ 			goto out;
+-		if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
++		if (pin >= pc->pctl_desc.npins) {
+ 			dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
+ 				np, pin);
+ 			err = -EINVAL;
+@@ -852,7 +877,7 @@ static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
+ {
+ 	/* every pin can do every function */
+ 	*groups = bcm2835_gpio_groups;
+-	*num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
++	*num_groups = BCM2835_NUM_GPIOS;
+ 
+ 	return 0;
+ }
+@@ -1055,7 +1080,7 @@ static const struct pinconf_ops bcm2711_pinconf_ops = {
+ static const struct pinctrl_desc bcm2835_pinctrl_desc = {
+ 	.name = MODULE_NAME,
+ 	.pins = bcm2835_gpio_pins,
+-	.npins = ARRAY_SIZE(bcm2835_gpio_pins),
++	.npins = BCM2835_NUM_GPIOS,
+ 	.pctlops = &bcm2835_pctl_ops,
+ 	.pmxops = &bcm2835_pmx_ops,
+ 	.confops = &bcm2835_pinconf_ops,
+@@ -1063,9 +1088,9 @@ static const struct pinctrl_desc bcm2835_pinctrl_desc = {
+ };
+ 
+ static const struct pinctrl_desc bcm2711_pinctrl_desc = {
+-	.name = MODULE_NAME,
++	.name = "pinctrl-bcm2711",
+ 	.pins = bcm2835_gpio_pins,
+-	.npins = ARRAY_SIZE(bcm2835_gpio_pins),
++	.npins = BCM2711_NUM_GPIOS,
+ 	.pctlops = &bcm2835_pctl_ops,
+ 	.pmxops = &bcm2835_pmx_ops,
+ 	.confops = &bcm2711_pinconf_ops,
+@@ -1077,6 +1102,11 @@ static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
+ 	.npins = BCM2835_NUM_GPIOS,
+ };
+ 
++static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
++	.name = "pinctrl-bcm2711",
++	.npins = BCM2711_NUM_GPIOS,
++};
++
+ struct bcm_plat_data {
+ 	const struct gpio_chip *gpio_chip;
+ 	const struct pinctrl_desc *pctl_desc;
+@@ -1090,9 +1120,9 @@ static const struct bcm_plat_data bcm2835_plat_data = {
+ };
+ 
+ static const struct bcm_plat_data bcm2711_plat_data = {
+-	.gpio_chip = &bcm2835_gpio_chip,
++	.gpio_chip = &bcm2711_gpio_chip,
+ 	.pctl_desc = &bcm2711_pinctrl_desc,
+-	.gpio_range = &bcm2835_pinctrl_gpio_range,
++	.gpio_range = &bcm2711_pinctrl_gpio_range,
+ };
+ 
+ static const struct of_device_id bcm2835_pinctrl_match[] = {
+@@ -1118,8 +1148,8 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
+ 	int err, i;
+ 	const struct of_device_id *match;
+ 
+-	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
+-	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
++	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
++	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
+ 
+ 	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
+ 	if (!pc)
+
+From patchwork Mon Jan 27 18:15:08 2020
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Linus Walleij <linus.walleij@linaro.org>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>
+Subject: [RFC PATCH 4/4] ARM: dts: bcm2711-rpi-4-b: Add SoC GPIO labels
+Date: Mon, 27 Jan 2020 19:15:08 +0100
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+Cc: Stefan Wahren <stefan.wahren@i2se.com>, linux-gpio@vger.kernel.org,
+ bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org,
+ devicetree@vger.kernel.org
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+ linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
+
+This adds the labels for all the SoC GPIOs on the Raspberry Pi 4.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 74 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+
+diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+index 1b5a835..6607e2e 100644
+--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
++++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+@@ -71,6 +71,80 @@
+ 	};
+ };
+ 
++&gpio {
++	/*
++	 * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
++	 * the official GPU firmware DT blob.
++	 *
++	 * Legend:
++	 * "NC" = not connected (no rail from the SoC)
++	 * "FOO" = GPIO line named "FOO" on the schematic
++	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
++	 */
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
++			  "SDA1",
++			  "SCL1",
++			  "GPIO_GCLK",
++			  "GPIO5",
++			  "GPIO6",
++			  "SPI_CE1_N",
++			  "SPI_CE0_N",
++			  "SPI_MISO",
++			  "SPI_MOSI",
++			  "SPI_SCLK",
++			  "GPIO12",
++			  "GPIO13",
++			  /* Serial port */
++			  "TXD1",
++			  "RXD1",
++			  "GPIO16",
++			  "GPIO17",
++			  "GPIO18",
++			  "GPIO19",
++			  "GPIO20",
++			  "GPIO21",
++			  "GPIO22",
++			  "GPIO23",
++			  "GPIO24",
++			  "GPIO25",
++			  "GPIO26",
++			  "GPIO27",
++			  "RGMII_MDIO",
++			  "RGMIO_MDC",
++			  /* Used by BT module */
++			  "CTS0",
++			  "RTS0",
++			  "TXD0",
++			  "RXD0",
++			  /* Used by Wifi */
++			  "SD1_CLK",
++			  "SD1_CMD",
++			  "SD1_DATA0",
++			  "SD1_DATA1",
++			  "SD1_DATA2",
++			  "SD1_DATA3",
++			  /* Shared with SPI flash */
++			  "PWM0_MISO",
++			  "PWM1_MOSI",
++			  "STATUS_LED_G_CLK",
++			  "SPIFLASH_CE_N",
++			  "SDA0",
++			  "SCL0",
++			  "RGMII_RXCLK",
++			  "RGMII_RXCTL",
++			  "RGMII_RXD0",
++			  "RGMII_RXD1",
++			  "RGMII_RXD2",
++			  "RGMII_RXD3",
++			  "RGMII_TXCLK",
++			  "RGMII_TXCTL",
++			  "RGMII_TXD0",
++			  "RGMII_TXD1",
++			  "RGMII_TXD2",
++			  "RGMII_TXD3";
++};
++
+ &pwm1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;

arm64-pine64-pinephone.patch

@@ -0,0 +1,568 @@
+From 836821a0addbd8589e949801aaa7be244703c7f8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Thu, 27 Feb 2020 02:26:48 +0100
+Subject: [PATCH 1/3] arm64: dts: sun50i-a64: Add i2c2 pins
+
+PinePhone needs I2C2 pins description. Add it, and make it default
+for i2c2, since it's the only possiblilty.
+
+Signed-off-by: Ondrej Jirman <megous@megous.com>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 862b47dc9dc9..107a48f9c5b3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -671,6 +671,11 @@ i2c1_pins: i2c1-pins {
+ 				function = "i2c1";
+ 			};
+ 
++			i2c2_pins: i2c2-pins {
++				pins = "PE14", "PE15";
++				function = "i2c2";
++			};
++
+ 			/omit-if-no-ref/
+ 			lcd_rgb666_pins: lcd-rgb666-pins {
+ 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+@@ -958,12 +963,13 @@ i2c2: i2c@1c2b400 {
+ 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&ccu CLK_BUS_I2C2>;
+ 			resets = <&ccu RST_BUS_I2C2>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pins>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
+ 
+-
+ 		spi0: spi@1c68000 {
+ 			compatible = "allwinner,sun8i-h3-spi";
+ 			reg = <0x01c68000 0x1000>;
+-- 
+2.24.1
+
+From 5c4e2cd9e8b600cc622c10543f69fcd897557eee Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Thu, 27 Feb 2020 02:26:49 +0100
+Subject: [PATCH 2/3] dt-bindings: arm: sunxi: Add PinePhone 1.0 and 1.1
+ bindings
+
+Document board compatible names for Pine64 PinePhone:
+
+- 1.0 - Developer variant
+- 1.1 - Braveheart variant
+
+Signed-off-by: Ondrej Jirman <megous@megous.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ Documentation/devicetree/bindings/arm/sunxi.yaml | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
+index 159060b65c5d..c632252be48b 100644
+--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
++++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
+@@ -636,6 +636,16 @@ properties:
+           - const: pine64,pinebook
+           - const: allwinner,sun50i-a64
+ 
++      - description: Pine64 PinePhone Developer Batch (1.0)
++        items:
++          - const: pine64,pinephone-1.0
++          - const: allwinner,sun50i-a64
++
++      - description: Pine64 PinePhone Braveheart (1.1)
++        items:
++          - const: pine64,pinephone-1.1
++          - const: allwinner,sun50i-a64
++
+       - description: Pine64 PineTab
+         items:
+           - const: pine64,pinetab
+-- 
+2.24.1
+
+From 697f60799172569e8d502a44ad98994f2c48778c Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Thu, 27 Feb 2020 02:26:50 +0100
+Subject: [PATCH 3/3] arm64: dts: allwinner: Add initial support for Pine64
+ PinePhone
+
+At the moment PinePhone comes in two slightly incompatible variants:
+
+- 1.0: Early Developer Batch
+- 1.1: Braveheart Batch
+
+There will be at least one more incompatible variant in the very near
+future, so let's start by sharing the dtsi among multiple variants,
+right away, even though the HW description doesn't yet include the
+different bits.
+
+The differences between 1.0 and 1.1 are: change in pins that control
+the flash LED, differences in modem power status signal routing, and
+maybe some other subtler things, that have not been determined yet.
+
+This is a basic DT that includes only features that are already
+supported by mainline drivers.
+
+Co-developed-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Co-developed-by: Martijn Braam <martijn@brixit.nl>
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+Co-developed-by: Luca Weiss <luca@z3ntu.xyz>
+Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
+Signed-off-by: Bhushan Shah <bshah@kde.org>
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Signed-off-by: Ondrej Jirman <megous@megous.com>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   2 +
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    |  11 +
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    |  11 +
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 379 ++++++++++++++++++
+ 4 files changed, 403 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 6dad63881cd3..e4d3cd0ac5bb 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -9,6 +9,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+new file mode 100644
+index 000000000000..0c42272106af
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -0,0 +1,11 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-a64-pinephone.dtsi"
++
++/ {
++	model = "Pine64 PinePhone Developer Batch (1.0)";
++	compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+new file mode 100644
+index 000000000000..06a775c41664
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -0,0 +1,11 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-a64-pinephone.dtsi"
++
++/ {
++	model = "Pine64 PinePhone Braveheart (1.1)";
++	compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+new file mode 100644
+index 000000000000..cefda145c3c9
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -0,0 +1,379 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz>
++// Copyright (C) 2020 Martijn Braam <martijn@brixit.nl>
++// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
++
++#include "sun50i-a64.dtsi"
++#include "sun50i-a64-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pwm/pwm.h>
++
++/ {
++	aliases {
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue {
++			function = LED_FUNCTION_INDICATOR;
++			color = <LED_COLOR_ID_BLUE>;
++			gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
++		};
++
++		green {
++			function = LED_FUNCTION_INDICATOR;
++			color = <LED_COLOR_ID_GREEN>;
++			gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
++		};
++
++		red {
++			function = LED_FUNCTION_INDICATOR;
++			color = <LED_COLOR_ID_RED>;
++			gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++		};
++	};
++
++	speaker_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
++		sound-name-prefix = "Speaker Amp";
++	};
++
++	vibrator {
++		compatible = "gpio-vibrator";
++		enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
++		vcc-supply = <&reg_dcdc1>;
++	};
++};
++
++&codec {
++	status = "okay";
++};
++
++&codec_analog {
++	cpvdd-supply = <&reg_eldo1>;
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&cpu1 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&cpu2 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&cpu3 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&dai {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&i2c1 {
++	status = "okay";
++
++	/* Magnetometer */
++	lis3mdl@1e {
++		compatible = "st,lis3mdl-magn";
++		reg = <0x1e>;
++		vdd-supply = <&reg_dldo1>;
++		vddio-supply = <&reg_dldo1>;
++	};
++
++	/* Accelerometer/gyroscope */
++	mpu6050@68 {
++		compatible = "invensense,mpu6050";
++		reg = <0x68>;
++		interrupt-parent = <&pio>;
++		interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */
++		vdd-supply = <&reg_dldo1>;
++		vddio-supply = <&reg_dldo1>;
++	};
++};
++
++/* Connected to pogo pins (external spring based pinheader for user addons) */
++&i2c2 {
++	status = "okay";
++};
++
++&lradc {
++	vref-supply = <&reg_aldo3>;
++	status = "okay";
++
++	button-200 {
++		label = "Volume Up";
++		linux,code = <KEY_VOLUMEUP>;
++		channel = <0>;
++		voltage = <200000>;
++	};
++
++	button-400 {
++		label = "Volume Down";
++		linux,code = <KEY_VOLUMEDOWN>;
++		channel = <0>;
++		voltage = <400000>;
++	};
++};
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc0_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_dcdc1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	disable-wp;
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_dcdc1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pb-supply = <&reg_dcdc1>;
++	vcc-pc-supply = <&reg_dcdc1>;
++	vcc-pd-supply = <&reg_dcdc1>;
++	vcc-pe-supply = <&reg_aldo1>;
++	vcc-pf-supply = <&reg_dcdc1>;
++	vcc-pg-supply = <&reg_dldo4>;
++	vcc-ph-supply = <&reg_dcdc1>;
++};
++
++&r_pio {
++	/*
++	 * FIXME: We can't add that supply for now since it would
++	 * create a circular dependency between pinctrl, the regulator
++	 * and the RSB Bus.
++	 *
++	 * vcc-pl-supply = <&reg_aldo2>;
++	 */
++};
++
++&r_rsb {
++	status = "okay";
++
++	axp803: pmic@3a3 {
++		compatible = "x-powers,axp803";
++		reg = <0x3a3>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
++	};
++};
++
++#include "axp803.dtsi"
++
++&ac_power_supply {
++	status = "okay";
++};
++
++&battery_power_supply {
++	status = "okay";
++};
++
++&reg_aldo1 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "dovdd-csi";
++};
++
++&reg_aldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-pl";
++};
++
++&reg_aldo3 {
++	regulator-always-on;
++	regulator-min-microvolt = <2700000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-pll-avcc";
++};
++
++&reg_dcdc1 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-3v3";
++};
++
++&reg_dcdc2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1000000>;
++	regulator-max-microvolt = <1300000>;
++	regulator-name = "vdd-cpux";
++};
++
++/* DCDC3 is polyphased with DCDC2 */
++
++&reg_dcdc5 {
++	regulator-always-on;
++	regulator-min-microvolt = <1200000>;
++	regulator-max-microvolt = <1200000>;
++	regulator-name = "vcc-dram";
++};
++
++&reg_dcdc6 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-sys";
++};
++
++&reg_dldo1 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-dsi-sensor";
++};
++
++&reg_dldo2 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-mipi-io";
++};
++
++&reg_dldo3 {
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "avdd-csi";
++};
++
++&reg_dldo4 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-wifi-io";
++};
++
++&reg_eldo1 {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-lpddr";
++};
++
++&reg_eldo3 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "dvdd-1v8-csi";
++};
++
++&reg_fldo1 {
++	regulator-min-microvolt = <1200000>;
++	regulator-max-microvolt = <1200000>;
++	regulator-name = "vcc-1v2-hsic";
++};
++
++&reg_fldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-cpus";
++};
++
++&reg_ldo_io0 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-lcd-ctp-stk";
++	status = "okay";
++};
++
++&reg_ldo_io1 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-1v8-typec";
++	status = "okay";
++};
++
++&reg_rtc_ldo {
++	regulator-name = "vcc-rtc";
++};
++
++&sound {
++	status = "okay";
++	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
++	simple-audio-card,widgets = "Microphone", "Headset Microphone",
++				    "Microphone", "Internal Microphone",
++				    "Headphone", "Headphone Jack",
++				    "Speaker", "Internal Earpiece",
++				    "Speaker", "Internal Speaker";
++	simple-audio-card,routing =
++			"Headphone Jack", "HP",
++			"Internal Earpiece", "EARPIECE",
++			"Internal Speaker", "Speaker Amp OUTL",
++			"Internal Speaker", "Speaker Amp OUTR",
++			"Speaker Amp INL", "LINEOUT",
++			"Speaker Amp INR", "LINEOUT",
++			"Left DAC", "AIF1 Slot 0 Left",
++			"Right DAC", "AIF1 Slot 0 Right",
++			"AIF1 Slot 0 Left ADC", "Left ADC",
++			"AIF1 Slot 0 Right ADC", "Right ADC",
++			"Internal Microphone", "MBIAS",
++			"MIC1", "Internal Microphone",
++			"Headset Microphone", "HBIAS",
++			"MIC2", "Headset Microphone";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb_pins>;
++	status = "okay";
++};
++
++/* Connected to the modem (hardware flow control can't be used) */
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usb_power_supply {
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++};
+-- 
+2.24.1
+

arm64-pine64-pinetab.patch

@@ -0,0 +1,583 @@
+From e15d9c7cb74033f668c19a65abfd77ed7331f91e Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Thu, 16 Jan 2020 11:36:35 +0800
+Subject: [PATCH 1/2] dt-bindings: arm: sunxi: add binding for PineTab tablet
+
+Add the device tree binding for Pine64's PineTab tablet, which uses
+Allwinner A64 SoC.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
+index 327ce6730823..159060b65c5d 100644
+--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
++++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
+@@ -636,6 +636,11 @@ properties:
+           - const: pine64,pinebook
+           - const: allwinner,sun50i-a64
+ 
++      - description: Pine64 PineTab
++        items:
++          - const: pine64,pinetab
++          - const: allwinner,sun50i-a64
++
+       - description: Pine64 SoPine Baseboard
+         items:
+           - const: pine64,sopine-baseboard
+-- 
+2.24.1
+
+From d7b56d337bb980f0b996958ec6808253c4f50771 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Thu, 16 Jan 2020 11:36:36 +0800
+Subject: [PATCH 2/2] arm64: dts: allwinner: a64: add support for PineTab
+
+PineTab is a 10.1" tablet by Pine64 with Allwinner A64 inside.
+
+It includes the following peripherals:
+
+USB:
+- A microUSB Type-B port connected to the OTG-capable USB PHY of
+Allwinner A64. The ID pin is connected to a GPIO of the A64 SoC, and the
+Vbus is connected to the Vbus of AXP803 PMIC. These enables OTG
+functionality on this port.
+- A USB Type-A port is connected to the internal hub attached to the
+non-OTG USB PHY of Allwinner A64.
+- There are reserved pins for an external keyboard connected to the
+internal hub.
+
+Power:
+- The microUSB port has its Vbus connected to AXP803, mentioned above.
+- A DC jack (of a strange size, 2.5mm outer diameter) is connected to
+the ACIN of AXP803.
+- A Li-Polymer battery is connected to the battery pins of AXP803.
+
+Storage:
+- An tradition Pine64 eMMC slot is on the board, mounted with an eMMC
+module by factory.
+- An external microSD slot is hidden under a protect case.
+
+Display:
+- A MIPI-DSI LCD panel (800x1280) is connected to the DSI port of A64 SoC.
+- A mini HDMI port.
+
+Input:
+- A touch panel attached to a Goodix GT9271 touch controller.
+- Volume keys connected to the LRADC of the A64 SoC.
+
+Camera:
+- An OV5640 CMOS camera is at rear, connected to the CSI bus of A64 SoC.
+- A GC2145 CMOS camera is at front, shares the same CSI bus with OV5640.
+
+Audio:
+- A headphone jack is conencted to the SoC's internal codec.
+- A speaker connected is to the Line Out port of SoC's internal codec, via
+an amplifier.
+
+Misc:
+- Debug UART is muxed with the headphone jack, with the switch next to
+the microSD slot.
+- A bosch BMA223 accelerometer is connected to the I2C bus of A64 SoC.
+- Wi-Fi and Bluetooth are available via a RTL8723CS chip, similar to the
+one in Pinebook.
+
+This commit adds a basically usable device tree for it, implementing
+most of the features mentioned above. HDMI is not supported now because
+bad LCD-HDMI coexistence situation of mainline A64 display driver, the
+front camera currently lacks a driver and a facility to share the bus
+with the rear one, and the accelerometer currently lacks a DT binding.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 460 ++++++++++++++++++
+ 2 files changed, 461 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index cf4f78617c3f..6dad63881cd3 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+new file mode 100644
+index 000000000000..316e8a443913
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -0,0 +1,460 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz>
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64.dtsi"
++#include "sun50i-a64-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pwm/pwm.h>
++
++/ {
++	model = "PineTab";
++	compatible = "pine64,pinetab", "allwinner,sun50i-a64";
++
++	aliases {
++		serial0 = &uart0;
++		ethernet0 = &rtl8723cs;
++	};
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
++		brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>;
++		default-brightness-level = <15>;
++		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
++		power-supply = <&vdd_bl>;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	i2c-csi {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */
++		scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
++		i2c-gpio,delay-us = <5>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		/* Rear camera */
++		ov5640: camera@3c {
++			compatible = "ovti,ov5640";
++			reg = <0x3c>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&csi_mclk_pin>;
++			clocks = <&ccu CLK_CSI_MCLK>;
++			clock-names = "xclk";
++
++			AVDD-supply = <&reg_dldo3>;
++			DOVDD-supply = <&reg_aldo1>;
++			DVDD-supply = <&reg_eldo3>;
++			reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
++			powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
++
++			port {
++				ov5640_ep: endpoint {
++					remote-endpoint = <&csi_ep>;
++					bus-width = <8>;
++					hsync-active = <1>; /* Active high */
++					vsync-active = <0>; /* Active low */
++					data-active = <1>;  /* Active high */
++					pclk-sample = <1>;  /* Rising */
++				};
++			};
++		};
++	};
++
++	speaker_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		sound-name-prefix = "Speaker Amp";
++	};
++
++	vdd_bl: regulator@0 {
++		compatible = "regulator-fixed";
++		regulator-name = "bl-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
++		enable-active-high;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&codec {
++	status = "okay";
++};
++
++&codec_analog {
++	hpvcc-supply = <&reg_eldo1>;
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&cpu1 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&cpu2 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&cpu3 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&csi {
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_ep: endpoint {
++			remote-endpoint = <&ov5640_ep>;
++			bus-width = <8>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <0>; /* Active low */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
++	};
++};
++
++&dai {
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&dphy {
++	status = "okay";
++};
++
++&dsi {
++	vcc-dsi-supply = <&reg_dldo1>;
++	status = "okay";
++
++	panel@0 {
++		compatible = "feixin,k101-im2ba02";
++		reg = <0>;
++		avdd-supply = <&reg_dc1sw>;
++		dvdd-supply = <&reg_dc1sw>;
++		cvdd-supply = <&reg_ldo_io1>;
++		reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
++		backlight = <&backlight>;
++	};
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	touchscreen@5d {
++		compatible = "goodix,gt9271";
++		reg = <0x5d>;
++		interrupt-parent = <&pio>;
++		interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */
++		irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
++		reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
++		AVDD28-supply = <&reg_ldo_io1>;
++	};
++};
++
++&i2c0_pins {
++	bias-pull-up;
++};
++
++&i2c1 {
++	status = "okay";
++
++	/* TODO: add Bochs BMA223 accelerometer here */
++};
++
++&lradc {
++	vref-supply = <&reg_aldo3>;
++	status = "okay";
++
++	button-200 {
++		label = "Volume Up";
++		linux,code = <KEY_VOLUMEUP>;
++		channel = <0>;
++		voltage = <200000>;
++	};
++
++	button-400 {
++		label = "Volume Down";
++		linux,code = <KEY_VOLUMEDOWN>;
++		channel = <0>;
++		voltage = <400000>;
++	};
++};
++
++&mixer1 {
++	status = "okay";
++};
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc0_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_dldo4>;
++	vqmmc-supply = <&reg_eldo1>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	rtl8723cs: wifi@1 {
++		reg = <1>;
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_dcdc1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&pwm {
++	status = "okay";
++};
++
++&r_rsb {
++	status = "okay";
++
++	axp803: pmic@3a3 {
++		compatible = "x-powers,axp803";
++		reg = <0x3a3>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
++		x-powers,drive-vbus-en;
++	};
++};
++
++#include "axp803.dtsi"
++
++&ac_power_supply {
++	status = "okay";
++};
++
++&battery_power_supply {
++	status = "okay";
++};
++
++&reg_aldo1 {
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "dovdd-csi";
++};
++
++&reg_aldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-pl";
++};
++
++&reg_aldo3 {
++	regulator-always-on;
++	regulator-min-microvolt = <2700000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-pll-avcc";
++};
++
++&reg_dc1sw {
++	regulator-name = "vcc-lcd";
++};
++
++&reg_dcdc1 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-3v3";
++};
++
++&reg_dcdc2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1000000>;
++	regulator-max-microvolt = <1300000>;
++	regulator-name = "vdd-cpux";
++};
++
++/* DCDC3 is polyphased with DCDC2 */
++
++&reg_dcdc5 {
++	regulator-always-on;
++	regulator-min-microvolt = <1200000>;
++	regulator-max-microvolt = <1200000>;
++	regulator-name = "vcc-dram";
++};
++
++&reg_dcdc6 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-sys";
++};
++
++&reg_dldo1 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-hdmi-dsi-sensor";
++};
++
++&reg_dldo3 {
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "avdd-csi";
++};
++
++&reg_dldo4 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-wifi";
++};
++
++&reg_drivevbus {
++	regulator-name = "usb0-vbus";
++	status = "okay";
++};
++
++&reg_eldo1 {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "cpvdd";
++};
++
++&reg_eldo2 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcca-1v8";
++};
++
++&reg_eldo3 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "dvdd-1v8-csi";
++};
++
++&reg_fldo1 {
++	regulator-min-microvolt = <1200000>;
++	regulator-max-microvolt = <1200000>;
++	regulator-name = "vcc-1v2-hsic";
++};
++
++&reg_fldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-cpus";
++};
++
++&reg_ldo_io0 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-usb";
++	status = "okay";
++};
++
++&reg_ldo_io1 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-enable-ramp-delay = <3500000>;
++	regulator-name = "vcc-touchscreen";
++	status = "okay";
++};
++
++&reg_rtc_ldo {
++	regulator-name = "vcc-rtc";
++};
++
++&sound {
++	status = "okay";
++	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
++	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
++				    "Microphone", "Internal Microphone Right",
++				    "Headphone", "Headphone Jack",
++				    "Speaker", "Internal Speaker";
++	simple-audio-card,routing =
++			"Left DAC", "AIF1 Slot 0 Left",
++			"Right DAC", "AIF1 Slot 0 Right",
++			"Speaker Amp INL", "LINEOUT",
++			"Speaker Amp INR", "LINEOUT",
++			"Internal Speaker", "Speaker Amp OUTL",
++			"Internal Speaker", "Speaker Amp OUTR",
++			"Headphone Jack", "HP",
++			"AIF1 Slot 0 Left ADC", "Left ADC",
++			"AIF1 Slot 0 Right ADC", "Right ADC",
++			"Internal Microphone Left", "MBIAS",
++			"MIC1", "Internal Microphone Left",
++			"Internal Microphone Right", "HBIAS",
++			"MIC2", "Internal Microphone Right";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usb_power_supply {
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++	usb0_vbus_power-supply = <&usb_power_supply>;
++	usb0_vbus-supply = <&reg_drivevbus>;
++	usb1_vbus-supply = <&reg_ldo_io0>;
++	status = "okay";
++};
+-- 
+2.24.1
+

arm64-pinebook-fixes.patch

@@ -0,0 +1,429 @@
+From e7a6e6b0c6506a9f070dbfb2ca948770c47a1d78 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:30:57 -0600
+Subject: [PATCH 1/8] arm64: dts: allwinner: pinebook: Remove unused vcc3v3
+ regulator
+
+This fixed regulator has no consumers, GPIOs, or other connections.
+Remove it.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 7 -------
+ 1 file changed, 7 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index 3d894b208901..ff32ca1a495e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -63,13 +63,6 @@ lid_switch {
+ 		};
+ 	};
+ 
+-	reg_vcc3v3: vcc3v3 {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc3v3";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-	};
+-
+ 	wifi_pwrseq: wifi_pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+-- 
+2.24.1
+
+From 5eea216437eeff908d6d2942bf893fb77ebfc111 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:30:59 -0600
+Subject: [PATCH 2/8] arm64: dts: allwinner: pinebook: Sort device tree nodes
+
+The r_i2c node should come before r_rsb, and in any case should not
+separate the axp803 node from its subnodes.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ .../boot/dts/allwinner/sun50i-a64-pinebook.dts   | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index ff32ca1a495e..77784f7b1da7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -172,6 +172,14 @@ &pwm {
+ 	status = "okay";
+ };
+ 
++/* The ANX6345 eDP-bridge is on r_i2c */
++&r_i2c {
++	clock-frequency = <100000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&r_i2c_pl89_pins>;
++	status = "okay";
++};
++
+ &r_rsb {
+ 	status = "okay";
+ 
+@@ -183,14 +191,6 @@ axp803: pmic@3a3 {
+ 	};
+ };
+ 
+-/* The ANX6345 eDP-bridge is on r_i2c */
+-&r_i2c {
+-	clock-frequency = <100000>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&r_i2c_pl89_pins>;
+-	status = "okay";
+-};
+-
+ #include "axp803.dtsi"
+ 
+ &ac_power_supply {
+-- 
+2.24.1
+
+From 4bdf53ffc64e5c6738c942dcdc422d5ca8a2070a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:31:00 -0600
+Subject: [PATCH 3/8] arm64: dts: allwinner: pinebook: Make simplefb more
+ consistent
+
+Boards generally reference the simplefb nodes from the SoC dtsi by
+label, not by full path. simplefb_hdmi is already like this in the
+Pinebook DTS. Update simplefb_lcd to match.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ .../arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index 77784f7b1da7..224bed65d008 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -41,12 +41,6 @@ backlight: backlight {
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+-
+-		framebuffer-lcd {
+-			panel-supply = <&reg_dc1sw>;
+-			dvdd25-supply = <&reg_dldo2>;
+-			dvdd12-supply = <&reg_fldo1>;
+-		};
+ 	};
+ 
+ 	gpio_keys {
+@@ -316,6 +310,12 @@ &reg_rtc_ldo {
+ 	regulator-name = "vcc-rtc";
+ };
+ 
++&simplefb_lcd {
++	panel-supply = <&reg_dc1sw>;
++	dvdd25-supply = <&reg_dldo2>;
++	dvdd12-supply = <&reg_fldo1>;
++};
++
+ &simplefb_hdmi {
+ 	vcc-hdmi-supply = <&reg_dldo1>;
+ };
+-- 
+2.24.1
+
+From c0f416de7141bbc713f080ad123b256f6320ec92 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:31:01 -0600
+Subject: [PATCH 4/8] arm64: dts: allwinner: pinebook: Document MMC0 CD pin
+ name
+
+Normally GPIO pin references are followed by a comment giving the pin
+name for searchability. Add the comment here where it was missing.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index 224bed65d008..a1e15777d524 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -119,7 +119,7 @@ &mmc0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc0_pins>;
+ 	vmmc-supply = <&reg_dcdc1>;
+-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ 	disable-wp;
+ 	bus-width = <4>;
+ 	status = "okay";
+-- 
+2.24.1
+
+From 8818d55ec31fa6e0dc14fb7a4924b3e8d3ecef7d Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:31:02 -0600
+Subject: [PATCH 5/8] arm64: dts: allwinner: pinebook: Add GPIO port regulators
+
+Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL.
+
+VCC-PC and VCC-PG are supplied by ELDO1 at 1.8v.
+VCC-PD is supplied by DCDC1 (VCC-IO) at 3.3v.
+VCC-PE is supplied by ALDO1, and is unused.
+
+VCC-PL creates a circular dependency, so it is omitted for now.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ .../boot/dts/allwinner/sun50i-a64-pinebook.dts  | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index a1e15777d524..1ec39120323f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -162,6 +162,13 @@ &ohci1 {
+ 	status = "okay";
+ };
+ 
++&pio {
++	vcc-pc-supply = <&reg_eldo1>;
++	vcc-pd-supply = <&reg_dcdc1>;
++	vcc-pe-supply = <&reg_aldo1>;
++	vcc-pg-supply = <&reg_eldo1>;
++};
++
+ &pwm {
+ 	status = "okay";
+ };
+@@ -174,6 +181,16 @@ &r_i2c {
+ 	status = "okay";
+ };
+ 
++&r_pio {
++	/*
++	 * FIXME: We can't add that supply for now since it would
++	 * create a circular dependency between pinctrl, the regulator
++	 * and the RSB Bus.
++	 *
++	 * vcc-pl-supply = <&reg_aldo2>;
++	 */
++};
++
+ &r_rsb {
+ 	status = "okay";
+ 
+-- 
+2.24.1
+
+From bd863f25d41173e140850772f9a02ffb3b3e0d6b Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:31:03 -0600
+Subject: [PATCH 6/8] arm64: dts: allwinner: pinebook: Fix backlight regulator
+
+The output from the backlight regulator is labeled as "VBKLT" in the
+schematic. Using the equation and resistor values from the schematic,
+the output is approximately 18V, not 3.3V. Since the regulator in use
+(SS6640STR) is a boost regulator powered by PS (battery or AC input),
+which are both >3.3V, the output could not be 3.3V anyway.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ .../dts/allwinner/sun50i-a64-pinebook.dts     | 20 +++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index 1ec39120323f..313f4e6edc19 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -21,22 +21,13 @@ aliases {
+ 		ethernet0 = &rtl8723cs;
+ 	};
+ 
+-	vdd_bl: regulator@0 {
+-		compatible = "regulator-fixed";
+-		regulator-name = "bl-3v3";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+-		enable-active-high;
+-	};
+-
+ 	backlight: backlight {
+ 		compatible = "pwm-backlight";
+ 		pwms = <&pwm 0 50000 0>;
+ 		brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+ 		default-brightness-level = <2>;
+ 		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+-		power-supply = <&vdd_bl>;
++		power-supply = <&reg_vbklt>;
+ 	};
+ 
+ 	chosen {
+@@ -57,6 +48,15 @@ lid_switch {
+ 		};
+ 	};
+ 
++	reg_vbklt: vbklt {
++		compatible = "regulator-fixed";
++		regulator-name = "vbklt";
++		regulator-min-microvolt = <18000000>;
++		regulator-max-microvolt = <18000000>;
++		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
++		enable-active-high;
++	};
++
+ 	wifi_pwrseq: wifi_pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+-- 
+2.24.1
+
+From 425472eb612873c9c64b41df70020de58448bef3 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:31:04 -0600
+Subject: [PATCH 7/8] arm64: dts: allwinner: pinebook: Fix 5v0 boost regulator
+
+Now that AXP803 GPIO support is available, we can properly model
+the hardware. Replace the use of GPIO0-LDO with a fixed regulator
+controlled by GPIO0. This boost regulator is used to power the
+(internal and external) USB ports, as well as the speakers.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ .../dts/allwinner/sun50i-a64-pinebook.dts     | 27 +++++++++----------
+ 1 file changed, 12 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index 313f4e6edc19..c06c540e6c08 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -57,6 +57,15 @@ reg_vbklt: vbklt {
+ 		enable-active-high;
+ 	};
+ 
++	reg_vcc5v0: vcc5v0 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++
+ 	wifi_pwrseq: wifi_pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+@@ -64,12 +73,7 @@ wifi_pwrseq: wifi_pwrseq {
+ 
+ 	speaker_amp: audio-amplifier {
+ 		compatible = "simple-audio-amplifier";
+-		/*
+-		 * TODO This is actually a fixed regulator controlled by
+-		 * the GPIO line on the PMIC. This should be corrected
+-		 * once GPIO support is added for this PMIC.
+-		 */
+-		VCC-supply = <&reg_ldo_io0>;
++		VCC-supply = <&reg_vcc5v0>;
+ 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ 		sound-name-prefix = "Speaker Amp";
+ 	};
+@@ -316,13 +320,6 @@ &reg_fldo2 {
+ 	regulator-name = "vdd-cpus";
+ };
+ 
+-&reg_ldo_io0 {
+-	regulator-min-microvolt = <3300000>;
+-	regulator-max-microvolt = <3300000>;
+-	regulator-name = "vcc-usb";
+-	status = "okay";
+-};
+-
+ &reg_rtc_ldo {
+ 	regulator-name = "vcc-rtc";
+ };
+@@ -371,7 +368,7 @@ &usb_otg {
+ };
+ 
+ &usbphy {
+-	usb0_vbus-supply = <&reg_ldo_io0>;
+-	usb1_vbus-supply = <&reg_ldo_io0>;
++	usb0_vbus-supply = <&reg_vcc5v0>;
++	usb1_vbus-supply = <&reg_vcc5v0>;
+ 	status = "okay";
+ };
+-- 
+2.24.1
+
+From c3aea4ea2117f5dc28da3d4175fc93296653ecd5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jan 2020 10:30:58 -0600
+Subject: [PATCH 8/8] arm64: dts: allwinner: pinebook: Remove unused AXP803
+ regulators
+
+The Pinebook does not use the CSI bus on the A64. In fact it does not
+use GPIO port E for anything at all. Thus the following regulators are
+not used and do not need voltages set:
+
+ - ALDO1: Connected to VCC-PE only
+ - DLDO3: Not connected
+ - ELDO3: Not connected
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ .../boot/dts/allwinner/sun50i-a64-pinebook.dts   | 16 +---------------
+ 1 file changed, 1 insertion(+), 15 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index c06c540e6c08..12e513ba8f50 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -217,9 +217,7 @@ &battery_power_supply {
+ };
+ 
+ &reg_aldo1 {
+-	regulator-min-microvolt = <2800000>;
+-	regulator-max-microvolt = <2800000>;
+-	regulator-name = "vcc-csi";
++	regulator-name = "vcc-pe";
+ };
+ 
+ &reg_aldo2 {
+@@ -282,12 +280,6 @@ &reg_dldo2 {
+ 	regulator-name = "vcc-edp";
+ };
+ 
+-&reg_dldo3 {
+-	regulator-min-microvolt = <3300000>;
+-	regulator-max-microvolt = <3300000>;
+-	regulator-name = "avdd-csi";
+-};
+-
+ &reg_dldo4 {
+ 	regulator-min-microvolt = <3300000>;
+ 	regulator-max-microvolt = <3300000>;
+@@ -301,12 +293,6 @@ &reg_eldo1 {
+ 	regulator-name = "cpvdd";
+ };
+ 
+-&reg_eldo3 {
+-	regulator-min-microvolt = <1800000>;
+-	regulator-max-microvolt = <1800000>;
+-	regulator-name = "vdd-1v8-csi";
+-};
+-
+ &reg_fldo1 {
+ 	regulator-min-microvolt = <1200000>;
+ 	regulator-max-microvolt = <1200000>;
+-- 
+2.24.1
+

arm64-rock960-add-onboard-wifi-bt.patch

@@ -1,163 +0,0 @@
-From c72235c288c8cc55d33e257e05d3017c2daf1603 Mon Sep 17 00:00:00 2001
-From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-Date: Fri, 15 Feb 2019 10:26:48 +0530
-Subject: arm64: dts: rockchip: Add on-board WiFi/BT support for Rock960 boards
-
-Add on-board WiFi/BT support for Rock960 boards such as Rock960 based
-on AP6356S and Ficus based on AP6354 wireless modules.
-
-Firmwares for the respective boards are available here:
-
-http://people.linaro.org/~manivannan.sadhasivam/rock960_wifi/
-http://people.linaro.org/~manivannan.sadhasivam/ficus_wifi/
-
-Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 95 +++++++++++++++++++++++-
- 1 file changed, 94 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-index fecb133b0ed2..e40e66e33a5e 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-@@ -9,6 +9,15 @@
- #include "rk3399-opp.dtsi"
- 
- / {
-+	sdio_pwrseq: sdio-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk808 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_enable_h>;
-+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
-+	};
-+
- 	vcc1v8_s0: vcc1v8-s0 {
- 		compatible = "regulator-fixed";
- 		regulator-name = "vcc1v8_s0";
-@@ -370,6 +379,20 @@
- };
- 
- &pinctrl {
-+	bt {
-+		bt_enable_h: bt-enable-h {
-+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_host_wake_l: bt-host-wake-l {
-+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_wake_l: bt-wake-l {
-+			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
- 	sdmmc {
- 		sdmmc_bus1: sdmmc-bus1 {
- 			rockchip,pins =
-@@ -395,6 +418,26 @@
- 		};
- 	};
- 
-+	sdio0 {
-+		sdio0_bus4: sdio0-bus4 {
-+			rockchip,pins =
-+				<2 20 RK_FUNC_1 &pcfg_pull_up_20ma>,
-+				<2 21 RK_FUNC_1 &pcfg_pull_up_20ma>,
-+				<2 22 RK_FUNC_1 &pcfg_pull_up_20ma>,
-+				<2 23 RK_FUNC_1 &pcfg_pull_up_20ma>;
-+		};
-+
-+		sdio0_cmd: sdio0-cmd {
-+			rockchip,pins =
-+				<2 24 RK_FUNC_1 &pcfg_pull_up_20ma>;
-+		};
-+
-+		sdio0_clk: sdio0-clk {
-+			rockchip,pins =
-+				<2 25 RK_FUNC_1 &pcfg_pull_none_20ma>;
-+		};
-+	};
-+
- 	pmic {
- 		pmic_int_l: pmic-int-l {
- 			rockchip,pins =
-@@ -411,6 +454,19 @@
- 				<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
- 		};
- 	};
-+
-+	sdio-pwrseq {
-+		wifi_enable_h: wifi-enable-h {
-+			rockchip,pins =
-+				<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	wifi {
-+		wifi_host_wake_l: wifi-host-wake-l {
-+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
- };
- 
- &pwm2 {
-@@ -421,6 +477,32 @@
- 	status = "okay";
- };
- 
-+&sdio0 {
-+	bus-width = <4>;
-+	clock-frequency = <50000000>;
-+	cap-sdio-irq;
-+	cap-sd-highspeed;
-+	keep-power-in-suspend;
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
-+	sd-uhs-sdr104;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+
-+	brcmf: wifi@1 {
-+		compatible = "brcm,bcm4329-fmac";
-+		reg = <1>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
-+		interrupt-names = "host-wake";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_host_wake_l>;
-+	};
-+};
-+
- &sdhci {
- 	bus-width = <8>;
- 	mmc-hs400-1_8v;
-@@ -447,8 +529,19 @@
- 
- &uart0 {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&uart0_xfer &uart0_cts>;
-+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- 	status = "okay";
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		clocks = <&rk808 1>;
-+		clock-names = "ext_clock";
-+		device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
-+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
-+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-+	};
- };
- 
- &uart2 {
--- 
-cgit 1.2-0.3.lf.el7

arm64-rock960-enable-hdmi-audio.patch

@@ -1,43 +0,0 @@
-From 803346a8efc9062da732c9d3e0b8e7079096f1ad Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 29 Jan 2019 08:33:24 -0300
-Subject: arm64: dts: rockchip: Enable HDMI audio devices on rk3399-rock960
-
-This commit enable the hdmi-sound and i2s2 devices needed to have
-audio over HDMI on both rock960 and the related ficus board.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-index 56abbb08c133..fecb133b0ed2 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-@@ -94,6 +94,10 @@
- 	status = "okay";
- };
- 
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
- &i2c0 {
- 	clock-frequency = <400000>;
- 	i2c-scl-rising-time-ns = <168>;
-@@ -336,6 +340,10 @@
- 	status = "okay";
- };
- 
-+&i2s2 {
-+        status = "okay";
-+};
-+
- &io_domains {
- 	bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
- 	audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
--- 
-cgit 1.2-0.3.lf.el7

arm64-rock960-enable-tsadc.patch

@@ -1,35 +0,0 @@
-From 02260a619efe574d0f6c2a4420b8b76c6802294e Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Fri, 15 Feb 2019 12:25:39 -0300
-Subject: arm64: dts: rockchip: Enable tsadc device on rock960
-
-Enable the thermal sensor. This device also provides
-temperature shutdown protection. The shutdown value is
-set at 110C, as tested by the vendor.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-index e40e66e33a5e..2927db4dda9d 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-@@ -527,6 +527,13 @@
- 	status = "okay";
- };
- 
-+&tsadc {
-+	rockchip,hw-tshut-mode = <1>;
-+	rockchip,hw-tshut-polarity = <1>;
-+	rockchip,hw-tshut-temp = <110000>;
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
--- 
-cgit 1.2-0.3.lf.el7

arm64-serial-8250_tegra-Create-Tegra-specific-8250-driver.patch

@@ -0,0 +1,396 @@
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+From: Jon Hunter <jonathanh@nvidia.com>
+To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
+ Jiri Slaby <jslaby@suse.com>, Thierry Reding <thierry.reding@gmail.com>
+CC: <linux-serial@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
+ <linux-tegra@vger.kernel.org>, Jeff Brasen <jbrasen@nvidia.com>,
+ Jon Hunter <jonathanh@nvidia.com>
+Subject: [PATCH V3] serial: 8250_tegra: Create Tegra specific 8250 driver
+Date: Wed, 29 Jan 2020 13:28:17 +0000
+Message-ID: <20200129132817.26343-1-jonathanh@nvidia.com>
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+
+From: Jeff Brasen <jbrasen@nvidia.com>
+
+To support booting NVIDIA Tegra platforms with either Device-Tree or
+ACPI, create a Tegra specific 8250 serial driver that supports both
+firmware types. Another benefit from doing this, is that the Tegra
+specific codec in the generic Open Firmware 8250 driver can now be
+removed.
+
+Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+---
+
+Changes since V2:
+- Added missing header for devm_ioremap (reported by kbuild test robot)
+Changes since V1:
+- Added support for COMPILE_TEST
+
+ drivers/tty/serial/8250/8250_of.c    |  28 ----
+ drivers/tty/serial/8250/8250_tegra.c | 198 +++++++++++++++++++++++++++
+ drivers/tty/serial/8250/Kconfig      |   9 ++
+ drivers/tty/serial/8250/Makefile     |   1 +
+ 4 files changed, 208 insertions(+), 28 deletions(-)
+ create mode 100644 drivers/tty/serial/8250/8250_tegra.c
+
+diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
+index 531ad67395e0..5e45cf8dbc6e 100644
+--- a/drivers/tty/serial/8250/8250_of.c
++++ b/drivers/tty/serial/8250/8250_of.c
+@@ -7,7 +7,6 @@
+ #include <linux/console.h>
+ #include <linux/module.h>
+ #include <linux/slab.h>
+-#include <linux/delay.h>
+ #include <linux/serial_core.h>
+ #include <linux/serial_reg.h>
+ #include <linux/of_address.h>
+@@ -26,28 +25,6 @@ struct of_serial_info {
+ 	int line;
+ };
+ 
+-#ifdef CONFIG_ARCH_TEGRA
+-static void tegra_serial_handle_break(struct uart_port *p)
+-{
+-	unsigned int status, tmout = 10000;
+-
+-	do {
+-		status = p->serial_in(p, UART_LSR);
+-		if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
+-			status = p->serial_in(p, UART_RX);
+-		else
+-			break;
+-		if (--tmout == 0)
+-			break;
+-		udelay(1);
+-	} while (1);
+-}
+-#else
+-static inline void tegra_serial_handle_break(struct uart_port *port)
+-{
+-}
+-#endif
+-
+ static int of_8250_rs485_config(struct uart_port *port,
+ 				  struct serial_rs485 *rs485)
+ {
+@@ -211,10 +188,6 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
+ 	port->rs485_config = of_8250_rs485_config;
+ 
+ 	switch (type) {
+-	case PORT_TEGRA:
+-		port->handle_break = tegra_serial_handle_break;
+-		break;
+-
+ 	case PORT_RT2880:
+ 		port->iotype = UPIO_AU;
+ 		break;
+@@ -359,7 +332,6 @@ static const struct of_device_id of_platform_serial_table[] = {
+ 	{ .compatible = "ns16550",  .data = (void *)PORT_16550, },
+ 	{ .compatible = "ns16750",  .data = (void *)PORT_16750, },
+ 	{ .compatible = "ns16850",  .data = (void *)PORT_16850, },
+-	{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
+ 	{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
+ 	{ .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
+ 	{ .compatible = "intel,xscale-uart", .data = (void *)PORT_XSCALE, },
+diff --git a/drivers/tty/serial/8250/8250_tegra.c b/drivers/tty/serial/8250/8250_tegra.c
+new file mode 100644
+index 000000000000..c0ffad1572c6
+--- /dev/null
++++ b/drivers/tty/serial/8250/8250_tegra.c
+@@ -0,0 +1,198 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ *  Serial Port driver for Tegra devices
++ *
++ *  Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
++ */
++
++#include <linux/acpi.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include "8250.h"
++
++struct tegra_uart {
++	struct clk *clk;
++	struct reset_control *rst;
++	int line;
++};
++
++static void tegra_uart_handle_break(struct uart_port *p)
++{
++	unsigned int status, tmout = 10000;
++
++	do {
++		status = p->serial_in(p, UART_LSR);
++		if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
++			status = p->serial_in(p, UART_RX);
++		else
++			break;
++		if (--tmout == 0)
++			break;
++		udelay(1);
++	} while (1);
++}
++
++static int tegra_uart_probe(struct platform_device *pdev)
++{
++	struct uart_8250_port port8250;
++	struct tegra_uart *uart;
++	struct uart_port *port;
++	struct resource *res;
++	int ret;
++
++	uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL);
++	if (!uart)
++		return -ENOMEM;
++
++	memset(&port8250, 0, sizeof(port8250));
++
++	port = &port8250.port;
++	spin_lock_init(&port->lock);
++
++	port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
++		      UPF_FIXED_TYPE;
++	port->iotype = UPIO_MEM32;
++	port->regshift = 2;
++	port->type = PORT_TEGRA;
++	port->irqflags |= IRQF_SHARED;
++	port->dev = &pdev->dev;
++	port->handle_break = tegra_uart_handle_break;
++
++	ret = of_alias_get_id(pdev->dev.of_node, "serial");
++	if (ret >= 0)
++		port->line = ret;
++
++	ret = platform_get_irq(pdev, 0);
++	if (ret < 0)
++		return ret;
++
++	port->irq = ret;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -ENODEV;
++
++	port->membase = devm_ioremap(&pdev->dev, res->start,
++				     resource_size(res));
++	if (!port->membase)
++		return -ENOMEM;
++
++	port->mapbase = res->start;
++	port->mapsize = resource_size(res);
++
++	uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
++	if (IS_ERR(uart->rst))
++		return PTR_ERR(uart->rst);
++
++	if (device_property_read_u32(&pdev->dev, "clock-frequency",
++				     &port->uartclk)) {
++		uart->clk = devm_clk_get(&pdev->dev, NULL);
++		if (IS_ERR(uart->clk)) {
++			dev_err(&pdev->dev, "failed to get clock!\n");
++			return -ENODEV;
++		}
++
++		ret = clk_prepare_enable(uart->clk);
++		if (ret < 0)
++			return ret;
++
++		port->uartclk = clk_get_rate(uart->clk);
++	}
++
++	ret = reset_control_deassert(uart->rst);
++	if (ret)
++		goto err_clkdisable;
++
++	ret = serial8250_register_8250_port(&port8250);
++	if (ret < 0)
++		goto err_clkdisable;
++
++	platform_set_drvdata(pdev, uart);
++	uart->line = ret;
++
++	return 0;
++
++err_clkdisable:
++	clk_disable_unprepare(uart->clk);
++
++	return ret;
++}
++
++static int tegra_uart_remove(struct platform_device *pdev)
++{
++	struct tegra_uart *uart = platform_get_drvdata(pdev);
++
++	serial8250_unregister_port(uart->line);
++	reset_control_assert(uart->rst);
++	clk_disable_unprepare(uart->clk);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int tegra_uart_suspend(struct device *dev)
++{
++	struct tegra_uart *uart = dev_get_drvdata(dev);
++	struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
++	struct uart_port *port = &port8250->port;
++
++	serial8250_suspend_port(uart->line);
++
++	if (!uart_console(port) || console_suspend_enabled)
++		clk_disable_unprepare(uart->clk);
++
++	return 0;
++}
++
++static int tegra_uart_resume(struct device *dev)
++{
++	struct tegra_uart *uart = dev_get_drvdata(dev);
++	struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
++	struct uart_port *port = &port8250->port;
++
++	if (!uart_console(port) || console_suspend_enabled)
++		clk_prepare_enable(uart->clk);
++
++	serial8250_resume_port(uart->line);
++
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(tegra_uart_pm_ops, tegra_uart_suspend,
++			 tegra_uart_resume);
++
++static const struct of_device_id tegra_uart_of_match[] = {
++	{ .compatible = "nvidia,tegra20-uart", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
++
++static const struct acpi_device_id tegra_uart_acpi_match[] = {
++	{ "NVDA0100", 0 },
++	{ },
++};
++MODULE_DEVICE_TABLE(acpi, tegra_uart_acpi_match);
++
++static struct platform_driver tegra_uart_driver = {
++	.driver = {
++		.name = "tegra-uart",
++		.pm = &tegra_uart_pm_ops,
++		.of_match_table = tegra_uart_of_match,
++		.acpi_match_table = ACPI_PTR(tegra_uart_acpi_match),
++	},
++	.probe = tegra_uart_probe,
++	.remove = tegra_uart_remove,
++};
++
++module_platform_driver(tegra_uart_driver);
++
++MODULE_AUTHOR("Jeff Brasen <jbrasen@nvidia.com>");
++MODULE_DESCRIPTION("NVIDIA Tegra 8250 Driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
+index f16824bbb573..af0688156dd0 100644
+--- a/drivers/tty/serial/8250/Kconfig
++++ b/drivers/tty/serial/8250/Kconfig
+@@ -500,6 +500,15 @@ config SERIAL_8250_PXA
+ 	  applicable to both devicetree and legacy boards, and early console is
+ 	  part of its support.
+ 
++config SERIAL_8250_TEGRA
++	tristate "8250 support for Tegra serial ports"
++	default SERIAL_8250
++	depends on SERIAL_8250
++	depends on ARCH_TEGRA || COMPILE_TEST
++	help
++	  Select this option if you have machine with an NVIDIA Tegra SoC and
++	  wish to enable 8250 serial driver for the Tegra serial interfaces.
++
+ config SERIAL_OF_PLATFORM
+ 	tristate "Devicetree based probing for 8250 ports"
+ 	depends on SERIAL_8250 && OF
+diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile
+index 51a6079d3f1f..a8bfb654d490 100644
+--- a/drivers/tty/serial/8250/Makefile
++++ b/drivers/tty/serial/8250/Makefile
+@@ -37,6 +37,7 @@ obj-$(CONFIG_SERIAL_8250_INGENIC)	+= 8250_ingenic.o
+ obj-$(CONFIG_SERIAL_8250_LPSS)		+= 8250_lpss.o
+ obj-$(CONFIG_SERIAL_8250_MID)		+= 8250_mid.o
+ obj-$(CONFIG_SERIAL_8250_PXA)		+= 8250_pxa.o
++obj-$(CONFIG_SERIAL_8250_TEGRA)		+= 8250_tegra.o
+ obj-$(CONFIG_SERIAL_OF_PLATFORM)	+= 8250_of.o
+ 
+ CFLAGS_8250_ingenic.o += -I$(srctree)/scripts/dtc/libfdt

ath9k-rx-dma-stop-check.patch

@@ -1,38 +0,0 @@
-From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org>
-Date: Wed, 6 Feb 2013 09:57:47 -0500
-Subject: [PATCH] ath9k: rx dma stop check
-
----
- drivers/net/wireless/ath/ath9k/mac.c | 12 +++++++++++-
- 1 file changed, 11 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
-index bba85d1a6cd1..ebbee8f17130 100644
---- a/drivers/net/wireless/ath/ath9k/mac.c
-+++ b/drivers/net/wireless/ath/ath9k/mac.c
-@@ -693,7 +693,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
- {
- #define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
- 	struct ath_common *common = ath9k_hw_common(ah);
--	u32 mac_status, last_mac_status = 0;
-+	u32 mac_status = 0, last_mac_status = 0;
- 	int i;
- 
- 	/* Enable access to the DMA observation bus */
-@@ -723,6 +723,16 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
- 	}
- 
- 	if (i == 0) {
-+		if (!AR_SREV_9300_20_OR_LATER(ah) &&
-+		    (mac_status & 0x700) == 0) {
-+			/*
-+			 * DMA is idle but the MAC is still stuck
-+			 * processing events
-+			 */
-+			*reset = true;
-+			return true;
-+		}
-+
- 		ath_err(common,
- 			"DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
- 			AH_RX_STOP_DMA_TIMEOUT / 1000,

backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch

@@ -0,0 +1,186 @@
+From patchwork Mon Feb 24 14:07:48 2020
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+ id <B5e53d8cd0006>; Mon, 24 Feb 2020 06:08:15 -0800
+From: Jon Hunter <jonathanh@nvidia.com>
+To: Milo Kim <milo.kim@ti.com>, Lee Jones <lee.jones@linaro.org>,
+ Daniel Thompson <daniel.thompson@linaro.org>,
+ Jingoo Han <jingoohan1@gmail.com>
+CC: <dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
+ <linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com>
+Subject: [PATCH] backlight: lp855x: Ensure regulators are disabled on probe
+ failure
+Date: Mon, 24 Feb 2020 14:07:48 +0000
+Message-ID: <20200224140748.2182-1-jonathanh@nvidia.com>
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+ YrCJM3gob7XIi7l0cbONUTfyGssXmyEi+0SUamN4DDOnXIFxHBentnbyQdvOQ9+11P
+ Dr5X+zeRff1B/SMt2pdNwrja2cVOPDRGAM+U4epkb2bICZZUiGv1fQLKa+KgJ7xMMS
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+
+If probing the LP885x backlight fails after the regulators have been
+enabled, then the following warning is seen when releasing the
+regulators ...
+
+ WARNING: CPU: 1 PID: 289 at drivers/regulator/core.c:2051 _regulator_put.part.28+0x158/0x160
+ Modules linked in: tegra_xudc lp855x_bl(+) host1x pwm_tegra ip_tables x_tables ipv6 nf_defrag_ipv6
+ CPU: 1 PID: 289 Comm: systemd-udevd Not tainted 5.6.0-rc2-next-20200224 #1
+ Hardware name: NVIDIA Jetson TX1 Developer Kit (DT)
+
+ ...
+
+ Call trace:
+  _regulator_put.part.28+0x158/0x160
+  regulator_put+0x34/0x50
+  devm_regulator_release+0x10/0x18
+  release_nodes+0x12c/0x230
+  devres_release_all+0x34/0x50
+  really_probe+0x1c0/0x370
+  driver_probe_device+0x58/0x100
+  device_driver_attach+0x6c/0x78
+  __driver_attach+0xb0/0xf0
+  bus_for_each_dev+0x68/0xc8
+  driver_attach+0x20/0x28
+  bus_add_driver+0x160/0x1f0
+  driver_register+0x60/0x110
+  i2c_register_driver+0x40/0x80
+  lp855x_driver_init+0x20/0x1000 [lp855x_bl]
+  do_one_initcall+0x58/0x1a0
+  do_init_module+0x54/0x1d0
+  load_module+0x1d80/0x21c8
+  __do_sys_finit_module+0xe8/0x100
+  __arm64_sys_finit_module+0x18/0x20
+  el0_svc_common.constprop.3+0xb0/0x168
+  do_el0_svc+0x20/0x98
+  el0_sync_handler+0xf4/0x1b0
+  el0_sync+0x140/0x180
+
+Fix this by ensuring that the regulators are disabled, if enabled, on
+probe failure.
+
+Finally, ensure that the vddio regulator is disabled in the driver
+remove handler.
+
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
+---
+ drivers/video/backlight/lp855x_bl.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/video/backlight/lp855x_bl.c b/drivers/video/backlight/lp855x_bl.c
+index f68920131a4a..e94932c69f54 100644
+--- a/drivers/video/backlight/lp855x_bl.c
++++ b/drivers/video/backlight/lp855x_bl.c
+@@ -456,7 +456,7 @@ static int lp855x_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+ 		ret = regulator_enable(lp->enable);
+ 		if (ret < 0) {
+ 			dev_err(lp->dev, "failed to enable vddio: %d\n", ret);
+-			return ret;
++			goto disable_supply;
+ 		}
+ 
+ 		/*
+@@ -471,24 +471,34 @@ static int lp855x_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+ 	ret = lp855x_configure(lp);
+ 	if (ret) {
+ 		dev_err(lp->dev, "device config err: %d", ret);
+-		return ret;
++		goto disable_vddio;
+ 	}
+ 
+ 	ret = lp855x_backlight_register(lp);
+ 	if (ret) {
+ 		dev_err(lp->dev,
+ 			"failed to register backlight. err: %d\n", ret);
+-		return ret;
++		goto disable_vddio;
+ 	}
+ 
+ 	ret = sysfs_create_group(&lp->dev->kobj, &lp855x_attr_group);
+ 	if (ret) {
+ 		dev_err(lp->dev, "failed to register sysfs. err: %d\n", ret);
+-		return ret;
++		goto disable_vddio;
+ 	}
+ 
+ 	backlight_update_status(lp->bl);
++
+ 	return 0;
++
++disable_vddio:
++	if (lp->enable)
++		regulator_disable(lp->enable);
++disable_supply:
++	if (lp->supply)
++		regulator_disable(lp->supply);
++
++	return ret;
+ }
+ 
+ static int lp855x_remove(struct i2c_client *cl)
+@@ -497,6 +507,8 @@ static int lp855x_remove(struct i2c_client *cl)
+ 
+ 	lp->bl->props.brightness = 0;
+ 	backlight_update_status(lp->bl);
++	if (lp->enable)
++		regulator_disable(lp->enable);
+ 	if (lp->supply)
+ 		regulator_disable(lp->supply);
+ 	sysfs_remove_group(&lp->dev->kobj, &lp855x_attr_group);

bcm2835-cpufreq-add-CPU-frequency-control-driver.patch

@@ -1,399 +0,0 @@
-From fbdb31e061b67941342fc5afa714488f75174632 Mon Sep 17 00:00:00 2001
-From: Peter Robinson <pbrobinson@gmail.com>
-Date: Thu, 31 May 2018 19:08:12 +0100
-Subject: [PATCH 1/3] bcm2835: cpufreq: add CPU frequency control driver
-
-Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
----
- arch/arm/boot/dts/bcm2835-rpi.dtsi |   7 ++
- arch/arm/boot/dts/bcm2837.dtsi     |  33 +++++++
- drivers/clk/bcm/Kconfig            |   8 ++
- drivers/clk/bcm/Makefile           |   1 +
- drivers/clk/bcm/clk-raspberrypi.c  | 138 +++++++++++++++++++++++++++++
- 5 files changed, 187 insertions(+)
- create mode 100644 drivers/clk/bcm/clk-raspberrypi.c
-
-diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
-index 29f970f864dc..6d0f43957af4 100644
---- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
-+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
-@@ -35,6 +35,13 @@
- 			reg = <0x7e00b840 0x3c>;
- 			interrupts = <0 2>;
- 		};
-+
-+		arm_clk: arm_clk {
-+			compatible = "raspberrypi,bcm2835-cpu";
-+			clocks = <&clocks BCM2835_CLOCK_VPU>;
-+			#clock-cells = <0>;
-+			clock-output-names = "arm";
-+		};
- 	};
- };
- 
-diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
-index beb6c502dadc..9cfc553a3633 100644
---- a/arch/arm/boot/dts/bcm2837.dtsi
-+++ b/arch/arm/boot/dts/bcm2837.dtsi
-@@ -44,6 +44,9 @@
- 			reg = <0>;
- 			enable-method = "spin-table";
- 			cpu-release-addr = <0x0 0x000000d8>;
-+			clocks = <&arm_clk>;
-+			clock-names = "cpu";
-+			operating-points-v2 = <&cpu0_opp_table>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -52,6 +55,9 @@
- 			reg = <1>;
- 			enable-method = "spin-table";
- 			cpu-release-addr = <0x0 0x000000e0>;
-+			clocks = <&arm_clk>;
-+			clock-names = "cpu";
-+			operating-points-v2 = <&cpu0_opp_table>;
- 		};
- 
- 		cpu2: cpu@2 {
-@@ -60,6 +66,9 @@
- 			reg = <2>;
- 			enable-method = "spin-table";
- 			cpu-release-addr = <0x0 0x000000e8>;
-+			clocks = <&arm_clk>;
-+			clock-names = "cpu";
-+			operating-points-v2 = <&cpu0_opp_table>;
- 		};
- 
- 		cpu3: cpu@3 {
-@@ -68,6 +77,30 @@
- 			reg = <3>;
- 			enable-method = "spin-table";
- 			cpu-release-addr = <0x0 0x000000f0>;
-+			clocks = <&arm_clk>;
-+			clock-names = "cpu";
-+			operating-points-v2 = <&cpu0_opp_table>;
-+		};
-+	};
-+
-+	cpu0_opp_table: opp_table0 {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp@600000000 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			clock-latency-ns = <355000>;
-+			opp-suspend;
-+		};
-+
-+		opp@900000000 {
-+			opp-hz = /bits/ 64 <900000000>;
-+			clock-latency-ns = <355000>;
-+		};
-+
-+		opp@1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			clock-latency-ns = <355000>;
- 		};
- 	};
- };
-diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
-index 4c4bd85f707c..e40bd19da22b 100644
---- a/drivers/clk/bcm/Kconfig
-+++ b/drivers/clk/bcm/Kconfig
-@@ -63,3 +63,11 @@ config CLK_BCM_SR
- 	default ARCH_BCM_IPROC
- 	help
- 	  Enable common clock framework support for the Broadcom Stingray SoC
-+
-+config CLK_RASPBERRYPI_CPU
-+	bool "Raspberry Pi CPU clock driver"
-+	depends on ARCH_BCM2835 || (COMPILE_TEST && OF)
-+	depends on RASPBERRYPI_FIRMWARE=y
-+	help
-+	  This enables support for the RPi CPU clock which can be adjusted
-+	  via the RPi firmware.
-diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
-index 002661d39128..a028b0a90b6e 100644
---- a/drivers/clk/bcm/Makefile
-+++ b/drivers/clk/bcm/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK_IPROC)	+= clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-a
- obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
- obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835-aux.o
- obj-$(CONFIG_ARCH_BCM_53573)	+= clk-bcm53573-ilp.o
-+obj-$(CONFIG_CLK_RASPBERRYPI_CPU)	+= clk-raspberrypi.o
- obj-$(CONFIG_CLK_BCM_CYGNUS)	+= clk-cygnus.o
- obj-$(CONFIG_CLK_BCM_HR2)	+= clk-hr2.o
- obj-$(CONFIG_CLK_BCM_NSP)	+= clk-nsp.o
-diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
-new file mode 100644
-index 000000000000..046efc822a59
---- /dev/null
-+++ b/drivers/clk/bcm/clk-raspberrypi.c
-@@ -0,0 +1,138 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Raspberry Pi CPU clock driver
-+ *
-+ * Copyright (C) 2018 Stefan Wahren <stefan.wahren@i2se.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/device.h>
-+#include <linux/err.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+#define VCMSG_ID_ARM_CLOCK 0x000000003	/* Clock/Voltage ID's */
-+
-+struct rpi_cpu_clkgen {
-+	struct clk_hw hw;
-+	struct rpi_firmware *fw;
-+};
-+
-+/* tag part of the message */
-+struct prop {
-+       u32 id;			/* the ID of the clock/voltage to get or set */
-+       u32 val;			/* the value (e.g. rate (in Hz)) to set */
-+} __packed;
-+
-+static int rpi_cpu_clock_property(struct rpi_firmware *fw, u32 tag, u32 *val)
-+{
-+	int ret;
-+	struct prop msg = {
-+		.id = VCMSG_ID_ARM_CLOCK,
-+		.val = *val,
-+	};
-+
-+	ret = rpi_firmware_property(fw, tag, &msg, sizeof(msg));
-+	if (ret)
-+		return ret;
-+
-+	*val = msg.val;
-+
-+	return 0;
-+}
-+
-+static unsigned long rpi_cpu_get_rate(struct clk_hw *hw,
-+				      unsigned long parent_rate)
-+{
-+	struct rpi_cpu_clkgen *cpu = container_of(hw, struct rpi_cpu_clkgen, hw);
-+	u32 rate = 0;
-+
-+	rpi_cpu_clock_property(cpu->fw, RPI_FIRMWARE_GET_CLOCK_RATE, &rate);
-+
-+	return rate;
-+}
-+
-+static long rpi_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
-+				     unsigned long *parent_rate)
-+{
-+	return rate;
-+}
-+
-+static int rpi_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
-+			    unsigned long parent_rate)
-+{
-+	struct rpi_cpu_clkgen *cpu = container_of(hw, struct rpi_cpu_clkgen, hw);
-+	u32 new_rate = rate;
-+
-+	return rpi_cpu_clock_property(cpu->fw, RPI_FIRMWARE_SET_CLOCK_RATE,
-+				      &new_rate);
-+}
-+
-+static const struct clk_ops rpi_cpu_ops = {
-+	.recalc_rate = rpi_cpu_get_rate,
-+	.round_rate = rpi_cpu_round_rate,
-+	.set_rate = rpi_cpu_set_rate,
-+};
-+
-+static int rpi_cpu_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct device_node *fw_node;
-+	struct rpi_cpu_clkgen *cpu;
-+	struct clk_init_data *init;
-+	int ret;
-+
-+	cpu = devm_kzalloc(dev, sizeof(*cpu), GFP_KERNEL);
-+	if (!cpu)
-+		return -ENOMEM;
-+
-+	init = devm_kzalloc(dev, sizeof(*init), GFP_KERNEL);
-+	if (!init)
-+		return -ENOMEM;
-+
-+	fw_node = of_find_compatible_node(NULL, NULL,
-+					  "raspberrypi,bcm2835-firmware");
-+	if (!fw_node) {
-+		dev_err(dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+
-+	cpu->fw = rpi_firmware_get(fw_node);
-+	of_node_put(fw_node);
-+	if (!cpu->fw)
-+		return -EPROBE_DEFER;
-+
-+	init->name = dev->of_node->name;
-+	init->ops = &rpi_cpu_ops;
-+
-+	cpu->hw.init = init;
-+	ret = devm_clk_hw_register(dev, &cpu->hw);
-+	if (ret)
-+		return ret;
-+
-+	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
-+				      &cpu->hw);
-+}
-+
-+static const struct of_device_id rpi_cpu_of_match[] = {
-+	{ .compatible = "raspberrypi,bcm2835-cpu", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, rpi_cpu_of_match);
-+
-+static struct platform_driver rpi_cpu_driver = {
-+	.driver = {
-+		.name = "raspberrypi-cpu",
-+		.of_match_table = rpi_cpu_of_match,
-+	},
-+	.probe		= rpi_cpu_probe,
-+};
-+builtin_platform_driver(rpi_cpu_driver);
-+
-+MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
-+MODULE_DESCRIPTION("Raspberry Pi CPU clock driver");
-+MODULE_LICENSE("GPL v2");
--- 
-2.20.1
-
-
-From 0681db63db37cf9015ef9b667c237c3974de04e6 Mon Sep 17 00:00:00 2001
-From: Peter Robinson <pbrobinson@gmail.com>
-Date: Mon, 4 Jun 2018 09:14:10 +0100
-Subject: [PATCH 2/3] add 1.4 ghz OPP for the 3B+
-
-Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
----
- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
-index 42bb09044cc7..3333c080696c 100644
---- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
-+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
-@@ -106,3 +106,10 @@
- 	pinctrl-0 = <&uart1_gpio14>;
- 	status = "okay";
- };
-+
-+&cpu0_opp_table {
-+	opp@1400000000 {
-+		opp-hz = /bits/ 64 <1400000000>;
-+		clock-latency-ns = <355000>;
-+	};
-+};
--- 
-2.20.1
-
-
-From 65f821f03ac635f28c8c79c5e436b398194521f2 Mon Sep 17 00:00:00 2001
-From: Stefan Wahren <stefan.wahren@i2se.com>
-Date: Wed, 26 Sep 2018 21:13:22 +0200
-Subject: [PATCH 3/3] ARM: bcm2837: Use CPU0 as cooling device
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
----
- arch/arm/boot/dts/bcm2837.dtsi | 25 +++++++++++++++++++++++++
- arch/arm/boot/dts/bcm283x.dtsi |  2 +-
- 2 files changed, 26 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
-index 9cfc553a3633..1590d94b618e 100644
---- a/arch/arm/boot/dts/bcm2837.dtsi
-+++ b/arch/arm/boot/dts/bcm2837.dtsi
-@@ -1,4 +1,5 @@
- #include "bcm283x.dtsi"
-+#include <dt-bindings/thermal/thermal.h>
- 
- / {
- 	compatible = "brcm,bcm2837";
-@@ -47,6 +48,7 @@
- 			clocks = <&arm_clk>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu0_opp_table>;
-+			#cooling-cells = <2>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -58,6 +60,7 @@
- 			clocks = <&arm_clk>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu0_opp_table>;
-+			#cooling-cells = <2>;
- 		};
- 
- 		cpu2: cpu@2 {
-@@ -69,6 +72,7 @@
- 			clocks = <&arm_clk>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu0_opp_table>;
-+			#cooling-cells = <2>;
- 		};
- 
- 		cpu3: cpu@3 {
-@@ -80,6 +84,7 @@
- 			clocks = <&arm_clk>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu0_opp_table>;
-+			#cooling-cells = <2>;
- 		};
- 	};
- 
-@@ -117,6 +122,26 @@
- 
- &cpu_thermal {
- 	coefficients = <(-538)	412000>;
-+
-+	trips {
-+		cpu_alert0: cpu-alert0 {
-+			temperature	= <70000>;
-+			hysteresis	= <0>;
-+			type		= "passive";
-+		};
-+	};
-+
-+	cooling-maps {
-+		map0 {
-+			trip = <&cpu_alert0>;
-+			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+		};
-+
-+		map1 {
-+			trip = <&cpu_crit>;
-+			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+		};
-+	};
- };
- 
- /* enable thermal sensor with the correct compatible property set */
-diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
-index 31b29646b14c..2def0684d198 100644
---- a/arch/arm/boot/dts/bcm283x.dtsi
-+++ b/arch/arm/boot/dts/bcm283x.dtsi
-@@ -38,7 +38,7 @@
- 			thermal-sensors = <&thermal>;
- 
- 			trips {
--				cpu-crit {
-+				cpu_crit: cpu-crit {
- 					temperature	= <80000>;
- 					hysteresis	= <0>;
- 					type		= "critical";
--- 
-2.20.1
-

bcm2835-irqchip-Quiesce-IRQs-left-enabled-by-bootloader.patch

@@ -0,0 +1,232 @@
+From patchwork Mon Feb 10 09:52:20 2020
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+X-Patchwork-Id: 11372935
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+From: Lukas Wunner <lukas@wunner.de>
+Date: Mon, 10 Feb 2020 10:52:20 +0100
+Subject: [PATCH v2] irqchip/bcm2835: Quiesce IRQs left enabled by bootloader
+To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>,
+ Marc Zyngier <maz@kernel.org>,
+ "Nicolas Saenz Julienne" <nsaenzjulienne@suse.de>
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+
+Customers of our "Revolution Pi" open source PLCs (which are based on
+the Raspberry Pi) have reported random lockups as well as jittery eMMC,
+UART and SPI latency.  We were able to reproduce the lockups in our lab
+and hooked up a JTAG debugger:
+
+It turns out that the USB controller's interrupt is already enabled when
+the kernel boots.  All interrupts are disabled when the chip comes out
+of power-on reset, according to the spec.  So apparently the bootloader
+enables the interrupt but neglects to disable it before handing over
+control to the kernel.
+
+The bootloader is a closed source blob provided by the Raspberry Pi
+Foundation.  Development of an alternative open source bootloader was
+begun by Kristina Brooks but it's not fully functional yet.  Usage of
+the blob is thus without alternative for the time being.
+
+The Raspberry Pi Foundation's downstream kernel has a performance-
+optimized USB driver (which we use on our Revolution Pi products).
+The driver takes advantage of the FIQ fast interrupt.  Because the
+regular USB interrupt was left enabled by the bootloader, both the
+FIQ and the normal interrupt is enabled once the USB driver probes.
+
+The spec has the following to say on simultaneously enabling the FIQ
+and the normal interrupt of a peripheral:
+
+"One interrupt source can be selected to be connected to the ARM FIQ
+ input.  An interrupt which is selected as FIQ should have its normal
+ interrupt enable bit cleared.  Otherwise a normal and an FIQ interrupt
+ will be fired at the same time.  Not a good idea!"
+                                  ^^^^^^^^^^^^^^^
+https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
+page 110
+
+On a multicore Raspberry Pi, the Foundation's kernel routes all normal
+interrupts to CPU 0 and the FIQ to CPU 1.  Because both the FIQ and the
+normal interrupt is enabled, a USB interrupt causes CPU 0 to spin in
+bcm2836_chained_handle_irq() until the FIQ on CPU 1 has cleared it.
+Interrupts with a lower priority than USB are starved as long.
+
+That explains the jittery eMMC, UART and SPI latency:  On one occasion
+I've seen CPU 0 blocked for no less than 2.9 msec.  Basically,
+everything not USB takes a performance hit:  Whereas eMMC throughput
+on a Compute Module 3 remains relatively constant at 23.5 MB/s with
+this commit, it irregularly dips to 23.0 MB/s without this commit.
+
+The lockups occur when CPU 0 receives a USB interrupt while holding a
+lock which CPU 1 is trying to acquire while the FIQ is temporarily
+disabled on CPU 1.
+
+I've tested old releases of the Foundation's bootloader as far back as
+1.20160202-1 and they all leave the USB interrupt enabled.  Still older
+releases fail to boot a contemporary kernel on a Compute Module 1 or 3,
+which are the only Raspberry Pi variants I have at my disposal for
+testing.
+
+Fix by disabling IRQs left enabled by the bootloader.  Although the
+impact is most pronounced on the Foundation's downstream kernel,
+it seems prudent to apply the fix to the upstream kernel to guard
+against such mistakes in any present and future bootloader.
+
+Signed-off-by: Lukas Wunner <lukas@wunner.de>
+Cc: Serge Schneider <serge@raspberrypi.org>
+Cc: Kristina Brooks <notstina@gmail.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+Changes since v1:
+* Use "relaxed" MMIO accessors to avoid memory barriers (Marc)
+* Use u32 instead of int for register access (Marc)
+* Quiesce FIQ as well (Marc)
+* Quiesce IRQs after mapping them for better readability
+* Drop alternative approach from commit message (Marc)
+
+Link to v1:
+https://lore.kernel.org/lkml/988737dbbc4e499c2faaaa4e567ba3ed8deb9a89.1581089797.git.lukas@wunner.de/
+
+ drivers/irqchip/irq-bcm2835.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c
+index 418245d31921..63539c88ac3a 100644
+--- a/drivers/irqchip/irq-bcm2835.c
++++ b/drivers/irqchip/irq-bcm2835.c
+@@ -61,6 +61,7 @@
+ 					| SHORTCUT1_MASK | SHORTCUT2_MASK)
+ 
+ #define REG_FIQ_CONTROL		0x0c
++#define REG_FIQ_ENABLE		0x80
+ 
+ #define NR_BANKS		3
+ #define IRQS_PER_BANK		32
+@@ -135,6 +136,7 @@ static int __init armctrl_of_init(struct device_node *node,
+ {
+ 	void __iomem *base;
+ 	int irq, b, i;
++	u32 reg;
+ 
+ 	base = of_iomap(node, 0);
+ 	if (!base)
+@@ -157,6 +159,19 @@ static int __init armctrl_of_init(struct device_node *node,
+ 				handle_level_irq);
+ 			irq_set_probe(irq);
+ 		}
++
++		reg = readl_relaxed(intc.enable[b]);
++		if (reg) {
++			writel_relaxed(reg, intc.disable[b]);
++			pr_err(FW_BUG "Bootloader left irq enabled: "
++			       "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg);
++		}
++	}
++
++	reg = readl_relaxed(base + REG_FIQ_CONTROL);
++	if (reg & REG_FIQ_ENABLE) {
++		writel_relaxed(0, base + REG_FIQ_CONTROL);
++		pr_err(FW_BUG "Bootloader left fiq enabled\n");
+ 	}
+ 
+ 	if (is_2836) {

bcm2837-dts-add-Raspberry-Pi-3-A.patch

@@ -1,511 +0,0 @@
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-
-This adds the root properties for the Raspberry Pi 3 A+ .
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Rob Herring <robh@kernel.org>
----
- Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
-index 0dcc3ea..245328f 100644
---- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
-+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
-@@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
- Required root node properties:
- compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
- 
-+Raspberry Pi 3 Model A+
-+Required root node properties:
-+compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
-+
- Raspberry Pi 3 Model B
- Required root node properties:
- compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
-
-From patchwork Tue Dec  4 18:58:18 2018
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-From: Stefan Wahren <stefan.wahren@i2se.com>
-To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
- Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
- Scott Branden <sbranden@broadcom.com>, Eric Anholt <eric@anholt.net>,
- Arnd Bergmann <arnd@arndb.de>
-Subject: [PATCH V3 2/3] ARM: dts: add Raspberry Pi 3 A+
-Date: Tue,  4 Dec 2018 19:58:18 +0100
-Message-Id: <1543949899-13380-3-git-send-email-stefan.wahren@i2se.com>
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-The Raspberry Pi 3 A+ is similar to the Pi 3 B+ but has only 512 MB RAM,
-1 USB 2.0 port and no Ethernet.
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
-Reviewed-by: Eric Anholt <eric@anholt.net>
----
- arch/arm/boot/dts/Makefile                 |   1 +
- arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 107 +++++++++++++++++++++++++++++
- 2 files changed, 108 insertions(+)
- create mode 100644 arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
-
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index b0e966d..15bbd0d 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
- 	bcm2835-rpi-a-plus.dtb \
- 	bcm2835-rpi-cm1-io1.dtb \
- 	bcm2836-rpi-2-b.dtb \
-+	bcm2837-rpi-3-a-plus.dtb \
- 	bcm2837-rpi-3-b.dtb \
- 	bcm2837-rpi-3-b-plus.dtb \
- 	bcm2837-rpi-cm3-io3.dtb \
-diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
-new file mode 100644
-index 0000000..b2df7cf
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
-@@ -0,0 +1,107 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/dts-v1/;
-+#include "bcm2837.dtsi"
-+#include "bcm2836-rpi.dtsi"
-+#include "bcm283x-rpi-usb-host.dtsi"
-+
-+/ {
-+	compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
-+	model = "Raspberry Pi 3 Model A+";
-+
-+	chosen {
-+		/* 8250 auxiliary UART instead of pl011 */
-+		stdout-path = "serial1:115200n8";
-+	};
-+
-+	memory {
-+		reg = <0 0x20000000>;
-+	};
-+
-+	leds {
-+		act {
-+			gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		pwr {
-+			label = "PWR";
-+			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	wifi_pwrseq: wifi-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
-+	};
-+};
-+
-+&firmware {
-+	expgpio: gpio {
-+		compatible = "raspberrypi,firmware-gpio";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		gpio-line-names = "BT_ON",
-+				  "WL_ON",
-+				  "STATUS_LED",
-+				  "",
-+				  "",
-+				  "CAM_GPIO0",
-+				  "CAM_GPIO1",
-+				  "";
-+		status = "okay";
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
-+	status = "okay";
-+};
-+
-+/* SDHCI is used to control the SDIO for wireless */
-+&sdhci {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_gpio34>;
-+	status = "okay";
-+	bus-width = <4>;
-+	non-removable;
-+	mmc-pwrseq = <&wifi_pwrseq>;
-+
-+	brcmf: wifi@1 {
-+		reg = <1>;
-+		compatible = "brcm,bcm4329-fmac";
-+	};
-+};
-+
-+/* SDHOST is used to drive the SD card */
-+&sdhost {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdhost_gpio48>;
-+	status = "okay";
-+	bus-width = <4>;
-+};
-+
-+/* uart0 communicates with the BT module */
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		max-speed = <2000000>;
-+		shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
-+	};
-+};
-+
-+/* uart1 is mapped to the pin header */
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_gpio14>;
-+	status = "okay";
-+};
-
-From patchwork Tue Dec  4 18:58:19 2018
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- id 1MFJfN-1gjyQ33mR7-00FlVP; Tue, 04 Dec 2018 19:58:55 +0100
-From: Stefan Wahren <stefan.wahren@i2se.com>
-To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
- Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
- Scott Branden <sbranden@broadcom.com>, Eric Anholt <eric@anholt.net>,
- Arnd Bergmann <arnd@arndb.de>
-Subject: [PATCH V3 3/3] arm64: dts: broadcom: Add reference to RPi 3 A+
-Date: Tue,  4 Dec 2018 19:58:19 +0100
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-
-This adds a reference to the dts of the Raspberry Pi 3 A+,
-so we don't need to maintain the content in arm64.
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
-Reviewed-by: Eric Anholt <eric@anholt.net>
----
- arch/arm64/boot/dts/broadcom/Makefile                 | 3 ++-
- arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts | 2 ++
- 2 files changed, 4 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts
-
-diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
-index 667ca98..d1d31cc 100644
---- a/arch/arm64/boot/dts/broadcom/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/Makefile
-@@ -1,5 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
--dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb \
-+dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-a-plus.dtb \
-+			      bcm2837-rpi-3-b.dtb \
- 			      bcm2837-rpi-3-b-plus.dtb \
- 			      bcm2837-rpi-cm3-io3.dtb
- 
-diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts
-new file mode 100644
-index 0000000..f0ec56a
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts
-@@ -0,0 +1,2 @@
-+// SPDX-License-Identifier: GPL-2.0
-+#include "arm/bcm2837-rpi-3-a-plus.dts"

configs/build_configs.sh

@@ -19,8 +19,6 @@ cd $SCRIPT_DIR
 set errexit
 set nounset
 
-control_file="config_generation"
-
 cleanup()
 {
 	rm -f config-*
@@ -52,7 +50,9 @@ function merge_configs()
 	arch=$(echo "$archvar" | cut -f1 -d"-")
 	configs=$2
 	order=$3
-	name=$OUTPUT_DIR/$PACKAGE_NAME-$archvar.config
+	flavor=$4
+
+	name=$OUTPUT_DIR/$PACKAGE_NAME-$archvar-$flavor.config
 	echo -n "Building $name ... "
 	touch config-merging config-merged
 
@@ -95,33 +95,55 @@ function merge_configs()
 	echo "done"
 }
 
+function build_flavor()
+{
+	flavor=$1
+	control_file="priority".$flavor
+	while read line
+	do
+		if [ $(echo "$line" | grep -c "^#") -ne 0 ]; then
+			continue
+		elif [ $(echo "$line" | grep -c "^$") -ne 0 ]; then
+			continue
+		elif [ $(echo "$line" | grep -c "^EMPTY") -ne 0 ]; then
+			empty=$(echo "$line" | cut -f2 -d"=")
+			for a in $empty
+			do
+				echo "# EMPTY" > $OUTPUT_DIR/$PACKAGE_NAME-$a-$flavor.config
+
+			done
+		elif [ $(echo "$line" | grep -c "^ORDER") -ne 0 ]; then
+			order=$(echo "$line" | cut -f2 -d"=")
+			for o in $order
+			do
+				glist=$(find $o -type d)
+				for d in $glist
+				do
+					combine_config_layer $d
+				done
+			done
+		else
+			arch=$(echo "$line" | cut -f1 -d"=")
+			configs=$(echo "$line" | cut -f2 -d"=")
+
+			if [ -n "$SUBARCH" ]; then
+				case $arch in
+					$SUBARCH*)
+						;;
+					*)
+						continue
+				esac
+			fi
+
+			merge_configs $arch $configs "$order" $flavor
+		fi
+	done < $control_file
+}
+
 while read line
 do
-	if [ $(echo "$line" | grep -c "^#") -ne 0 ]; then
-		continue
-	elif [ $(echo "$line" | grep -c "^$") -ne 0 ]; then
-		continue
-	elif [ $(echo "$line" | grep -c "^ORDER") -ne 0 ]; then
-		order=$(echo "$line" | cut -f2 -d"=")
-		for o in $order
-		do
-			glist=$(find $o -type d)
-			for d in $glist
-			do
-				combine_config_layer $d
-			done
-		done
-	else
-		arch=$(echo "$line" | cut -f1 -d"=")
-		configs=$(echo "$line" | cut -f2 -d"=")
-
-		if [ -n "$SUBARCH" -a "$SUBARCH" != "$arch" ]; then
-			continue
-		fi
-
-		merge_configs $arch $configs "$order"
-	fi
-done < $control_file
+	build_flavor $line
+done < flavors
 
 # A passed in kernel version implies copy to final location
 # otherwise defer to another script

configs/fedora/debug/CONFIG_DEBUG_BLK_CGROUP

@@ -1 +0,0 @@
-CONFIG_DEBUG_BLK_CGROUP=y

configs/fedora/debug/CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE

@@ -1 +0,0 @@
-CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4096

configs/fedora/debug/CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE

@@ -0,0 +1 @@
+CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000

configs/fedora/debug/CONFIG_DEBUG_MISC

@@ -0,0 +1 @@
+CONFIG_DEBUG_MISC=y

configs/fedora/debug/CONFIG_DEBUG_PAGEALLOC

@@ -1 +0,0 @@
-# CONFIG_DEBUG_PAGEALLOC is not set

configs/fedora/debug/CONFIG_DEBUG_PI_LIST

@@ -1 +0,0 @@
-CONFIG_DEBUG_PI_LIST=y

configs/fedora/debug/CONFIG_DEBUG_VM

@@ -1 +0,0 @@
-CONFIG_DEBUG_VM=y

configs/fedora/debug/CONFIG_DMADEVICES_DEBUG

@@ -1 +1 @@
-CONFIG_DMADEVICES_DEBUG=y
+# CONFIG_DMADEVICES_DEBUG is not set

configs/fedora/debug/CONFIG_LOCK_EVENT_COUNTS

@@ -0,0 +1 @@
+CONFIG_LOCK_EVENT_COUNTS=y

configs/fedora/debug/CONFIG_PM_TEST_SUSPEND

@@ -1 +0,0 @@
-CONFIG_PM_TEST_SUSPEND=y

configs/fedora/debug/CONFIG_REFCOUNT_FULL

@@ -1 +0,0 @@
-CONFIG_REFCOUNT_FULL=y

configs/fedora/debug/CONFIG_TRACE_EVENT_INJECT

@@ -0,0 +1 @@
+CONFIG_TRACE_EVENT_INJECT=y

configs/fedora/debug/arm/CONFIG_CROS_EC_DEBUGFS

@@ -0,0 +1 @@
+CONFIG_CROS_EC_DEBUGFS=m

configs/fedora/debug/x86/CONFIG_CROS_EC_DEBUGFS

@@ -0,0 +1 @@
+CONFIG_CROS_EC_DEBUGFS=m

configs/fedora/debug/x86/x86_64/CONFIG_NR_CPUS

@@ -1 +0,0 @@
-CONFIG_NR_CPUS=8192

configs/fedora/debug/x86/x86_64/README

@@ -0,0 +1,2 @@
+Place config options in this directory that you want applied to x86_64
+debug kernel variant.

configs/fedora/generic/CONFIG_ACPI_HMAT

@@ -0,0 +1 @@
+CONFIG_ACPI_HMAT=y

configs/fedora/generic/CONFIG_AD7091R5

@@ -0,0 +1 @@
+# CONFIG_AD7091R5 is not set

configs/fedora/generic/CONFIG_AD7152

@@ -1 +0,0 @@
-# CONFIG_AD7152 is not set

configs/fedora/generic/CONFIG_AD7292

@@ -0,0 +1 @@
+CONFIG_AD7292=m

configs/fedora/generic/CONFIG_AD7606_IFACE_PARALLEL

@@ -0,0 +1 @@
+# CONFIG_AD7606_IFACE_PARALLEL is not set

configs/fedora/generic/CONFIG_AD7606_IFACE_SPI

@@ -0,0 +1 @@
+# CONFIG_AD7606_IFACE_SPI is not set

configs/fedora/generic/CONFIG_AD7768_1

@@ -0,0 +1 @@
+# CONFIG_AD7768_1 is not set

configs/fedora/generic/CONFIG_ADF4371

@@ -0,0 +1 @@
+# CONFIG_ADF4371 is not set

configs/fedora/generic/CONFIG_ADIN_PHY

@@ -0,0 +1 @@
+CONFIG_ADIN_PHY=m

configs/fedora/generic/CONFIG_ADIS16460

@@ -0,0 +1 @@
+# CONFIG_ADIS16460 is not set

configs/fedora/generic/CONFIG_ADUX1020

@@ -0,0 +1 @@
+CONFIG_ADUX1020=m

configs/fedora/generic/CONFIG_ALLOW_LOCKDOWN_LIFT_BY_SYSRQ

@@ -1 +0,0 @@
-CONFIG_ALLOW_LOCKDOWN_LIFT_BY_SYSRQ=y

configs/fedora/generic/CONFIG_ALTERA_FREEZE_BRIDGE

@@ -0,0 +1 @@
+# CONFIG_ALTERA_FREEZE_BRIDGE is not set

configs/fedora/generic/CONFIG_AL_FIC

@@ -0,0 +1 @@
+# CONFIG_AL_FIC is not set

configs/fedora/generic/CONFIG_AMD_XGBE

@@ -1 +0,0 @@
-# CONFIG_AMD_XGBE is not set

configs/fedora/generic/CONFIG_ARCH_IOP13XX

@@ -1 +0,0 @@
-# CONFIG_ARCH_IOP13XX is not set

configs/fedora/generic/CONFIG_ARCH_IOP33X

@@ -1 +0,0 @@
-# CONFIG_ARCH_IOP33X is not set

configs/fedora/generic/CONFIG_ARCH_KS8695

@@ -1 +0,0 @@
-# CONFIG_ARCH_KS8695 is not set

configs/fedora/generic/CONFIG_ARCH_LPC32XX

@@ -1 +0,0 @@
-# CONFIG_ARCH_LPC32XX is not set

configs/fedora/generic/CONFIG_ARCH_NETX

@@ -1 +0,0 @@
-# CONFIG_ARCH_NETX is not set

configs/fedora/generic/CONFIG_ARCH_W90X900

@@ -1 +0,0 @@
-# CONFIG_ARCH_W90X900 is not set

configs/fedora/generic/CONFIG_ASIX_PHY

@@ -1 +0,0 @@
-# CONFIG_ASIX_PHY is not set

configs/fedora/generic/CONFIG_ATH11K

@@ -0,0 +1 @@
+# CONFIG_ATH11K is not set

configs/fedora/generic/CONFIG_ATH9K_PCI_NO_EEPROM

@@ -0,0 +1 @@
+CONFIG_ATH9K_PCI_NO_EEPROM=m

configs/fedora/generic/CONFIG_AX88796B_PHY

@@ -0,0 +1 @@
+CONFIG_AX88796B_PHY=m

configs/fedora/generic/CONFIG_BACKLIGHT_LCD_SUPPORT

@@ -1 +0,0 @@
-CONFIG_BACKLIGHT_LCD_SUPPORT=y

configs/fedora/generic/CONFIG_BACKLIGHT_LED

@@ -0,0 +1 @@
+CONFIG_BACKLIGHT_LED=m

configs/fedora/generic/CONFIG_BACKLIGHT_PM8941_WLED

@@ -1 +0,0 @@
-# CONFIG_BACKLIGHT_PM8941_WLED is not set

configs/fedora/generic/CONFIG_BACKLIGHT_QCOM_WLED

@@ -0,0 +1 @@
+# CONFIG_BACKLIGHT_QCOM_WLED is not set

configs/fedora/generic/CONFIG_BATMAN_ADV_SYSFS

@@ -0,0 +1 @@
+CONFIG_BATMAN_ADV_SYSFS=y

configs/fedora/generic/CONFIG_BCM84881_PHY

@@ -0,0 +1 @@
+# CONFIG_BCM84881_PHY is not set

configs/fedora/generic/CONFIG_BFQ_CGROUP_DEBUG

@@ -0,0 +1 @@
+# CONFIG_BFQ_CGROUP_DEBUG is not set

configs/fedora/generic/CONFIG_BLK_CGROUP_IOCOST

@@ -0,0 +1 @@
+CONFIG_BLK_CGROUP_IOCOST=y

configs/fedora/generic/CONFIG_BMA400

@@ -0,0 +1 @@
+# CONFIG_BMA400 is not set